[all-commits] [llvm/llvm-project] ff58fb: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff58fb1cef69c6d9e2e8889f2e72b962858a5475
      https://github.com/llvm/llvm-project/commit/ff58fb1cef69c6d9e2e8889f2e72b962858a5475
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
    M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
    M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
    M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
    M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
    M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
    M llvm/test/CodeGen/AMDGPU/trap.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
    M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AMDGPU/valu-i1.ll
    M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
    M llvm/test/CodeGen/AMDGPU/verify-sop.mir
    M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
    M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
    M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
    M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
    M llvm/test/CodeGen/AMDGPU/zext-lid.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (52) (#209778)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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