[all-commits] [llvm/llvm-project] bfc2d5: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 08:48:30 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bfc2d553401bfd69c57f848d35d5ec5952298cbb
      https://github.com/llvm/llvm-project/commit/bfc2d553401bfd69c57f848d35d5ec5952298cbb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
    M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
    M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
    M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
    M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
    M llvm/test/CodeGen/AMDGPU/lds-size.ll
    M llvm/test/CodeGen/AMDGPU/liveness.mir
    M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
    M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
    M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
    M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
    M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
    M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
    M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
    M llvm/test/CodeGen/AMDGPU/madmk.ll
    M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
    M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-m0.mir
    M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
    M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
    M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
    M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
    M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
    M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
    M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
    M llvm/test/CodeGen/AMDGPU/nullptr.ll
    M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
    M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
    M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
    M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
    M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
    M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
    M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
    M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
    M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
    M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
    M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
    M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
    M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
    M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
    M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
    M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
    M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
    M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
    M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
    M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
    M llvm/test/CodeGen/AMDGPU/select-opt.ll
    M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
    M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
    M llvm/test/CodeGen/AMDGPU/setcc-select.ll
    M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
    M llvm/test/CodeGen/AMDGPU/setcc.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
    M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
    M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (51) (#209777)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list