[all-commits] [llvm/llvm-project] f829df: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 07:39:49 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f829df1bf55e674aad2d90390b7b53dd141c2c8b
      https://github.com/llvm/llvm-project/commit/f829df1bf55e674aad2d90390b7b53dd141c2c8b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-legalize-atomic.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-fptrunc_fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-sext_inreg-to-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (46) (#209754)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list