[all-commits] [llvm/llvm-project] d0a85f: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Wed Jul 15 04:02:13 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d0a85f53b9e6c3b7146736a6b19524d1e5f738ee
      https://github.com/llvm/llvm-project/commit/d0a85f53b9e6c3b7146736a6b19524d1e5f738ee
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/use-after-free-after-cleanup-failed-vreg.ll
    M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
    M llvm/test/CodeGen/AMDGPU/usubo.ll
    M llvm/test/CodeGen/AMDGPU/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/v-cmp-cse-across-loop.mir
    M llvm/test/CodeGen/AMDGPU/v1024.ll
    M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
    M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
    M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
    M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
    M llvm/test/CodeGen/AMDGPU/v_mac.ll
    M llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
    M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/v_pack.ll
    M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
    M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
    M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-vgpr-msb-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane16var-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca-atomic.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
    M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
    M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
    M llvm/test/CodeGen/AMDGPU/vector_range_metadata.ll
    M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/vectorize-buffer-fat-pointer.ll
    M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
    M llvm/test/CodeGen/AMDGPU/vectorize-loads.ll
    M llvm/test/CodeGen/AMDGPU/vectorize-unroll-metadata.ll
    M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
    M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
    M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
    M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
    M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
    M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
    M llvm/test/CodeGen/AMDGPU/verify-image.mir
    M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
    M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
    M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent-invalid.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250-t16.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36) (#209600)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)

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