[all-commits] [llvm/llvm-project] ea56bc: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 11:56:33 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea56bc30bdabf00e401422f49e9588f1b5ff5e73
      https://github.com/llvm/llvm-project/commit/ea56bc30bdabf00e401422f49e9588f1b5ff5e73
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
    M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/save-fp.ll
    M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
    M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
    M llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
    M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
    M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
    M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
    M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
    M llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir
    M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
    M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
    M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
    M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
    M llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
    M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
    M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
    M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
    M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
    M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
    M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
    M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
    M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
    M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
    M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-commute.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-sext.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave64.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
    M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
    M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
    M llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (30) (#209559)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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