[all-commits] [llvm/llvm-project] 527396: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 11:53:53 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 527396dd7c7370b1649ade49ceb48e48f6f26de1
      https://github.com/llvm/llvm-project/commit/527396dd7c7370b1649ade49ceb48e48f6f26de1
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
    M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
    M llvm/test/CodeGen/AMDGPU/reduction.ll
    M llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
    M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
    M llvm/test/CodeGen/AMDGPU/register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
    M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
    M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
    M llvm/test/CodeGen/AMDGPU/rel32.ll
    M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
    M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
    M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
    M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave64-feature.ll
    M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
    M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
    M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
    M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
    M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
    M llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
    M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
    M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
    M llvm/test/CodeGen/AMDGPU/required-export-priority.mir
    M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
    M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
    M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
    M llvm/test/CodeGen/AMDGPU/ret.ll
    M llvm/test/CodeGen/AMDGPU/ret_jump.ll
    M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
    M llvm/test/CodeGen/AMDGPU/returnaddress.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
    M llvm/test/CodeGen/AMDGPU/rotate-add.ll
    M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
    M llvm/test/CodeGen/AMDGPU/rotl.ll
    M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
    M llvm/test/CodeGen/AMDGPU/rotr.ll
    M llvm/test/CodeGen/AMDGPU/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
    M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
    M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
    M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
    M llvm/test/CodeGen/AMDGPU/s_code_end.ll
    M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
    M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
    M llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll
    M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
    M llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll
    M llvm/test/CodeGen/AMDGPU/sad.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (29) (#209558)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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