[all-commits] [llvm/llvm-project] f77162: [Clang][Driver] Parallelize device cc1 jobs for of...
Daniil Kovalev via All-commits
all-commits at lists.llvm.org
Mon Jul 13 07:05:26 PDT 2026
Branch: refs/heads/users/kovdan01/ptrauth-module-flags-mismatch
Home: https://github.com/llvm/llvm-project
Commit: f77162dd86a4abb102e6f9c717ab4e64497ef948
https://github.com/llvm/llvm-project/commit/f77162dd86a4abb102e6f9c717ab4e64497ef948
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Driver/Job.h
M clang/lib/Driver/Compilation.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
A clang/test/Driver/offload-parallel-device-cc1.cu
Log Message:
-----------
[Clang][Driver] Parallelize device cc1 jobs for offload arches
[Clang][Driver] Parallelize device cc1 jobs for offload arches
Large offload builds can target many device architectures. A common
ROCm build can target around ten `--offload-arch=` values. For a large
single translation unit, the offload device cc1 work before
clang-linker-wrapper can become a build-time bottleneck. Those
per-architecture jobs are independent, but the driver ran them serially,
so `--offload-jobs=` only helped the later wrapper work.
Borrow the parallel job mechanism used by clang-linker-wrapper for the
pre-wrapper device cc1 jobs. Device job construction marks eligible
compile and backend jobs with an offload parallel group. The generic
executor only consumes that opt-in metadata for adjacent device jobs
with distinct bound architectures.
The parallel path is disabled for driver-side output modes and callbacks
so existing serial output handling is preserved. This is NFC for
non-offload compilation.
Commit: 20429870a5ba92762fe0135a207670a1d1d052e2
https://github.com/llvm/llvm-project/commit/20429870a5ba92762fe0135a207670a1d1d052e2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/lib/Driver/Driver.cpp
Log Message:
-----------
clang: Remove extra space and braces in flang check (#208714)
Commit: 9a1fe8e03c0499990b820d0151eabe60da864c9a
https://github.com/llvm/llvm-project/commit/9a1fe8e03c0499990b820d0151eabe60da864c9a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
AMDGPU/GlobalISel: Switch CallLowering to extended LLTs (#208268)
Stop using LLT::scalar for argument lowering in AMDGPUCallLowering.
Mostly straightforward, worth noting that some places now require
a bitcast between integer and float.
Commit: 62bf9d924cb7b5b59bbacf42dfb80c6671671e86
https://github.com/llvm/llvm-project/commit/62bf9d924cb7b5b59bbacf42dfb80c6671671e86
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/include/__memory/shared_ptr.h
M libcxx/test/support/min_allocator.h
Log Message:
-----------
[libc++] Fix shared_ptr not accepting allocators with explicit conversions (#208439)
Allocators are only required to be explicitly convertible between
different types. `shared_ptr` currently requires implicit conversions,
however.
This is a regression introduced by #200401.
Commit: 016605d7eceb269a38a0cd3da8bf9cdd39e04f48
https://github.com/llvm/llvm-project/commit/016605d7eceb269a38a0cd3da8bf9cdd39e04f48
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
A llvm/test/CodeGen/AArch64/get-active-lane-mask-extract-nosve.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
Log Message:
-----------
[AArch64][CodeGen] Split wide active lane mask into smaller masks if preferred (#202909)
Extends the AArch64 specific DAG combine for get_active_lane_mask to split
up a single wide active lane mask used by a series of subvector extracts
into several smaller get_active_lane_mask nodes if preferred.
This PR is part of a series of changes leading to the use of wide active
lane masks as the canonical form in LoopVectorize when choosing to
interleave and tail-fold loops. #193757 is the original PR where this was
discussed.
The motivation for this PR is to leave the decision on which form of the IR
to use up to the target. This will remove the need for more complex decisions
and transformations during vectorisation to query whether it's best to create
a single mask + extracts or multiple smaller masks.
Commit: 68ee7f096e21837f3d025e5e4ac6bb761588a409
https://github.com/llvm/llvm-project/commit/68ee7f096e21837f3d025e5e4ac6bb761588a409
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/sorting/is_heap.bench.cpp
Log Message:
-----------
[libc++] Add benchmarks for std::is_heap and std::is_heap_until (#207045)
This continues expanding our set of benchmarks.
Assisted by Claude
Commit: d600c925f4df79a008ddbb6c1862e1d8b0ee0686
https://github.com/llvm/llvm-project/commit/d600c925f4df79a008ddbb6c1862e1d8b0ee0686
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/TokenConcatenation.cpp
A clang/test/Lexer/dollar-idents.cpp
Log Message:
-----------
[Clang] Supports dollars in UDLs and pp-numbers (#208490)
When dollars are supported in identifiers, we should be consistent.
Fixes #173985
Fixes #171190
Commit: d6ef81ce4e18563c49116fc82502e4ef237a201d
https://github.com/llvm/llvm-project/commit/d6ef81ce4e18563c49116fc82502e4ef237a201d
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxxabi/include/cxxabi.h
M libcxxabi/src/abort_message.h
M libcxxabi/src/cxa_aux_runtime.cpp
M libcxxabi/src/cxa_default_handlers.cpp
M libcxxabi/src/cxa_exception.cpp
M libcxxabi/src/cxa_handlers.cpp
M libcxxabi/src/cxa_handlers.h
M libcxxabi/src/cxa_personality.cpp
M libcxxabi/src/cxa_vector.cpp
M libcxxabi/src/cxa_virtual.cpp
Log Message:
-----------
[libc++abi][NFC] Use C++11 spelling of [[noreturn]] (#207344)
We already use the C++11 spelling for libc++, and there isn't much of a
reason not to use it. Except for the changes in `cxxabi.h` this is even
fully standard code.
Commit: f66516456d3cf4cff2c1ab6d83afac6e2f9e4c26
https://github.com/llvm/llvm-project/commit/f66516456d3cf4cff2c1ab6d83afac6e2f9e4c26
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Lex/PPDirectives.cpp
A clang/test/Lexer/invalid-directive.cpp
Log Message:
-----------
[clang] Don't crash in invalid #module directive (#208695)
The following preprocessing directive is not a C++ module directive,
don't handle it in C++ module subroutine.
```cpp
#module
```
Fixes https://github.com/llvm/llvm-project/issues/179220.
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: f2dfbf06f7db1a3cace4beb9f65d5a7f6a8b6235
https://github.com/llvm/llvm-project/commit/f2dfbf06f7db1a3cace4beb9f65d5a7f6a8b6235
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/Mips/cconv/vector.ll
M llvm/test/CodeGen/Mips/cmov.ll
M llvm/test/CodeGen/NVPTX/i1-select.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
M llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
M llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
M llvm/test/CodeGen/X86/isel-select-cmov.ll
M llvm/test/CodeGen/X86/select-constant-xor.ll
M llvm/test/CodeGen/X86/select-mmx.ll
A llvm/test/CodeGen/X86/select-of-load-poison.ll
Log Message:
-----------
[SDAG] Freeze condition in select of load fold (#208683)
When converting `select cond, (load p1), (load p2)` to `load (select
cond, p1, p2)`, if `cond` is poison, originally this would result in a
`poison` result, while after the transform it would result in a load of
poison, which is immediate UB. Fix this by freezing the condition.
Fixes https://github.com/llvm/llvm-project/issues/208611.
Commit: 87901900fc10f1a3cdf04b20fef371562bf31d34
https://github.com/llvm/llvm-project/commit/87901900fc10f1a3cdf04b20fef371562bf31d34
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/global-var-intrinsic.ll
A llvm/test/CodeGen/SPIRV/pointers/fun-ptr-as-data-load-store.ll
M llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll
M llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll
M llvm/test/CodeGen/SPIRV/transcoding/global_block.ll
Log Message:
-----------
[SPIR-V] Diagnose function used as data pointer without SPV_INTEL_function_pointers (#207347)
Commit: 53130f3398014dd78ff1ce3d6b028f8cadade3ca
https://github.com/llvm/llvm-project/commit/53130f3398014dd78ff1ce3d6b028f8cadade3ca
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
AMDGPU/GlobalISel: Switch legalizer custom lowering to extended LLTs (#208269)
Stop using LLT::scalar in custom lowering in AMDGPULegalizerInfo.
The exception is S1 since it seems to work fine.
Does not change legalizer actions. In general this is intended as a
mechanical step in amdgpu's switch to extended LLTs, just try to
avoid LLT::scalar in instructions generated after IRtranslator,
since it seems like a step in the right direction. Some tests remove
-global-isel-abort=2 since GIM_SwitchType no longer fails on
LLT::scalar. Exposes a couple of new failures with 16bit bitcast.
Commit: 8544134f118dcbd1543e29c1ae6b5ac019d4a138
https://github.com/llvm/llvm-project/commit/8544134f118dcbd1543e29c1ae6b5ac019d4a138
Author: Zain <beingzainsv at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M compiler-rt/lib/builtins/hexagon/dffma.S
A compiler-rt/test/builtins/Unit/hexagon_fmadf5_test.c
Log Message:
-----------
[compiler-rt][hexagon] Fix `__hexagon_fmadf5` overflow under directed rounding (#207373)
The overflow path in `__hexagon_fmadf5` computed the round-mode
predicate (inf vs. largest-finite) into p0, but then overwrote p0 with
`dfcmp.eq(ATMP,ATMP)` before consuming it. Since ATMP is +inf,
`dfcmp.eq(ATMP,ATMP)` is always true, so CTMP was unconditionally set to
infinity and the rounding-mode decision was discarded.
As a result, a finite-magnitude overflow returned +/-inf in every
rounding mode.
Fix: Fuse the selection into a single packet so the round-mode predicate
selects inf-vs-DBL_MAX, and recompute p0 = dfcmp.eq afterwards only to
raise the exception flags which matching the correct sequence already
used
by dfdiv.S.
Also, I've added a regression test (`hexagon_fmadf5_test.c`) covering
FMA special
cases: NaN propagation, invalid operations (0*inf, inf+(-inf)), infinity
propagation, exact results, signed-zero of exact sums, the single-
rounding property, overflow under all rounding modes, and subnormal
results.
Please let me know if this test for the builtin is in the right place,
or if it should be in some place else.
Assisted by: GPT 5.5
Signed-off-by: Zain Siddavatam <zsiddava at qti.qualcomm.com>
Commit: 26d1c4f05ad9b715336a1cdc8be9257f6e30038d
https://github.com/llvm/llvm-project/commit/26d1c4f05ad9b715336a1cdc8be9257f6e30038d
Author: Yitzhak Mandelbaum <ymand at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Fix bug in transfer function of CK_BaseToDerived (#208726)
Bug fix. In the transfer function (one of the cast cases), the loop
adding synthetic fields to the derived record storage location was incorrectly
nested inside the loop that iterates over modeled fields (`getModeledFields`).
If the derived class has 0 modeled fields, `getModeledFields(Derived)`
is empty. Consequently, synthetic fields were never added to the storage
location, causing an assertion failure in `StorageLocation::getSyntheticField`
when initializing field values.
This patch moves the synthetic fields loop outside of the modeled fields loop
and adds a regression unit test in `TransferTest.cpp`.
Commit: 3018fd74d14d9b9c25f7931e6ef51ee5f203a66b
https://github.com/llvm/llvm-project/commit/3018fd74d14d9b9c25f7931e6ef51ee5f203a66b
Author: Jerry Dang <kuroyukiasuna at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/framelayout-fpr128-csr.ll
M llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
Log Message:
-----------
[AArch64] Stop determineCalleeSaves double counting registers with saved supers (#208521)
`determineCalleeSaves()` in `AArch64FrameLowering` double counts the
D8-D15/Q8-Q1 overlap - fixed by skipping sub-registers whose super is
saved.
Fixes #204564
Commit: 73976bc0e88a6fb5e8213726074f2b0474899499
https://github.com/llvm/llvm-project/commit/73976bc0e88a6fb5e8213726074f2b0474899499
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A lldb/test/API/commands/command/script/import/import-error/Makefile
A lldb/test/API/commands/command/script/import/import-error/TestImportError.py
A lldb/test/API/commands/command/script/import/import-error/fail_importerror.py
A lldb/test/API/commands/command/script/import/import-error/fail_valueerror.py
R lldb/test/API/commands/command/script/import/rdar-12586188/Makefile
R lldb/test/API/commands/command/script/import/rdar-12586188/TestRdar12586188.py
R lldb/test/API/commands/command/script/import/rdar-12586188/fail12586188.py
R lldb/test/API/commands/command/script/import/rdar-12586188/fail212586188.py
A lldb/test/API/commands/expression/int128/Test128BitsInteger.py
A lldb/test/API/commands/expression/int128/main.c
R lldb/test/API/commands/expression/rdar42038760/TestScalarURem.py
R lldb/test/API/commands/expression/rdar42038760/main.c
R lldb/test/API/commands/expression/rdar44436068/Test128BitsInteger.py
R lldb/test/API/commands/expression/rdar44436068/main.c
A lldb/test/API/commands/expression/urem-sign/TestScalarURem.py
A lldb/test/API/commands/expression/urem-sign/main.c
R lldb/test/API/functionalities/data-formatter/summary-string-onfail/Test-rdar-9974002.py
A lldb/test/API/functionalities/data-formatter/summary-string-onfail/TestSummaryStringOnFail.py
A lldb/test/API/lang/objc/coalesced-cf-types/Makefile
A lldb/test/API/lang/objc/coalesced-cf-types/TestCoalescedCFTypes.py
A lldb/test/API/lang/objc/coalesced-cf-types/main.m
A lldb/test/API/lang/objc/dynamic-type-children/Makefile
A lldb/test/API/lang/objc/dynamic-type-children/TestDynamicTypeChildren.py
A lldb/test/API/lang/objc/dynamic-type-children/main.m
R lldb/test/API/lang/objc/rdar-10967107/Makefile
R lldb/test/API/lang/objc/rdar-10967107/TestRdar10967107.py
R lldb/test/API/lang/objc/rdar-10967107/main.m
R lldb/test/API/lang/objc/rdar-12408181/Makefile
R lldb/test/API/lang/objc/rdar-12408181/TestRdar12408181.py
R lldb/test/API/lang/objc/rdar-12408181/main.m
Log Message:
-----------
[lldb][test] Get rid of radar references in test names (#208673)
No one outside Apple can access the associated radars and understand
what these tests are about. These tests have other problems, but this
makes them at least possible to comprehend for everyone.
Commit: 5394e2aec901f34dc3f92976529dab9ce7829d93
https://github.com/llvm/llvm-project/commit/5394e2aec901f34dc3f92976529dab9ce7829d93
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/test/API/lang/c/unions/TestUnionMembers.py
M lldb/test/API/lang/c/unions/main.c
Log Message:
-----------
[lldb][test] Modernize and expand C union test (#208662)
Replace most of the test's setup code with modern test utils and expand
the test case to cover more common or potentially problematic uses of
unions.
Commit: 54aa96fdd08c79bbd8143cbbd3b2fcb95b1377fc
https://github.com/llvm/llvm-project/commit/54aa96fdd08c79bbd8143cbbd3b2fcb95b1377fc
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A lldb/test/API/lang/cpp/builtin_types/long_int/Makefile
A lldb/test/API/lang/cpp/builtin_types/long_int/TestLongIntTypes.py
A lldb/test/API/lang/cpp/builtin_types/long_int/main.cpp
Log Message:
-----------
[lldb][test] Add a new test for long types (#208447)
This is a new modern test for long types that replaces the test logic
from `API/types` test that is about to be deleted. This is a distinct
test from the normal integer types due to long depending on data models
which change depending on platform.
See also #208402
assisted-by: claude
Commit: a465ef6968f30abacde4f2d526b98b206b9a149f
https://github.com/llvm/llvm-project/commit/a465ef6968f30abacde4f2d526b98b206b9a149f
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/Makefile
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/TestRecursiveTypesFuncPtrs.py
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/main.cpp
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/recursive_types.cpp
Log Message:
-----------
[lldb][test] Add a new test for recursive types (#208449)
This is a new modern test for recursive types that self-reference
themselves via function pointers.
This replaces the test logic from `API/types` test that is about to be
deleted.
See also #208402
assisted-by: claude
Commit: 2c0541b661c98467caf0b70d147ff8ffa34a6331
https://github.com/llvm/llvm-project/commit/2c0541b661c98467caf0b70d147ff8ffa34a6331
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A lldb/test/API/lang/cpp/builtin_types/char/Makefile
A lldb/test/API/lang/cpp/builtin_types/char/TestCharTypes.py
A lldb/test/API/lang/cpp/builtin_types/char/main.cpp
Log Message:
-----------
[lldb][test] Add a new test for char types (#208442)
This is a new modern test for char types that replaces the test logic
from `API/types` test that is about to be deleted.
See also #208402
assisted-by: claude
Commit: c8b02ba5ac7a37c4fa0100431b357da74f1b200f
https://github.com/llvm/llvm-project/commit/c8b02ba5ac7a37c4fa0100431b357da74f1b200f
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/test/API/lang/c/blocks/TestBlocks.py
M lldb/test/API/lang/c/blocks/main.c
Log Message:
-----------
[lldb][test] Expand blocks test (#208406)
This moves some of the tested logic from the `types/` test that is about
to be deleted to the already existing c/blocks test.
See also #208402
assisted-by: claude
Commit: ff5363bf29ba9f426b241abb9e72d12d9b785221
https://github.com/llvm/llvm-project/commit/ff5363bf29ba9f426b241abb9e72d12d9b785221
Author: Bartosz Wiklak <bwiklak at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/index/remote/marshalling/Marshalling.cpp
M clang-tools-extra/clangd/index/remote/server/Server.cpp
A clang-tools-extra/clangd/test/remote-index/cross-platform-root.test
M clang-tools-extra/clangd/unittests/remote/MarshallingTests.cpp
Log Message:
-----------
[clangd][remote] Add clangd-index-server support for cross platform indexes (#207202)
The main use case is to serve windows index on linux server.
Without this change server wasn't able to check if project_root path is
absolute and was closed with error: "Index root should be an absolute
path."
This change is meant to solve issue:
https://github.com/clangd/clangd/issues/2646
Commit: 72b8db717ac2a5dfb03755b592e796a61c7db60b
https://github.com/llvm/llvm-project/commit/72b8db717ac2a5dfb03755b592e796a61c7db60b
Author: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] add consistent stride verification to masked load/store and gather/scatter ops (#205869)
Extend negative stride checks to MaskedLoadOp, MaskedStoreOp, GatherOp,
and ScatterOp to match LoadOp and StoreOp behavior.
Depends on: https://github.com/llvm/llvm-project/pull/204611.
AI Disclaimer: I used AI for the tests.
@banach-space @dcaballe If you look at the latest commit, you can see
why the integration tests were failing in #204842. Those two calls were
added in this PR, I sincerely apologize to you!
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Commit: b12c64e0a26e9d0a45bc013bb1740e16100a700c
https://github.com/llvm/llvm-project/commit/b12c64e0a26e9d0a45bc013bb1740e16100a700c
Author: Marquis <98034810+marquisburg at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/emulate-narrow-type-unsupported.mlir
Log Message:
-----------
[mlir][vector] Fix crash on untraceable masks in getCompressedMaskOp (#207299)
The loop tracing a mask back to its creation op assumed the chain always
ends at a create_mask/constant_mask/arith.constant, a block-argument
mask made it fall through to isa<> on a null op (segfault), and any
other unhandled defining op spun it forever.
Fixes #206928
Claude Fable 5 did assist with this.
Commit: 6211a71358a4d23d810a0bca526ea28f98e07996
https://github.com/llvm/llvm-project/commit/6211a71358a4d23d810a0bca526ea28f98e07996
Author: Adam Scott <adamscott200322 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-load-store.ll
M llvm/test/CodeGen/X86/avx512-mask-op.ll
M llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
A llvm/test/CodeGen/X86/buildvec-strided-loads.ll
M llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
M llvm/test/CodeGen/X86/vector-compress.ll
Log Message:
-----------
[X86] EltsFromConsecutiveLoads - handle trunc(wideload()) patterns (#199371)
The existing path emits N x vpinsrb for buildvecs whose elements are
loads at a regular byte stride larger than the element size:
```asm
movzbl 216(%rsp), %eax
vmovd %eax, %xmm0
vpinsrb $1, 224(%rsp), %xmm0, %xmm0
vpinsrb $2, 232(%rsp), %xmm0, %xmm0
...
vpinsrb $15, 336(%rsp), %xmm0, %xmm0
```
This patch adds a strided-load path to EltsFromConsecutiveLoads that
folds these into wide load(s) + vector truncation:
```asm
vmovdqu64 216(%rsp), %zmm0
vmovdqu64 280(%rsp), %zmm1
vpmovqb %zmm0, %xmm0
vpmovqb %zmm1, %xmm1
vpunpcklqdq %xmm1, %xmm0, %xmm0
```
The combine detects element loads at a uniform power of 2 byte stride
larger than the element size, picks a wide-load size (ZMM/YMM/XMM) from
the buildvec lane count, and emits X86ISD::VTRUNC for partial pieces or
ISD::TRUNCATE for full pieces. Multi-piece results recombine with
pairwise shuffle (partial) or CONCAT_VECTORS (full).
This simplifies 12 existing X86 codegen tests where many-arg functions
hit the strided pattern naturally.
Also created a new test file with 14 tests covering:
- 3 cases with 4-byte stride: v16i8, v8i16, and v32i8 destinations
(single-piece full and 2-piece full with CONCAT_VECTORS)
- 3 cases with 8-byte stride and partial truncation: v16i8 (2-piece
pairwise), v16i16 (2-piece pairwise), v32i8 (4-piece pairwise tree)
- 1 sub-xmm destination (v8i8) that widens to v16i8
- 3 partial-fill destinations of v32i8: trailing zero padding,
INSERT_SUBVECTOR placement at lane 16, vector shuffle placement at lane
8
- 1 reverse-stride case
- 3 negative tests: volatile loads, non-uniform stride, sparse loaded
positions with interleaved undefs
Fixes #198175
Commit: 9d1c207b18fea9bacbe921d182be647d75bf3e95
https://github.com/llvm/llvm-project/commit/9d1c207b18fea9bacbe921d182be647d75bf3e95
Author: Guy David <guyda96 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/neg-sign-masked-and.ll
Log Message:
-----------
[AArch64] Reassociate neg (and X, M) with an all-0/1's mask M (#207671)
Commit: 7138e1f3e2170de61e10f2d1fae03690de591548
https://github.com/llvm/llvm-project/commit/7138e1f3e2170de61e10f2d1fae03690de591548
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
A llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/i128-switch-condition-type.ll
A llvm/test/CodeGen/SPIRV/switch-odd-width-condition.ll
Log Message:
-----------
[SPIR-V] Fix crash on switch with odd-width condition type (#208026)
getPreferredSwitchConditionType called getSimpleVT unconditionally,
which asserts on extended EVTs like i31
Return i1 for non-simple types to keep CodeGenPrepare from widening the
condition
Commit: 4c6646f1e497e25cb4e6a633ce565c864e66de93
https://github.com/llvm/llvm-project/commit/4c6646f1e497e25cb4e6a633ce565c864e66de93
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/alloca.ll
A llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/comdat.ll
M llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
M llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-func.ll
M llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll
M llvm/test/CodeGen/AMDGPU/hsa.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
A llvm/test/CodeGen/AMDGPU/lower-kernargs-lds-ptr.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-invalid-signature.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-kernel-arguments.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll
M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-wcg-attributes.mir
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-crash.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void.ll
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
Log Message:
-----------
AMDGPU: Manually convert some tests to use subarches (#208638)
Commit: 618ac1068f42a03eda1a2e4d2e160ae441665302
https://github.com/llvm/llvm-project/commit/618ac1068f42a03eda1a2e4d2e160ae441665302
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Log Message:
-----------
AMDGPU/GlobalISel: Fix buildbot failure for unused variable (used in assert) (#208743)
Commit: 8834939829a3e3cfee2b98a3db6f12d068686ed8
https://github.com/llvm/llvm-project/commit/8834939829a3e3cfee2b98a3db6f12d068686ed8
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/setcc-redundant.ll
Log Message:
-----------
[M68k] Update tests (#208748)
After f2dfbf06f7db1a3cace4beb9f65d5a7f6a8b6235.
Commit: ef3ac7a77a06442ab2ac57f5417cfa9ded7a3b46
https://github.com/llvm/llvm-project/commit/ef3ac7a77a06442ab2ac57f5417cfa9ded7a3b46
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
A lldb/test/API/driver/longpath/Makefile
A lldb/test/API/driver/longpath/TestLongPathDriver.py
A lldb/test/API/driver/longpath/main.c
A lldb/test/API/functionalities/longpath/Makefile
A lldb/test/API/functionalities/longpath/TestLongPath.py
A lldb/test/API/functionalities/longpath/main.c
A lldb/test/API/tools/lldb-dap/longpath/Makefile
A lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
A lldb/test/API/tools/lldb-dap/longpath/main.c
Log Message:
-----------
[lldb][Windows] Support modules with long paths (#206099)
`PlatformWindows::DoLoadImage` injected a 261-byte buffer for the loaded
module path. Longer paths would be truncated and fail to load. This
patch adds a growing buffer (up to the NT limit) which is used only when
`GetModuleFileNameA` reports truncation, re-querying without taking an
extra reference on the module.
This patch also adds 3 tests for lldb, lldb-driver and the SBAPI. They
are really regression tests which break if long path support regresses.
Requires:
- https://github.com/llvm/llvm-project/pull/206046
- https://github.com/llvm/llvm-project/pull/206060
Commit: d58b0562a340b043ed83b0fb4375e89ed74fc621
https://github.com/llvm/llvm-project/commit/d58b0562a340b043ed83b0fb4375e89ed74fc621
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/test/OpenMP/error_codegen.cpp
M compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-warnings.ll
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVIRReader.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/test/Bitcode/DIModule-fortran-external-module.ll
A llvm/test/Bitcode/upgrade-cu-static-locals.ll
A llvm/test/Bitcode/upgrade-cu-static-locals.ll.bc
M llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
M llvm/test/CodeGen/BPF/BTF/static-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var.ll
M llvm/test/CodeGen/BPF/dwarfdump.ll
M llvm/test/CodeGen/PowerPC/pr24546.ll
M llvm/test/CodeGen/X86/dbg-distringtype-uint.ll
M llvm/test/DebugInfo/COFF/fortran-basic.ll
M llvm/test/DebugInfo/COFF/fortran-contained-proc.ll
M llvm/test/DebugInfo/COFF/global_visibility.ll
M llvm/test/DebugInfo/COFF/type-quals.ll
M llvm/test/DebugInfo/Generic/2009-11-05-DeadGlobalVariable.ll
M llvm/test/DebugInfo/Generic/global-var-in-abstract-lexical-block.ll
M llvm/test/DebugInfo/Generic/inlined-static-var.ll
A llvm/test/DebugInfo/Generic/verifier-invalid-dicompileunit.ll
M llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll
M llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
M llvm/test/DebugInfo/X86/DW_AT_specification.ll
M llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll
M llvm/test/DebugInfo/X86/dimodule-external-fortran.ll
M llvm/test/DebugInfo/X86/distringtype.ll
M llvm/test/DebugInfo/X86/global-sra-struct-fit-segment.ll
M llvm/test/DebugInfo/X86/global-sra-struct-part-overlap-segment.ll
M llvm/test/DebugInfo/X86/gnu-public-names.ll
A llvm/test/DebugInfo/X86/lexical-block-static-var.ll
M llvm/test/DebugInfo/X86/namelist1.ll
M llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
M llvm/test/DebugInfo/duplicate_dbgvalue.ll
M llvm/test/Instrumentation/InstrProfiling/debug-info-correlate-bitmap.ll
M llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
M llvm/test/Transforms/Util/clone-dicompileunit.ll
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/ThreadLocalStorage.ll
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialectBytecode.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
[DebugMetadata][DwarfDebug][CodeView] Support function-local static variables in lexical block scopes (6/7) (#187927)
RFC
https://discourse.llvm.org/t/rfc-dwarfdebug-fix-and-improve-handling-imported-entities-types-and-static-local-in-subprogram-and-lexical-block-scopes/68544
Similar to imported declarations and types, the patch tracks
function-local static variables (globals in terms of LLVM IR) in
DISubprogram's 'retainedNodes'. DwarfDebug is adjusted in accordance
with the aforementioned metadata change and provided a support of static
locals scoped by a lexical block. CodeViewDebug is modified to collect
global variables from DISubprogram's 'retainedNodes' too.
The patch assumes that DICompileUnit's 'globals' no longer tracks static
locals and DwarfDebug would assert if any locally-scoped variables get
placed there.
This change has already been reviewed in
https://reviews.llvm.org/D144008, but I’m opening a new PR because it
has been a while since it was approved. Additional logic was added to
CloneFunction to deal with DISubprograms that have static locals: if
such a subprogram is cloned, DIGlobalVariableExpressions are removed
from retainedNodes of the clone. This is consistent with the current
behavior, in which DIGlobalVariableExpressions are not cloned.
Authored-by: Kristina Bessonova <kbessonova at accesssoftek.com>
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: b4cf9c7c89ec541495c38c4e34fa8967713bf843
https://github.com/llvm/llvm-project/commit/b4cf9c7c89ec541495c38c4e34fa8967713bf843
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[MLIR][Vector] Relax shape_cast unrolling to per-reassociation-group contiguity (#205684)
UnrollShapeCastPattern previously only unrolled a vector.shape_cast when
the target unroll tile was contiguous in the whole result vector
(isContiguous(targetShape, resultShape)). This rejected valid cases such
as:
```mlir
%0 = vector.shape_cast %src : vector<8x32xf8> to vector<8x1x32xf8> // target tile [8, 1, 4]
%1 = vector.shape_cast %src : vector<8x32x32xf8> to vector<256x32xf8> // target tile [16, 4]
```
This PR factors the source and result shapes of a shape_cast into
independent reassociation groups — maximal aligned source/result dim
ranges that hold equal element counts:
```
- 8x32 → 8x1x32 ⇒ groups {8 ↔ 8x1}, {32 ↔ 32}
- 8x32x32 → 256x32 ⇒ groups {8x32 ↔ 256}, {32 ↔ 32}
```
Instead of requiring the target tile to be contiguous in the whole
result vector, it only checks that the tile is contiguous within each
group.
This criterion is correct because a shape_cast preserves row-major
linear order. The groups partition the dimensions into blocks whose
element ranges don't overlap, so the global linear index breaks down
into one independent sub-index per group. A tile that is contiguous
within each group therefore corresponds to a slice that is contiguous
within each group of both the source and result.
Assist-by-Claude
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: bd97ce04dd43e4345d5930946eaba1623782f0d5
https://github.com/llvm/llvm-project/commit/bd97ce04dd43e4345d5930946eaba1623782f0d5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-compress.ll
Log Message:
-----------
[X86] vector-compress.ll - test with x86-64 levels not raw AVX levels (#208745)
Prep work for VECREDUCE_ADD lowering support (VECTOR_COMPRESS expansion
creates VECREDUCE_ADD nodes)
Test with/without vbmi2 to show the terrible v32i8/v64i8 compress
codegen on x86-64-v4 targets
Commit: 0fa1ae1a8bb10f6d237a411e9d343c5d07e34d23
https://github.com/llvm/llvm-project/commit/0fa1ae1a8bb10f6d237a411e9d343c5d07e34d23
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
Log Message:
-----------
AMDGPU/GlobalISel: Switch RegBankLegalize lowering to extended LLTs (#208270)
Stop using LLT::scalar for lowering in AMDGPURegBankLegalizeHelper
Affects integer lowering code for RegBankLLTMappingApplyID and
custom cpp for LoweringMethodID.
Commit: c5fbabb36e9be13e001cc6b96bfef7b4db33210d
https://github.com/llvm/llvm-project/commit/c5fbabb36e9be13e001cc6b96bfef7b4db33210d
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-variant.cpp
A flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
A flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
A flang/test/Semantics/OpenMP/metadirective-loop-sequence.f90
Log Message:
-----------
[flang][OpenMP] Semantic checks for metadirective loop nests (#207088)
A loop-associated metadirective variant (`do`, `simd`, ...) is only
resolved during lowering, so it is never checked as a loop construct
during semantic analysis. A malformed or non-canonical associated nest
therefore reaches lowering, which assumes a canonical nest.
This patch validates the nest that follows such a variant (the next
executable construct) during semantics, reusing the diagnostics of a
real loop-associated construct. Each applicable variant is checked
against it:
* Canonical loop: the affected loop must be a canonical DO loop, so a
`DO WHILE`, a pre-6.0 `DO CONCURRENT`, or a `DO` without loop control is
rejected.
* Nest depth: `collapse(n)` and `ordered(n)` must not exceed the depth
of the associated loop nest.
* Rectangularity: loops that must be rectangular (e.g. under `tile`) may
not have bounds that depend on an outer loop's variable.
A loop-associated variant may also have no loop nest at all. This
happens when the metadirective ends the execution part or a non-loop
construct follows it. Such a variant is rejected like a bare loop
directive with no associated loop.
Only variants that could be selected are checked: when a target is
known, a WHEN variant whose device or implementation selector cannot
match it is skipped (runtime `user` conditions never cause a skip).
Part of the feature work for #188820. Builds on top of
[#193664](https://github.com/llvm/llvm-project/issues/193664) and
[#194424](https://github.com/llvm/llvm-project/pull/194424).
Assisted with Copilot.
Commit: 23d7ed226e3e70e6f116457a77e5ec24396186f6
https://github.com/llvm/llvm-project/commit/23d7ed226e3e70e6f116457a77e5ec24396186f6
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
A llvm/test/CodeGen/Hexagon/pr196966.ll
Log Message:
-----------
[Hexagon] Add S2_pstorerf{t,f}_io to isValidOffset (PR196966) (#208616)
The predicated store-high-halfword opcodes S2_pstorerft_io and
S2_pstorerff_io share the memh(Rs32+#u6:1) encoding with
S2_pstorerh{t,f}_io but were missing from
HexagonInstrInfo::isValidOffset. This caused an llvm_unreachable in
HexagonOptAddrMode when it queried the offset range for these opcodes.
Fixes #196966
Commit: 114f2675514ffb8ab0e9092bb3071e3fdb31dad3
https://github.com/llvm/llvm-project/commit/114f2675514ffb8ab0e9092bb3071e3fdb31dad3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-ptr-to-itself.ll
Log Message:
-----------
[NFC][SPIR-V] Enable spirv-val checks fixed after accepting Generic casts to/from CodeSectionINTEL storage class (#208739)
https://github.com/KhronosGroup/SPIRV-Tools/pull/6787
Commit: 034fd4c90d5b5a991048e62193ed74f00d504d69
https://github.com/llvm/llvm-project/commit/034fd4c90d5b5a991048e62193ed74f00d504d69
Author: Ying Chen <chenying at inchitech.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/MC/RISCV/rv32-only-csr-names.s
Log Message:
-----------
[RISCV] Fix state enable CSR coverage in rv32-only-csr-names.s (#208603)
Fix duplicate `mstateen3h` and `hstateen3h` test entries and add the
missing RV64 rejection coverage for `mstateen2h` and `hstateen2h`.
Commit: 54b5b78a6332a0faa13f2297a5b3751a1d7544a9
https://github.com/llvm/llvm-project/commit/54b5b78a6332a0faa13f2297a5b3751a1d7544a9
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/StackMaps.h
M llvm/lib/CodeGen/StackMaps.cpp
Log Message:
-----------
[CodeGen] Use natural type for StackMaps::ConstPool. NFC. (#208732)
This is mostly just a revert of e839965faa22 which switched to using
unsigned types to work around problems with DenseMap sentinel values.
Since DenseMaps no longer have sentinels we can use signed types to
match the values that are stored in the map.
Commit: 74cc7fdcc850416b5760b8245c6f80e468220732
https://github.com/llvm/llvm-project/commit/74cc7fdcc850416b5760b8245c6f80e468220732
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/ConstantPools.h
Log Message:
-----------
[MC] Use DenseMap for ConstantPool::CachedEntries. NFC. (#208728)
This is mostly just a revert of:
3d0f9507d5e3 "[MC] Fix constant pools with DenseMap sentinel values"
although the key type has changed in the mean time. DenseMap no longer
uses sentinels so the reasons for avoiding it no longer apply.
Commit: fe80624dc6d62902319e34af8e9c709308957776
https://github.com/llvm/llvm-project/commit/fe80624dc6d62902319e34af8e9c709308957776
Author: Fabian Parzefall <parzefall at meta.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/indirect-goto.test
Log Message:
-----------
[BOLT] Treat relr relocations like rela (#206830)
The linker can emit certain relative .dyn.rela relocations in .dyn.relr.
This includes relocations for jumptables emitted for indirect goto. The
current processing recognizes these relocations as jump targets only for
relative relocations from .dyn.rela, but not from .dyn.relr. Give
.dyn.relr the same treatment, so CFG construction does not dismiss
blocks that are only reachable indirectly.
Commit: 8ece73c9f8b54fea6a98e9e4c55f9a2e6ccc9b3c
https://github.com/llvm/llvm-project/commit/8ece73c9f8b54fea6a98e9e4c55f9a2e6ccc9b3c
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/utils/ci/docker/linux-builder-base.dockerfile
Log Message:
-----------
[libc++] Update the base image hash to get most recent clang-23 (#208766)
Commit: 4bf0737d68bbb86d9d693e96a94c4175f27acebe
https://github.com/llvm/llvm-project/commit/4bf0737d68bbb86d9d693e96a94c4175f27acebe
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
Log Message:
-----------
[Github] Add ids container (#208498)
This will be used for the ids check workflow. This will enable us to use
a PGO optimized compiler that we also use elsewhere, which should help
speed up the builds on top of reducing redundant work like needing to
configure/build ids for every job. This also makes things a bit more
hermetic.
This is a bit of a hack with how the ids build is setup now (e.g.,
copying over libLLVM.so), but that's something that can be rectified
pretty easily later.
Commit: 2b0a79ec3f0c7b6919661f437f5474f3f9a3c942
https://github.com/llvm/llvm-project/commit/2b0a79ec3f0c7b6919661f437f5474f3f9a3c942
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/test/Analysis/Checkers/WebKit/binding-to-refptr.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-loop-init-opaque-value.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-safe-functions.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-wtf-containers.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
M clang/test/Analysis/Checkers/WebKit/ref-countable-default-arg-nullptr.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-call-arg.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.mm
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-const-v-muable.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-member.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Analysis/Checkers/WebKit/unretained-obj-arg.mm
Log Message:
-----------
[alpha.webkit.UncountedCallArgsChecker] Improve the warning text (#202724)
This PR improves UncountedCallArgsChecker and its variant's warning
message to explicitly state the argument expression, the qualified
callee type as well as the type which needs to be kept alive.
Commit: 01f376888e118ada65c88a59b183ba6139756a11
https://github.com/llvm/llvm-project/commit/01f376888e118ada65c88a59b183ba6139756a11
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll
Log Message:
-----------
ValueTracking: Fix off by one in known frexp exponent range (#208295)
Also restrict the optimization to the exactly 1 case for now.
There was an additional bug for values less than 1 to be fixed
separately.
Fixes #208192
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 4cd865f00afd8ef6c7947fae51328b7a168152c4
https://github.com/llvm/llvm-project/commit/4cd865f00afd8ef6c7947fae51328b7a168152c4
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/SemaCXX/cxx2c-constexpr-placement-new.cpp
Log Message:
-----------
[clang] Fix constexpr placement new of arrays. (#196669)
The existing code tried to implement a overly generous rule, and it
didn't really work. Restrict the accepted constructs to what we can
easily support. Adjust the representation of the destination pointer to
match the array which will be constructed.
Fixes #117294
Commit: 5ea45502aab0df356213d06651c62f59619a56a1
https://github.com/llvm/llvm-project/commit/5ea45502aab0df356213d06651c62f59619a56a1
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/add_u64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
M llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
M llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-attr.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
M llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
[AMDGPU] Add GFX1250 unclaused VMEM workaround (#208467)
Commit: c03584a783b03cb0a4c90a7d16ce3e2f7acd42fd
https://github.com/llvm/llvm-project/commit/c03584a783b03cb0a4c90a7d16ce3e2f7acd42fd
Author: Fateme Hosseini <Fhossein at qti.qualcomm.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
A llvm/test/CodeGen/Hexagon/autohvx/xqf-mult-normalize-second-operand.mir
Log Message:
-----------
[Hexagon] Fix wrong operand in XQFloat qf32 multiply normalization (#208489)
In convertNormalizeMultOp32, when only the second operand of a
V6_vmpy_qf32 comes from an add/sub/mul unit (secondconvert), the
generated multiply incorrectly used the raw second operand (Reg2)
instead of the first operand (Reg1). This dropped the first operand and
multiplied the normalized second operand by the un-normalized second
operand.
This patch fixed the multiply to use Reg1 and the normalized input_mpy2,
matching the correct arrangement used elsewhere. The bug was not
observed on v81 (which takes the V81normalizeMultF32 path); it only
affected the v79 fallback.
Co-authored-by: Santanu Das <quic_santdas at qti.qualcomm.com>
Commit: beffef686fde396bee59bf31ce44fffa0e6fc2ca
https://github.com/llvm/llvm-project/commit/beffef686fde396bee59bf31ce44fffa0e6fc2ca
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/docs/python_extensions.md
Log Message:
-----------
[lldb][docs] Try to fix forward the Sphinx automodapi doc generation (#208608)
Fixes LLDB doc generation errors for me locally
Commit: 4d834cd7644bfa083b3bac0604fc56455354c605
https://github.com/llvm/llvm-project/commit/4d834cd7644bfa083b3bac0604fc56455354c605
Author: timon-ul <timon.ulrich at advantest.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
M clang-tools-extra/clangd/unittests/IndexActionTests.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
Log Message:
-----------
[clangd] CodeCompletion surface param names if possible (#206716)
Resolves issue https://github.com/clangd/clangd/issues/2651
Commit: 7c35673039cf52ebe9458420e2ef712ffff9ad1a
https://github.com/llvm/llvm-project/commit/7c35673039cf52ebe9458420e2ef712ffff9ad1a
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-write-to-xegpu.mlir
Log Message:
-----------
[mlir][xegpu] Add support for 1D SLM case in vector-to-xepgu (#208276)
Currently vector-to-xegpu only support 2D SLM buffers. However
load/store_matrix op definition allows 1D access.
Assisted by: Claude
Commit: d981ae2be3be6fd65ad66e763fcc20b3a6cac58a
https://github.com/llvm/llvm-project/commit/d981ae2be3be6fd65ad66e763fcc20b3a6cac58a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
A llvm/test/Transforms/SampleProfile/icp_target_feature.ll
Log Message:
-----------
Reapply "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#208774)
Reverts llvm/llvm-project#208079
We're still seeing build failures without this, so reapply for now.
Commit: 5ddad72b154e4c4ddc2547b6cd17abd7b9a6ae53
https://github.com/llvm/llvm-project/commit/5ddad72b154e4c4ddc2547b6cd17abd7b9a6ae53
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/include/lldb/Protocol/MCP/Protocol.h
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
M lldb/source/Protocol/MCP/Protocol.cpp
M lldb/tools/lldb-mcp/CMakeLists.txt
A lldb/tools/lldb-mcp/Multiplexer.cpp
A lldb/tools/lldb-mcp/Multiplexer.h
M lldb/tools/lldb-mcp/lldb-mcp.cpp
Log Message:
-----------
[lldb-mcp] Replace byte forwarding with a protocol-aware multiplexer (#208506)
To serve several LLDB instances behind one endpoint it has to act as a
multiplexer. This PR adds a Multiplexer that presents a unified MCP
server to the client. It answers initialize and tools/list locally, and
forwards tools/call and the resource requests to the different instances
through an mcp::Client (added in #208371), relaying the answer back.
For now, this still drives a single backend. Discovering and routing
across several instances is coming next.
Assisted-by: Claude
Commit: 5b9d51ffcfa60e986be6cc4335bcf6c636b48d91
https://github.com/llvm/llvm-project/commit/5b9d51ffcfa60e986be6cc4335bcf6c636b48d91
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 5ddad72 (#208792)
This fixes 5ddad72b154e4c4ddc2547b6cd17abd7b9a6ae53.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=5ddad72b154e4c4ddc2547b6cd17abd7b9a6ae53
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: cc0f75682622778349cef748d2a8d1dfd09e8185
https://github.com/llvm/llvm-project/commit/cc0f75682622778349cef748d2a8d1dfd09e8185
Author: Ian Anderson <iana at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M compiler-rt/test/asan/TestCases/Posix/new_array_cookie_with_new_from_class.cpp
Log Message:
-----------
[asan][test] Fix Posix/new_array_cookie_with_new_from_class.cpp to work for arm targets (#208378)
arm targets, and arm64 targets on Darwin, use a 2-pointer array cookie
size. Update the test to support that.
Assisted-by: Claude Code
rdar://181775880
Commit: d1dbd484ada2a323a83ec9db64bcc247badc3025
https://github.com/llvm/llvm-project/commit/d1dbd484ada2a323a83ec9db64bcc247badc3025
Author: Rithik Sharma <rithiksh02 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/CodeGen/array-init-loop-exprs.cpp
M clang/test/CIR/CodeGen/ctor-try-body.cpp
M clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
M clang/test/CIR/CodeGen/inherited-ctors.cpp
M clang/test/CIR/IR/func.cir
M clang/test/CIR/IR/invalid-func.cir
M clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/CallOpTest.cpp
Log Message:
-----------
[CIR] Generalize the special member attribute into func_info and add a callee resolver (#207261)
The `cxx_special_member` slot on `cir.func` becomes a general slot named
`func_info`, so facts about a function that are not special member facts
can join later without redesign.
Nothing about the special member forms changes. The attribute stays the
same union of the constructor, destructor, and assignment forms. Each
form keeps its shape and its embedded record type, and the CXX ABI
lowering still replaces that type with the converted one. The FuncOp
helpers keep their names, so passes that read the special member facts
do not change.
The printed keyword on `cir.func` changes from `special_member` to
`func_info`, so the old spelling no longer parses. The existing tests
update their check lines with no other change.
Calls gain a resolver named `resolveCallee` that returns the function a
direct call targets, so a pass standing at a call can read the facts
recorded on its callee. It returns null when the call is indirect, when
the callee symbol does not resolve, and when the target is not a
`cir.func`. A second form takes a symbol table collection so a pass can
reuse its cached lookup. Both `cir.call` and `cir.try_call` get the
resolver through one shared implementation, and a unit test drives all
of these cases.
Commit: 340bd05d5f3c5dbd8bb49618aaaf39188cd2014b
https://github.com/llvm/llvm-project/commit/340bd05d5f3c5dbd8bb49618aaaf39188cd2014b
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] Simplify creating RegisterSets in DynamicRegisterInfo (#208592)
`DynamicRegisterInfo::GetRegisterSetIndexByName` is only used in
`DynamicRegisterInfo::SetRegisterInfo` so I inlined it and removed the
function. I also noticed that `m_set_names` is only used in this
function for setup, so I made it a local variable instead of a member.
Commit: 93737c9d36ad89f83c64ea201bd6d8f364e1f8c6
https://github.com/llvm/llvm-project/commit/93737c9d36ad89f83c64ea201bd6d8f364e1f8c6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/test/Driver/hip-include-path.hip
Log Message:
-----------
clang/AMDGPU: Forward host system includes in offload compiles (#208783)
Commit 640079288c5e merged the AMDGPU toolchain subclasses but dropped
the HIPAMDToolChain::AddClangSystemIncludeArgs override, which forwarded to
the host toolchain.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 8709f6f18fe29c4a9e3bac970e05326bc5b3d9d6
https://github.com/llvm/llvm-project/commit/8709f6f18fe29c4a9e3bac970e05326bc5b3d9d6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A llvm/include/llvm/TargetParser/TripleName.def
M llvm/include/module.modulemap
M llvm/lib/TargetParser/Triple.cpp
Log Message:
-----------
Triple: Move OS/vendor/environment names into a def file (#208722)
Extract the component name lists into a macro .def file, similar
to how many targets do for CPU names. The arch/subarch names are
left alone because they have trickier manual parsing logic.
Co-Authored-By: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 22ca91ce27af31f579a8a770a4d584f47bcc607f
https://github.com/llvm/llvm-project/commit/22ca91ce27af31f579a8a770a4d584f47bcc607f
Author: Kevin Bravo <kbravjr at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/misc/misplaced-const-cxx17.cpp
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/PCH/cxx1z-decomposition.cpp
M clang/test/Parser/cxx1z-decomposition.cpp
Log Message:
-----------
[clang] more useful error message for decomposition declaration missing initializer (#127924)
#90107
Diagnostic message for decomposition declaration missing an initializer
only highlights the declared identifier. This change adds an additional
diagnostic message to highlight the token found where the initializer
was expected. So, for example:
auto [a, b] S = {1, 2}
The new error points to 'S' and says that 'S' was found where an
initializer was expected.
Commit: 92d9e0dad82b6acb3e836a255580bb3eebcc3dd4
https://github.com/llvm/llvm-project/commit/92d9e0dad82b6acb3e836a255580bb3eebcc3dd4
Author: Rifet-c <levinale17 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/source/Commands/CommandObjectRegister.cpp
A lldb/test/Shell/Commands/command-register-read-alignment.test
Log Message:
-----------
[lldb] Improved formatting of 'register read' command. (#188049)
Made alignment of 'register read' command's output to be dynamic to the
register's name lengths -> `=` signs of different registers align when
printed as sets, also aligned when picked in some custom ordering. No
alignment between separate sets is included (i.e, each set is aligned to
itself only). Sample change:
```
Micro-architectural Registers:
r_pc = 0x0000108c main.xexe`main + 20 at main.c:5:5
instr_trace_r_init_print = 0x00
wb_csr_file_r_mstatus = 0x00000000
wb_csr_file_r_mie = 0x00000000
```
This example is changed into:
```
Micro-architectural Registers:
r_pc = 0x0000108c main.xexe`main + 20 at main.c:5:5
instr_trace_r_init_print = 0x00
wb_csr_file_r_mstatus = 0x00000000
wb_csr_file_r_mie = 0x00000000
```
---------
Co-authored-by: Aleksandr Levin <alexander.levin03 at mail.ru>
Commit: 2396c15bd38f50c49ee2eda0f8978a9f43ff7693
https://github.com/llvm/llvm-project/commit/2396c15bd38f50c49ee2eda0f8978a9f43ff7693
Author: Yitzhak Mandelbaum <ymand at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[NFC][clang][dataflow] Add explanatory comment to test. (#208779)
Commit: 188b9a3bfbc4e3720999b282c0c8c9af4c110e17
https://github.com/llvm/llvm-project/commit/188b9a3bfbc4e3720999b282c0c8c9af4c110e17
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll
Log Message:
-----------
ValueTracking: Generalize known frexp exponent range to any constant (#208316)
Extend computeKnownExponentRangeFromContext beyond the special case of a
dominating fabs(V) compare against exactly 1.0 to any finite limit.
Generalizing below 1.0 exposes a soundness issue: frexp(0) has exponent
0, so a bound derived assuming a nonzero value could wrongly exclude it
when the limit implies a negative maximum exponent. Query fcZero and
clamp the maximum exponent to at least 0 when the source may be zero.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 9e13720eb81fd8a68fe82ac962c17fd522547464
https://github.com/llvm/llvm-project/commit/9e13720eb81fd8a68fe82ac962c17fd522547464
Author: Stephan T. Lavavej <stl at nuwen.net>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/CREDITS.TXT
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/__exception/exception_ptr.h
M libcxx/src/support/runtime/exception_pointer_msvc.ipp
Log Message:
-----------
[libc++] Add MSVC's implementation of exception_ptr for Windows (#94977)
Microsoft is happy to contribute our implementation of exception_ptr for
Windows, under the Apache License v2.0 with LLVM Exception that our STLs
share.
* excptptr.cpp, copied verbatim as:
https://github.com/microsoft/STL/blob/e36ee6c2b9bc6f5b1f70776c18cf5d3a93a69798/stl/src/excptptr.cpp
* <exception>, copied verbatim as:
https://github.com/microsoft/STL/blob/e36ee6c2b9bc6f5b1f70776c18cf5d3a93a69798/stl/inc/exception
The implementation was integrated into libc++:
* Deleted STL copy of <exception>. All standard exception classes are
already provided by libc++'s standard headers.
* Replaced MSVC STL naming conventions and macros (_STD,
_CRTIMP2_PURE, _Ref_count_base, _Ptr_base, _EXCEPTION_RECORD, etc.)
with standard libc++ style and identifiers (_LIBCPP_EXPORTED_FROM_ABI,
__double_leading_underscore variable/function names).
* Replaced internal MSVC CRT headers (<trnsctrl.h>,
<internal_shared.h>, <xcall_once.h>) with portable standard C++
constructs (e.g., standard C++ function-local static initialization
for immortal static exception objects) and inline pointer-to-member
invocation helpers.
* Removed all exported __ExceptionPtr... C functions. These symbols
were originally present in Microsoft's CRT DLL exports solely to
support inline methods in MSVC STL's <exception> header.
* Moved all SEH/EH exception record definitions, SEH copying helpers
(__populate_cpp_exception_record, __copy_exception_object), and
reference-counted control blocks (__exception_ptr_static and
__exception_ptr_normal) directly into exception_pointer_msvc.ipp.
* Use reference-counted control block representation on Windows which
removed the platform #ifdef _LIBCPP_ABI_MICROSOFT bifurcation for
class exception_ptr in exception_ptr.h. std::exception_ptr now uses
the same layout across all operating systems.
Co-authored-by: Petr Hosek <phosek at google.com>
Commit: a8319d8bee48936c7748afc81a01907a6398adef
https://github.com/llvm/llvm-project/commit/a8319d8bee48936c7748afc81a01907a6398adef
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/src/atomic.cpp
Log Message:
-----------
[libc++] Merge atomic-wait contention tables into a single table (#208493)
PR #161086 (73a13839d3ec) introduced a new contention table for atomics
with a native size. However, this also increases the size of the dylib
and the footprint of processes using the dylib by a non-negligible
margin.
To mitigate this issue, this change folds the two tables into a single
one. The native waiter count can be stored for free inside padding that
was previously unused.
rdar://179161875
Commit: f505ece3359d778f06752e518046589ef6e544ff
https://github.com/llvm/llvm-project/commit/f505ece3359d778f06752e518046589ef6e544ff
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M flang/include/flang/Lower/DirectivesCommon.h
M flang/test/Lower/OpenACC/acc-bounds.f90
Log Message:
-----------
[flang][OpenACC] Preserve source extents in section strides (#208594)
Use the source array extent when advancing cumulative strides across
scalar subscripts, whose selected extent is one. Add coverage for mixed
scalar and triplet dimensions.
Commit: 59b0935b1494c90e02cc95a625f168f606966c3d
https://github.com/llvm/llvm-project/commit/59b0935b1494c90e02cc95a625f168f606966c3d
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaTemplate/overload-candidates.cpp
Log Message:
-----------
[Clang] Treat address-of template substitution as SFINAE
Taking the address of a function template specialization can instantiate
its trailing return type as part of a SFINAE probe:
struct X {};
template <class T> void f(T) = delete;
template <class T> auto probe(T t) -> decltype(f(t), void());
template <class T, class = decltype(&probe<T>)> int test(int);
template <class T> char test(...);
static_assert(sizeof(test<X>(0)) == sizeof(char));
Here, substituting the return type of probe<X> selects the deleted f<X>.
The deleted call is in the immediate context of substitution, so it should
remove test(int) from overload resolution. GCC accepts this example. Clang
instead kept deduction as successful and later replayed the stored
diagnostic as a hard error.
The call-deduction path already checks the SFINAE trap after finishing
template argument deduction. Do the same for the address-of path, so the
stored diagnostic is not replayed after deduction succeeds.
Commit: fbc9c356e11b8b47ed60c1329d7a2f2363e6b388
https://github.com/llvm/llvm-project/commit/fbc9c356e11b8b47ed60c1329d7a2f2363e6b388
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A libc/docs/arch_support.md
R libc/docs/arch_support.rst
A libc/docs/build_and_test.md
R libc/docs/build_and_test.rst
A libc/docs/build_concepts.md
R libc/docs/build_concepts.rst
A libc/docs/compiler_support.md
R libc/docs/compiler_support.rst
A libc/docs/contributing.md
R libc/docs/contributing.rst
A libc/docs/dev/building_docs.md
R libc/docs/dev/building_docs.rst
A libc/docs/dev/builtin_compatibility.md
R libc/docs/dev/builtin_compatibility.rst
A libc/docs/dev/code_style.md
R libc/docs/dev/code_style.rst
A libc/docs/dev/config_options.md
R libc/docs/dev/config_options.rst
A libc/docs/dev/entrypoints.md
R libc/docs/dev/entrypoints.rst
A libc/docs/dev/fuzzing.md
R libc/docs/dev/fuzzing.rst
A libc/docs/dev/header_generation.md
R libc/docs/dev/header_generation.rst
A libc/docs/dev/implementation_standard.md
R libc/docs/dev/implementation_standard.rst
A libc/docs/dev/implementing_a_function.md
R libc/docs/dev/implementing_a_function.rst
A libc/docs/dev/index.md
R libc/docs/dev/index.rst
A libc/docs/dev/modular_format.md
R libc/docs/dev/modular_format.rst
A libc/docs/dev/printf_behavior.md
R libc/docs/dev/printf_behavior.rst
A libc/docs/dev/source_tree_layout.md
R libc/docs/dev/source_tree_layout.rst
A libc/docs/dev/syscall_wrapper_refactor.md
R libc/docs/dev/syscall_wrapper_refactor.rst
A libc/docs/dev/undefined_behavior.md
R libc/docs/dev/undefined_behavior.rst
A libc/docs/full_cross_build.md
R libc/docs/full_cross_build.rst
A libc/docs/full_host_build.md
R libc/docs/full_host_build.rst
A libc/docs/getting_started.md
R libc/docs/getting_started.rst
A libc/docs/hand_in_hand.md
R libc/docs/hand_in_hand.rst
A libc/docs/index.md
R libc/docs/index.rst
A libc/docs/overlay_mode.md
R libc/docs/overlay_mode.rst
A libc/docs/platform_support.md
R libc/docs/platform_support.rst
A libc/docs/porting.md
R libc/docs/porting.rst
A libc/docs/talks.md
R libc/docs/talks.rst
Log Message:
-----------
[docs] Rename selected libc docs to Markdown (#208354)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: 71fe35814f4b4b5dc88b9caa65f44da5da946df8
https://github.com/llvm/llvm-project/commit/71fe35814f4b4b5dc88b9caa65f44da5da946df8
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M offload/CMakeLists.txt
M offload/ci/openmp-offload-amdgpu-clang-flang.py
M offload/test/lit.cfg
M offload/test/offloading/fortran/basic_array.c
M offload/test/offloading/fortran/target-use-dev-ptr.f90
M offload/test/offloading/fortran/usm_map_close.f90
M openmp/CMakeLists.txt
M openmp/device/CMakeLists.txt
Log Message:
-----------
[OpenMP][Offload][AMDGPU] Fix offload tests failure after the new triple (#208617)
Offload tests failed after introducing the new triple. This PR attempts
to address that. It includes the changes in
https://github.com/llvm/llvm-project/pull/208551. In addition, it also
made following changes:
- Updated flang builder that our buildbot uses;
- Updated the CMakeLists for offload and AMDGPU device runtime (a little
duplications to avoid breaking other buildbots);
- Added per target linker path and mapping for lit substitution/features
in lit config;
- Updated hard-coded check lines in the tests.
This PR reduces the failed offload tests from 246 to 2 on my test runs
locally. Test results and the two failed tests:
```
Failed Tests (2):
libomptarget :: amdgpu-amd-amdhsa :: offloading/fortran/declare-target-common-block-main.f90
libomptarget :: amdgpu-amd-amdhsa :: sanitizer/use_after_free_2.c
Total Discovered Tests: 3478
Skipped : 77 (2.21%)
Unsupported : 341 (9.80%)
Passed : 3053 (87.78%)
Expectedly Failed: 5 (0.14%)
Failed : 2 (0.06%)
```
I was not able to identify the commits for the two failed tests yet
(didn't look like flakiness), will try again later.
Co-authored-by: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Commit: 03ce818a29ac8385e879fe3f0d464ca95c128088
https://github.com/llvm/llvm-project/commit/03ce818a29ac8385e879fe3f0d464ca95c128088
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Update bazel amdgpu to use extended llt (#208797)
Updating flags since this is changed in cmake:
https://github.com/llvm/llvm-project/pull/207419/changes#diff-e857fdc8c81a5cc9f4fafbd85d56b409a7bf316e4d6da23a1c0a6418d66e5db6R23
Commit: 7bb9626d5ab901e5c1a8e9acbbb1684c982401b4
https://github.com/llvm/llvm-project/commit/7bb9626d5ab901e5c1a8e9acbbb1684c982401b4
Author: Tulio Magno Quites Machado Filho <tuliom at redhat.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/test/Verifier/gc_relocate_out_of_bounds.ll
Log Message:
-----------
[LLVM][Verifier] Fix buffer overflow when verifying gc.statepoint (#208278)
When a negative base index is passed, the verification detects the
out-of-bounds value and start printing information that helps to
identify what caused the error. In order to print all the information,
it tries to dereference the Base pointer at
GCRelocateInst::getBasePtr(), causing the buffer overflow. Add a bounds
check to getBasePTR() and getDerivedPtr() in order to avoid this.
Improve the test in order to validate negative values passed as indexes.
They're based on the reproducer from issue #199191.
Fixes #199191
Commit: 821afb2ed82f66513cbaab1657d680179f10ed35
https://github.com/llvm/llvm-project/commit/821afb2ed82f66513cbaab1657d680179f10ed35
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libc/docs/arch_support.md
M libc/docs/build_and_test.md
M libc/docs/build_concepts.md
M libc/docs/compiler_support.md
M libc/docs/conf.py
M libc/docs/contributing.md
M libc/docs/dev/building_docs.md
M libc/docs/dev/builtin_compatibility.md
M libc/docs/dev/code_style.md
M libc/docs/dev/config_options.md
M libc/docs/dev/entrypoints.md
M libc/docs/dev/fuzzing.md
M libc/docs/dev/header_generation.md
M libc/docs/dev/implementation_standard.md
M libc/docs/dev/implementing_a_function.md
M libc/docs/dev/index.md
M libc/docs/dev/modular_format.md
M libc/docs/dev/printf_behavior.md
M libc/docs/dev/source_tree_layout.md
M libc/docs/dev/syscall_wrapper_refactor.md
M libc/docs/dev/undefined_behavior.md
M libc/docs/full_cross_build.md
M libc/docs/full_host_build.md
M libc/docs/getting_started.md
M libc/docs/hand_in_hand.md
M libc/docs/index.md
M libc/docs/overlay_mode.md
M libc/docs/platform_support.md
M libc/docs/porting.md
M libc/docs/talks.md
Log Message:
-----------
[docs] Rewrite libc docs from reST to markdown (#208802)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This was prepared with rst2myst plus LLM-assisted cleanup. I paged
through all the generated HTML looking for migration artifacts, and all
of the differences I could find appear to be formatting error
corrections. Please spot check my work and approve if it looks good.
Commit: b33af86b032e4a89a947b1c2818cb36861814ad9
https://github.com/llvm/llvm-project/commit/b33af86b032e4a89a947b1c2818cb36861814ad9
Author: Aleksandr Popov <42888396+aleks-tmb at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
Log Message:
-----------
[SCEV][NFC] Precommit tests for #208778 (#208784)
These tests capture the current missed vectorization behavior and serve
as a baseline for the upcoming fix.
Commit: a6cf9ec73060bf2b38b3981459071d86b254e8fc
https://github.com/llvm/llvm-project/commit/a6cf9ec73060bf2b38b3981459071d86b254e8fc
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/utils/ci/docker/docker-compose.yml
Log Message:
-----------
[libc++] Bump base image version to most recent (#208776)
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: 95a117bc8a724095e26d942228564ff7c685ca25
https://github.com/llvm/llvm-project/commit/95a117bc8a724095e26d942228564ff7c685ca25
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/directive-amdgcn-target-legacy-triples.ll
R llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/target-id-xnack-always-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
Log Message:
-----------
AMDGPU: Migrate target id tests to use new subarch triples (#206488)
Commit: b29d4b270b96b6e291306332ab87d72e639ccba9
https://github.com/llvm/llvm-project/commit/b29d4b270b96b6e291306332ab87d72e639ccba9
Author: Ron Green [NVIDIA] <rogreen at nvidia.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/acc-loop-nested-in-do-concurrent.f90
Log Message:
-----------
[flang][OpenACC] Bind DO CONCURRENT construct index for nested acc loops (#208529)
A DO CONCURRENT index-name is a construct entity that lives in the
construct's own scope, distinct from a like-named variable in the
enclosing subprogram scope. When a DO CONCURRENT is associated with an
`!$acc loop`, lowering privatizes the symbol referenced by the loop
control, which inside an OpenACC compute construct is the
enclosing-scope variable. However, a reference to that index from within
a *nested* explicit `!$acc loop` construct resolves to the construct
entity instead. That entity was never bound in the symbol map, so
lowering the reference hit the "lowering symbol to HLFIR" TODO and
aborted.
Bind the construct entity to the same privatized storage as the loop
control so such references lower correctly.
Commit: b2ae07fde4029f9c40932101680fbade34e237ff
https://github.com/llvm/llvm-project/commit/b2ae07fde4029f9c40932101680fbade34e237ff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[TableGen] Add MCReadAdvanceEntry to vector first, then write its fields. NFC (#208789)
Commit: 3bc47c8dc927e0d6145eb128e588179f7654b5f7
https://github.com/llvm/llvm-project/commit/3bc47c8dc927e0d6145eb128e588179f7654b5f7
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.cpp
R clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractor.cpp
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-bad-id.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-no-key.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-bad-id.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-empty.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-no-key.json
A clang/test/Analysis/Scalable/OperatorNewDelete/operator-new-delete.cpp
A clang/test/Analysis/Scalable/OperatorNewDelete/tu-summary-serialization.test
A clang/test/Analysis/Scalable/OperatorNewDelete/wpa-result-serialization.test
Log Message:
-----------
[SSAF][WPA] Operator new/delete overload entities that shall retain their types (#208342)
A follow-up change to #206600. This commit adds the WPA implementation
for those operator new/delete overload entities that shall retain their
types. This WPA result will later be used to filter unsafe buffer
analysis results.
rdar://179151541
Assisted by Claude Sonnet 4.6
Commit: 15480d2d7f4519b4bdda633d2f9e8f8e6413b19d
https://github.com/llvm/llvm-project/commit/15480d2d7f4519b4bdda633d2f9e8f8e6413b19d
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/test/CodeGenCXX/ms-mangle-requires.cpp
Log Message:
-----------
[Clang][NFC] Add two CWG2369 regression tests (#186380)
Some of the MS ABI regressions, which were caused by CWG2369, were fixed
by https://github.com/llvm/llvm-project/pull/197215. Let's add those
regressions to our tests.
Closes https://github.com/llvm/llvm-project/issues/173160
Closes https://github.com/llvm/llvm-project/issues/191588
Commit: 1e713b277aff89ea2a64ebf4a8a1ec62004ac146
https://github.com/llvm/llvm-project/commit/1e713b277aff89ea2a64ebf4a8a1ec62004ac146
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/test/Driver/offload-parallel-device-cc1.cu
Log Message:
-----------
[Clang][Driver][NFC] Fix offload-parallel-device-cc1.cu failing in read-only runfiles sandbox (#208801)
When running offload-parallel-device-cc1.cu with multiple
--cuda-gpu-arch
flags and --cuda-device-only -S, Clang generates multiple .s outputs in
the
current working directory (.). In sandboxed test environments, . is
read-only,
causing compilation to fail with "Permission denied".
Fix by executing the CUDA compilation step inside a temporary directory
(%t).
This pattern is being used in other tests like in
clang/test/Driver/ftime-trace-offload.cpp and
clang/test/Driver/unix-conformance.c.
Commit: 9c8485a2c216160bfc5d64a71cbbd298776618bd
https://github.com/llvm/llvm-project/commit/9c8485a2c216160bfc5d64a71cbbd298776618bd
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init.c
Log Message:
-----------
[clang] Use a 128-byte destructive interference size on Apple AArch64 (#208716)
Apple arm64 cores use a 128-byte cache line, as reported by `sysctl -a`.
However, Clang inherited the generic AArch64 value and was setting
`__GCC_DESTRUCTIVE_SIZE` to 256 for Apple targets (see bce2cc15133a).
While the value of 256 matches what GCC uses and is what's documented by
ARM, 128 seems to be a better value for Apple arm64 specifically, with
256 simply being wasteful.
Note that changing this value should in principle not be an issue since
it (and constructive interference) are explicitly documented as being
"ABI unstable" values, in the sense that users should not rely on them
in ABI-sensitive places.
Fixes #182951
Commit: 2fd14194bf8c01d8b3a5364ea17d04409d0e942c
https://github.com/llvm/llvm-project/commit/2fd14194bf8c01d8b3a5364ea17d04409d0e942c
Author: sujianIBM <Jian.Su at ibm.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/CodeGen/SystemZ/zos-ppa1-name.c
A clang/test/Driver/zos-ppa1-name.c
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/test/CodeGen/SystemZ/zos-ppa1.ll
Log Message:
-----------
[SystemZ][z/OS] Add options -m[no-]zos-ppa1-name to remove the function name in PPA1. (#207416)
This PR adds a pair of flag options `-m[no-]zos-ppa1-name` to clang,
which controls whether the function name is emitted in PPA1 on z/OS.
Commit: a1956712099b11ae7b218fce93115e45935933d9
https://github.com/llvm/llvm-project/commit/a1956712099b11ae7b218fce93115e45935933d9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AMDGPU/abs.ll
M llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
M llvm/test/Analysis/CostModel/AMDGPU/addrspacecast.ll
M llvm/test/Analysis/CostModel/AMDGPU/aggregates.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-sminmax.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-ssat.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-uminmax.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-usat.ll
M llvm/test/Analysis/CostModel/AMDGPU/arithmetic_fence.ll
M llvm/test/Analysis/CostModel/AMDGPU/bit-ops.ll
M llvm/test/Analysis/CostModel/AMDGPU/canonicalize.ll
M llvm/test/Analysis/CostModel/AMDGPU/cast.ll
M llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
M llvm/test/Analysis/CostModel/AMDGPU/div.ll
M llvm/test/Analysis/CostModel/AMDGPU/exp.ll
M llvm/test/Analysis/CostModel/AMDGPU/exp10.ll
M llvm/test/Analysis/CostModel/AMDGPU/exp2.ll
M llvm/test/Analysis/CostModel/AMDGPU/extractelement.ll
M llvm/test/Analysis/CostModel/AMDGPU/fabs.ll
M llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
M llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
M llvm/test/Analysis/CostModel/AMDGPU/fma.ll
M llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
M llvm/test/Analysis/CostModel/AMDGPU/fmuladd.ll
M llvm/test/Analysis/CostModel/AMDGPU/fneg.ll
M llvm/test/Analysis/CostModel/AMDGPU/fptosi.ll
M llvm/test/Analysis/CostModel/AMDGPU/fptoui.ll
M llvm/test/Analysis/CostModel/AMDGPU/frexp.ll
M llvm/test/Analysis/CostModel/AMDGPU/fround.ll
M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
M llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
M llvm/test/Analysis/CostModel/AMDGPU/gep.ll
M llvm/test/Analysis/CostModel/AMDGPU/insertelement.ll
M llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
M llvm/test/Analysis/CostModel/AMDGPU/ldexp.ll
M llvm/test/Analysis/CostModel/AMDGPU/load-to-trunc.ll
M llvm/test/Analysis/CostModel/AMDGPU/load.ll
M llvm/test/Analysis/CostModel/AMDGPU/log.ll
M llvm/test/Analysis/CostModel/AMDGPU/log10.ll
M llvm/test/Analysis/CostModel/AMDGPU/log2.ll
M llvm/test/Analysis/CostModel/AMDGPU/logicalop.ll
M llvm/test/Analysis/CostModel/AMDGPU/maximum.ll
M llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/maxnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/mul.ll
M llvm/test/Analysis/CostModel/AMDGPU/ptrmask.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-and.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-or.ll
M llvm/test/Analysis/CostModel/AMDGPU/rem.ll
M llvm/test/Analysis/CostModel/AMDGPU/shifts.ll
M llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
M llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
M llvm/test/Analysis/CostModel/AMDGPU/sqrt.ll
M llvm/test/Analysis/CostModel/AMDGPU/store.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/inline-asm.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/uses-value-from-cycle.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-subgraph.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization-preserve-name.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-simplify-cfg-CAS-block.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-cmpxchg-flat-maybe-private.ll
Log Message:
-----------
AMDGPU: Migrate Analysis/Transforms tests to amdgpu subarch triple (1) (#208809)
Mechanically migrate the command-line target spelling on RUN lines from
-mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g.
-mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu.
This first batch covers Analysis and Transforms tests. Tests whose
output materially depends on -mcpu (e.g. opt runs that record a target-cpu
attribute, or cost-model tests whose default subtarget differs) are left for
separate handling. This begins a series of ~62 PRs covering backend tests.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 82922454d89f5d34481af2e8313cd25b1eb3868d
https://github.com/llvm/llvm-project/commit/82922454d89f5d34481af2e8313cd25b1eb3868d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M .github/workflows/ids-check.yml
Log Message:
-----------
[Github] Make ids-check workflow use container (#208780)
4bf0737d68bbb86d9d693e96a94c4175f27acebe introduced a container for this
to enable the use of a PGO optimized compiler and to bake the idt build
into the container. This patch updates the workflow to use it.
Commit: 4a717571c2d313c6cf3a54b3d3da1fe52cbe5453
https://github.com/llvm/llvm-project/commit/4a717571c2d313c6cf3a54b3d3da1fe52cbe5453
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/test/Transforms/AggressiveInstCombine/X86/lower-table-based-log2-basics.ll
Log Message:
-----------
[AggressiveInstCombine] Support alternate deBruijn log2 table that isolates the MSB before the multiply. (#208532)
The existing deBruijn log2 match expects the multiply input to be a mask
that has all bits below the most significant set bit to be 1.
There is an alternate form in some programs where this mask is modified
to isolate the MSB by doing (mask - (mask >> 1)). A cttz table is then
used instead of a log2 table.
This patch teaches tryToRecognizeTableBasedLog2 to match this form too.
I think there's still some additional work needed elsewhere to recognize
that the sub+select in the output can be done with not+and.
Fixes #207571
Assisted-by: Claude
Commit: 4e5a44a332d020e668f350f65fd24019fe239c8d
https://github.com/llvm/llvm-project/commit/4e5a44a332d020e668f350f65fd24019fe239c8d
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lld/ELF/Relocations.cpp
M lld/ELF/SyntheticSections.cpp
M lld/test/ELF/mips-tls-64-pic-local-variable.s
M lld/test/ELF/x86-64-tls-gd-local.s
Log Message:
-----------
[ELF] Fix TLS GD against non-preemptible dynamic symbols in DSOs (#207881)
Consider a DSO that uses TLS GD against a dynamic non-preemptible symbol
(e.g. protected, or linked with -Bsymbolic). The expected meaning of
this is to always reference the DSO's own TLS segment for that symbol,
regardless of any attempts to preempt it at load time, and LLD will
indeed emit a constant offset rather than a symbolic DTPOFF relocation
for the second GOT word. However, for the first GOT word, because we
currently only treat the isLocalInExecutable case as special (where the
module index is 1), we end up creating a symbolic DTPMOD relocation,
rather than a non-symbolic (i.e. against the null symbol) one to get
this DSO's index, and so any load-time preemption will cause us to use a
different module's TLS block. As a result, not only do we have symbol
preemption when we shouldn't, but also the two halves of the TLS GD GOT
entry end up inconsistent, using the offset of the symbol in this
module's TLS block for a different module's.
Fix this by breaking down the two !isLocalInExecutable cases, emitting
the expected non-symbolic DTPMOD relocation for any non-preemptible
symbol references in a DSO. Whilst here, combine the DTPMOD and DTPOFF
code rather than have two different if statements, so it's clearer what
the three cases are and they don't get out of sync.
Note that although, for the existing code, local symbols take the exact same
code paths in postScanRelocations, they do not end up with symbolic DTPMOD
relocations in the output, despite creating them. DynamicReloc::getSymIndex has
the quirk of silently squashing the symbol index to 0 for symbolic relocations
against non-dynamic symbols, which applies to local symbols but not other
non-preemptible symbols, i.e. the case relevant in the first paragraph. This
quirky behaviour of DynamicReloc::getSymIndex is probably something that should
be retired; I can't see a good reason for it, and any case that it squashes
could be hiding similar bugs like this. I take the view that a request to
create a symbolic relocation against a symbol that won't be in the dynamic
symbol table is a strong sign that the code is confused and doing something
wrong, even if it happens to work out.
Commit: 4c5e15667fe384e434961fe44cf5950dc309fdf1
https://github.com/llvm/llvm-project/commit/4c5e15667fe384e434961fe44cf5950dc309fdf1
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/cmake/modules/FindDIASDK.cmake
Log Message:
-----------
[cmake] Fix VSINSTALLDIR check in FindDIASDK module (#208524)
elseif($ENV{VSINSTALLDIR}) expands the env value into the condition,
where CMake treats it as an undefined variable, so the branch is always
false. Fix this by testing if the env variable is defined instead.
Commit: 2705f4613aee08fcbe7292ae4a2ce577c8192d48
https://github.com/llvm/llvm-project/commit/2705f4613aee08fcbe7292ae4a2ce577c8192d48
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A libc/docs/dev/date_and_time.md
M libc/docs/dev/index.md
M libc/src/time/CMakeLists.txt
M libc/src/time/time_constants.h
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/test/src/time/CMakeLists.txt
M libc/test/src/time/gmtime_test.cpp
Log Message:
-----------
[libc] Implement fast date conversion algorithm of Ben Joffe (#208312)
Replaced the loop-based year/month/day extraction in update_from_seconds
with Ben Joffe's "Very Fast 64-bit" date algorithm using multiply-shift
division (4 multiplications, 0 hardware divisions). Also replaced the
mktime inverse with Ben Joffe's inverse date algorithm.
Updated is_leap_year to use the Drepper-Neri-Schneider algorithm (% 25
instead of % 100). Replaced the O(n) yday month-length loop with a
constant-time cumulative-days table lookup.
Uses UInt128 for portable 128-bit support across 64-bit (native) and
32-bit (software fallback) targets.
Raman's benchmarks on x86-64 show a ~13% wall-time improvement:
Before: real 2.215s, user 2.214s
After: real 1.919s, user 1.913s
Algorithm references:
https://www.benjoffe.com/fast-date-64
https://www.benjoffe.com/fast-date#inverse
https://www.benjoffe.com/fast-leap-year#drepper-neri-schneider
---------
Co-authored-by: Raman Tenneti <rtenneti at google.com>
Commit: ac88468d745f0f10d51029ca9d2ef717f43086a0
https://github.com/llvm/llvm-project/commit/ac88468d745f0f10d51029ca9d2ef717f43086a0
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constexpr-array-unknown-bound.cpp
Log Message:
-----------
[Clang] Adjust assert in addUnsizedArray to check Base is set before … (#208112)
In addUnsizedArray we attempt to check the type of Base in an assert but
don't verify if it set before doing so. This can lead to a crash, check
Base is set before checking its type and add a regression test.
Fixes: https://github.com/llvm/llvm-project/issues/44212
Commit: ddbce7b55c368c9601feb803802274703bfa1854
https://github.com/llvm/llvm-project/commit/ddbce7b55c368c9601feb803802274703bfa1854
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-load.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-store.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll
M llvm/test/Transforms/Attributor/AMDGPU/do-not-replace-addrspacecast-with-constantpointernull.ll
M llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/address_space_info.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/addressing-modes.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll
M llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/convergent-call.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/memrealtime.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem-inf.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/missing-analysis.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/pass-parameters.ll
M llvm/test/Transforms/GlobalOpt/address_space_initializer.ll
M llvm/test/Transforms/GlobalOpt/shrink-global-to-bool.ll
M llvm/test/Transforms/HipStdPar/accelerator-code-selection.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-0.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-1.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-2.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-count.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-type.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection.ll
M llvm/test/Transforms/HipStdPar/global-var.ll
M llvm/test/Transforms/HipStdPar/unsupported-asm.ll
M llvm/test/Transforms/HipStdPar/unsupported-builtins.ll
M llvm/test/Transforms/HipStdPar/unsupported-thread-local-direct-use.ll
M llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll
M llvm/test/Transforms/IndVarSimplify/AMDGPU/no-widen-to-i64.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/address-space-id-funcs.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/assumed-addrspace.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/basic.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/builtin-assumed-addrspace.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/debug-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/icmp.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-address-space.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-addrspacecast.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-getelementptr.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/insert-pos-assert.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/intrinsics.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/is.constant.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue110433.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue53665.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/masked-load-store.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/mem-intrinsics.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/multiple-uses-of-val.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/no-flat-addrspace.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/phi-poison.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/prefetch.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/preserving-debugloc-addrspacecast.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/ptrmask.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/redundant-addrspacecast.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/select.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/self-phi.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/store-pointer-to-self.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/unreachable-code-assert.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/volatile.ll
M llvm/test/Transforms/InferFunctionAttrs/enable-builtin.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument-cost.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-only-one-live-use.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-argument-i64.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-array-ptr-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-indirect-call-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-ptr-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-struct-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-vector-ptr-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-vecbonus.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-atomicrmw-md-preserve.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-denormal-fp-math.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-hint.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-sram-ecc.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-xnack.ll
M llvm/test/Transforms/Inline/AMDGPU/load-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/addrspacecast.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics-gfx8.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-simplify-image-buffer-stores.ll
M llvm/test/Transforms/InstCombine/AMDGPU/canonicalize-add-to-gep.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmed3-fpext-fold.ll
Log Message:
-----------
AMDGPU: Migrate Analysis/Transforms tests to amdgpu subarch triple (2) (#208810)
Commit: a2fc23854f963cbf63cc6266b73a2df7cc4a5068
https://github.com/llvm/llvm-project/commit/a2fc23854f963cbf63cc6266b73a2df7cc4a5068
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
M llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
M llvm/test/Transforms/InstCombine/AMDGPU/issue68120.ll
M llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll
M llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll
M llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll
M llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
M llvm/test/Transforms/InstCombine/AMDGPU/sendmsg-m0-poison.ll
M llvm/test/Transforms/InstCombine/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll
M llvm/test/Transforms/InstCombine/AMDGPU/tan.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll
M llvm/test/Transforms/InstCombine/exp2-1.ll
M llvm/test/Transforms/InstCombine/pow-1.ll
M llvm/test/Transforms/JumpThreading/divergent-target-test.ll
M llvm/test/Transforms/LICM/AMDGPU/bitcast.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/addrspace-7.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll
M llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
M llvm/test/Transforms/MemCpyOpt/no-libcalls.ll
M llvm/test/Transforms/OpenMP/custom_state_machines.ll
M llvm/test/Transforms/OpenMP/custom_state_machines_pre_lto.ll
M llvm/test/Transforms/OpenMP/heap-to-shared-missing-declarations.ll
M llvm/test/Transforms/OpenMP/spmdization.ll
M llvm/test/Transforms/OpenMP/spmdization_indirect.ll
M llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
M llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll
M llvm/test/Transforms/PhaseOrdering/varargs.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expamd-masked-load.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-gather.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-scatter.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-store.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll
Log Message:
-----------
AMDGPU: Migrate Analysis/Transforms tests to amdgpu subarch triple (3) (#208811)
Continue migrating command-line target spelling on RUN lines to the
folded amdgpu subarch triple form, covering more Transforms tests.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 37593bf3c58e693fb3bdaa2f5e7ab136a5ddbe75
https://github.com/llvm/llvm-project/commit/37593bf3c58e693fb3bdaa2f5e7ab136a5ddbe75
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/hexagon_fmadf5_test.c
Log Message:
-----------
[compiler-rt][hexagon][test] Guard __hexagon_fmadf5 unit test with __hexagon__ define (#208818)
When `compiler-rt/test/builtins/Unit/` C test files are compiled outside
of a standard `lit` pipeline (such as direct standalone compilation or
downstream test harnesses where each `.c` file is built and run as an
independent executable against `libclang_rt.builtins.a`),
`hexagon_fmadf5_test.c` unconditionally referenced `__hexagon_fmadf5`.
Because `__hexagon_fmadf5` is only provided in
`libclang_rt.builtins-hexagon.a`, non-Hexagon builds failed at link
time.
This change is consistent with other architecture-specific builtin unit
tests (such as `divdf3vfp_test.c`, `adddf3vfp_test.c`, and ARM/PPC
builtin tests), this change wraps Hexagon-specific declarations,
helpers, and test logic inside `#if defined(__hexagon__)`. On
non-Hexagon targets, `main()` prints `"skipped\n"` and returns `0`.
Introduced by https://github.com/llvm/llvm-project/pull/207373
Commit: 98e5f18078ca87ff59bb6e6b07e341a77d599f81
https://github.com/llvm/llvm-project/commit/98e5f18078ca87ff59bb6e6b07e341a77d599f81
Author: jimingham <jingham at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
Move the error about DIE not having an address range to the Verbose channel (#208593)
This particular error, when it comes tends to come over and over and
over and swamps all the other logging output.
It's clearly a candidate for the verbose log channel. Since this was
emitted with LLDB_LOG_ERROR that also meant it went to the always on
log, where again it was swamping the other output and making logs quite
difficult to read. I asked around and nobody felt the need to have this
always on.
Commit: 6d3cf7f436a01f4622fb660e413a4020209777b8
https://github.com/llvm/llvm-project/commit/6d3cf7f436a01f4622fb660e413a4020209777b8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/utils/ci/docker/docker-compose.yml
Log Message:
-----------
[libcxx] Bump GitHub runner version (#208823)
To stay ahead of the 6-month deprecation curve, we might as well bump
this as we update the image to get a more recent clang version.
Commit: 5b1484c828448675dbfddc50be7280c2dcab80da
https://github.com/llvm/llvm-project/commit/5b1484c828448675dbfddc50be7280c2dcab80da
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/include/clang/Driver/CommonArgs.h
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/opencl-libclc.cl
Log Message:
-----------
clang/AMDGPU: Fix double linking opencl libs with --libclc-lib (#204865)
Noticed by inspection. If using an explicit --libclc-lib flag,
do not attempt to also link the rocm device libs which will contain
different implementations of the same opencl symbols.
Co-Authored-By: Claude <noreply at anthropic.com>
Commit: f8ea8223d2ab1d6c3aa6c7c21444cf4d23a6d184
https://github.com/llvm/llvm-project/commit/f8ea8223d2ab1d6c3aa6c7c21444cf4d23a6d184
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
A llvm/test/CodeGen/Hexagon/pr207422.ll
Log Message:
-----------
[Hexagon] Recompute physreg live-ins after HexagonRDFOpt (PR207422) (#208050)
HexagonRDFOpt's Liveness recomputation (LV.resetLiveIns) can leave
stale, over-approximate physical register live-ins on some blocks.
Downstream this has surfaced as If Converter inserting incorrect
implicit-use operands on predicated loads, tripping the machine verifier
with 'Using an undefined physical register'.
Run a conventional backward liveness recomputation after the RDF update
to correct the live-in lists. The entry block is skipped because its
live-ins reflect the calling convention and include argument registers
that may not be read directly.
Commit: d1fc322223b6e1e9e45b4ec3af3f2b1aa7c4f1fc
https://github.com/llvm/llvm-project/commit/d1fc322223b6e1e9e45b4ec3af3f2b1aa7c4f1fc
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
[CMake] Use minimum python version of 3.8 everywhere (#208822)
We used to set a minimum of 3.0, and only 3.8 if tests were enabled. But
it doesn't seem like anyone is actually testing this config and it just
seems to cause more confusion/breakage than anything else, so just set
the global minimum to 3.8.
Commit: 956777b773f81f6103c621857c3784b2c3f76c66
https://github.com/llvm/llvm-project/commit/956777b773f81f6103c621857c3784b2c3f76c66
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Bump runner version to 2.335.1 (#208824)
To stay ahead of the 6-month deprecation window.
Commit: 60474dc123ab46badaccc237e43c1fe5ebb87481
https://github.com/llvm/llvm-project/commit/60474dc123ab46badaccc237e43c1fe5ebb87481
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M mlir/test/Dialect/SCF/loop-pipelining.mlir
M mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
Log Message:
-----------
[mlir][scf] Validate pipelining annotations in test pass (#208788)
I made the SCF pipelining test pass validate malformed scheduling
annotations before building the schedule. Bad annotations now produce
diagnostics instead of crashing, while valid schedules keep using the
existing path.
Fixes #206918
Commit: 372e0ab3a8c3ff57781a432ab35190cc9aca144d
https://github.com/llvm/llvm-project/commit/372e0ab3a8c3ff57781a432ab35190cc9aca144d
Author: Aleksandr Platonov <platonov.aleksandr at huawei.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/index/remote/marshalling/Marshalling.cpp
Log Message:
-----------
[clangd][remote] Fix SmallVector assertion in uriToRelativePath for Windows paths (#208830)
After https://github.com/llvm/llvm-project/pull/207202 buildbot has
detected a new failure.
Assertion happens in newly created test:
```
ClangdTests: /vol/worker/clangd-ubuntu-clang/clangd-ubuntu-tsan/llvm-project/llvm/include/llvm/ADT/SmallVector.h:196: void llvm::SmallVectorTemplateCommon<char>::assertSafeToReferenceAfterResize(const void *, size_t) [T = char]: Assertion `isSafeToReferenceAfterResize(Elt, NewSize) && "Attempting to reference an element of the vector in an operation " "that invalidates it"' failed.
```
The root cause is that `Path` is a `StringRef` aliasing `Result`s
buffer. Assigning `Result` to `Path.drop_front()` triggers
`SmallVector`s `assertSafeToReferenceAfterResize` assertion (that
assertion checks if we are passing an iterator that points into the own
buffer).
With this patch we convert `Path.drop_front()` to `std::string` to break
the aliasing before assignment.
Commit: ff77f06bcc287458041f876106d7f8ae86d3a118
https://github.com/llvm/llvm-project/commit/ff77f06bcc287458041f876106d7f8ae86d3a118
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Driver/bbc-implicit-use-module.f90
Log Message:
-----------
[flang][cuda] Restrict implicit use to non-cuda subprogram (#208808)
Commit: 3b3509a2adcbab4dfc224ba1d85c0ce7fab786c1
https://github.com/llvm/llvm-project/commit/3b3509a2adcbab4dfc224ba1d85c0ce7fab786c1
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/cse-replicate-regions.ll
Log Message:
-----------
[VPlan] Enable CSE of VPWidenPHIRecipe. (#207573)
Add VPWidenPHIRecipe to the set of recipes CSE can handle. Besides their
operands (incoming values), they also depend on their predecessors, so
canHandle checks for that.
PR: https://github.com/llvm/llvm-project/pull/207573/
Commit: 1dbefed159e96e875e1f898093c8e872ab760035
https://github.com/llvm/llvm-project/commit/1dbefed159e96e875e1f898093c8e872ab760035
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/Representation.cpp
Log Message:
-----------
[clang-doc][nfc] Remove stale FIXME (#208795)
This was fixed a long time ago when relanding arena support. This FIXME
was missed when we folded in the deep copying to the reland. It can
safely be removed, as the situation it warns about cannot happen
anymore.
Commit: 160ff82534b171965da6d5d2bd079547dbf73547
https://github.com/llvm/llvm-project/commit/160ff82534b171965da6d5d2bd079547dbf73547
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
Log Message:
-----------
[clang-doc][nfc] Delete commented out code (#208843)
Commit: 8a4a2aed7d758d004576c5fa3666dcfe9e669728
https://github.com/llvm/llvm-project/commit/8a4a2aed7d758d004576c5fa3666dcfe9e669728
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/docs/GettingStarted.md
Log Message:
-----------
[GettingStarted] Clarify Python requirement. (#208790)
We don't support building LLVM without python in any configuration;
clarify that it's a hard requirement.
Commit: cf51c12c49526af7f9291a6f060b31def85b9a24
https://github.com/llvm/llvm-project/commit/cf51c12c49526af7f9291a6f060b31def85b9a24
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/support/File.h
M clang-tools-extra/clang-doc/support/Utils.h
Log Message:
-----------
[clang-doc] Update include guards in header files (#208840)
These do not follow the style guide, and Utils.h has the wrong macro
definition.
Commit: d09048a46401b8e8385196679a9515516e16288a
https://github.com/llvm/llvm-project/commit/d09048a46401b8e8385196679a9515516e16288a
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/include/clang/AST/ASTNodeTraverser.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtCXX.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Scope.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprClassification.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/StmtCXX.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseInit.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/CMakeLists.txt
M clang/lib/Sema/IdentifierResolver.cpp
M clang/lib/Sema/Scope.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
A clang/lib/Sema/SemaExpand.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaStmtAttr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/AST/ast-dump-expansion-stmt.cpp
A clang/test/AST/ast-print-expansion-stmts.cpp
A clang/test/CodeGenCXX/cxx2c-destructuring-expansion-stmt.cpp
A clang/test/CodeGenCXX/cxx2c-enumerating-expansion-statements.cpp
A clang/test/CodeGenCXX/cxx2c-expansion-stmts-control-flow.cpp
A clang/test/CodeGenCXX/cxx2c-expansion-stmts-mangling.cpp
A clang/test/CodeGenCXX/cxx2c-expansion-stmts-templates.cpp
A clang/test/CodeGenCXX/cxx2c-iterating-expansion-stmt.cpp
A clang/test/Parser/cxx2c-expansion-statements-not-backported.cpp
A clang/test/Parser/cxx2c-expansion-statements.cpp
A clang/test/SemaCXX/cxx2c-expansion-statements-shadow.cpp
A clang/test/SemaCXX/cxx2c-expansion-stmts-control-flow.cpp
A clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
M clang/test/SemaTemplate/GH176155.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[Clang] [C++26] Expansion Statements (P1306R5) (#169680)
This implements C++26's expansion statements, i.e.
[P1306R5](https://wg21.link/P1306R5).
An expansion statement is implemented using a number of new AST
nodes. Since an expansion statement is a template, we need it to be
a dependent DeclContext, but only nodes that inherit from Decl can
be DeclContexts, for which reason this introduces a CXXExpansionStmtDecl.
This holds a synthesised constant template parameter used as the
expansion index as well as a 'CXXExpansionStmtPattern' and a
'CXXExpansionStmtInstantiation.
These two AST nodes are similar to the semantic vs syntactic form
of an InitListExpr: the 'Pattern' represents an unexpanded expansion
statement, and the resulting AST after expansion is stored in an
'Instantiation'.
Since expansion statements require us to perform template instantiation
*inside* a function without instantiating the rest of a function, I had to
remove a number of assertions in the template instantiation engine (e.g.
the assertion that a function parameter must always have an instantiation
by the time we encounter a DeclRefExpr to it no longer holds).
For more implementation details, see the corresponding doc comments
in DeclTemplate.h and StmtCXX.h.
There is some follow up work to be done after this lands, which is
tracked in #207776.
Commit: 4df43305b846fd5cb8da85da6d23272985d1d1ba
https://github.com/llvm/llvm-project/commit/4df43305b846fd5cb8da85da6d23272985d1d1ba
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
M lldb/test/API/linux/aarch64/permission_overlay/TestAArch64LinuxPOE.py
Log Message:
-----------
[lldb][test] Update whitespace of `register read` in some tests (#208838)
#188049 changed the formatting of `register read` output. A few tests
are failing now due to small space changes.
Commit: ed1e356f888ff3bfa846ad4902d4645030bc0a6d
https://github.com/llvm/llvm-project/commit/ed1e356f888ff3bfa846ad4902d4645030bc0a6d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
A clang/test/Driver/amdgpu-openmp-gpu-max-threads-per-block.c
A clang/test/Frontend/openmp-warn-gpu-max-threads-per-block.c
Log Message:
-----------
clang/AMDGPU: Remove driver restriction on --gpu-max-threads-per-block (#204864)
Commit: 3b36c2d642778249dd6f15249a827be979fafbb7
https://github.com/llvm/llvm-project/commit/3b36c2d642778249dd6f15249a827be979fafbb7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/crash-in-unreachable-code.ll
M llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/nontrivial-unswitch-divergent-target.ll
M llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll
M llvm/test/Transforms/SimplifyCFG/AMDGPU/cttz-ctlz.ll
M llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll
M llvm/test/Transforms/SpeculativeExecution/single-lane-execution.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
M llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll
M llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll
M llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll
M llvm/test/Transforms/StructurizeCFG/structurizer-keep-perf-md.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/narrow-phi-of-shuffles.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/no-scalarize-vector-extract.ll
Log Message:
-----------
AMDGPU: Migrate Analysis/Transforms tests to amdgpu subarch triple (4) (#208812)
Continue migrating command-line target spelling on RUN lines to the
folded amdgpu subarch triple form, covering the remaining Transforms tests in
this group.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: a8ba0ad546660542b7200cd8269574b988c89f86
https://github.com/llvm/llvm-project/commit/a8ba0ad546660542b7200cd8269574b988c89f86
Author: Lukas Stephan <kulst at mailbox.org>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/convert-fp-i128.ll
Log Message:
-----------
[NVPTX] Expand fp/int conversions involving integers wider than 64 bits (#201679)
NVPTX does not support direct PTX conversion instructions between
floating point types and integer types wider than 64 bits.
Previously, such conversions could reach instruction selection and fail
with an _unsupported library call operation_ error.
Reproducer on godbolt: https://godbolt.org/z/G6Yr9cE1d
This patch sets the maximum supported fp/int conversion width to 64 bits
so larger conversions are expanded before instruction selection.
It also adds a regression test for 128-bit integer/floating-point
conversions.
Related to #191013
Co-authored-by: Justin Fargnoli <jfargnoli at nvidia.com>
Commit: 5a73020f0261922e1f30cd458f7d0bd757fb9ba1
https://github.com/llvm/llvm-project/commit/5a73020f0261922e1f30cd458f7d0bd757fb9ba1
Author: Mike Kruskal <mkruskal at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
[compiler-rt] [sanitizer_common] Add a testcase reproducing SIGSEGV in ForEachMappedRegion (#208358)
Likely related to https://github.com/llvm/llvm-project/issues/84482 and
https://github.com/llvm/llvm-project/issues/21068
Assisted-by: Gemini
Commit: 7e89dcfba2dcc4d85f04c05a3fee483b6d2e3150
https://github.com/llvm/llvm-project/commit/7e89dcfba2dcc4d85f04c05a3fee483b6d2e3150
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M flang/test/Lower/OpenMP/defaultmap.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir
A offload/test/offloading/fortran/map-zero-size-array.f90
Log Message:
-----------
[Flang][OpenMP] Support mapping of zero-sized arrays (#208133)
Whilst there is no data in theory to map with a zero sized array, the
Fortran OpenMP specification considers the case of a zero sized array
being mapped to device as the data being present on device. This
includes both the data and the descriptor, and it should fundamentlaly
work as a zero-sized array would on device with the respective Fortran
functions for presence and size checking etc.
We can't actually map a nullptr to device and expect it to be present in
current OpenMP (for good reason), however, thankfully, a zero sized
array isn't actually a nullptr, it is a descriptor contianing an
allocated 1-byte of data. So, we can map this to device, alongside the
descriptor and then the zero sized array is correctlly on device for all
intents and purposes. This case is notably different from a
non-allocated or non-zero sized array so we can do this without shooting
ourselves in the foot.
Commit: a9a709f01bfb6204816db9b3bedbe4b627c4bfc3
https://github.com/llvm/llvm-project/commit/a9a709f01bfb6204816db9b3bedbe4b627c4bfc3
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/include/clang/Sema/Scope.h
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/Scope.cpp
Log Message:
-----------
[Clang] [NFC] Use ScopeFlags for expansion statement scopes (#208849)
Previously, we were using a separate `bool` member in `Scope` for this
because we ran out of bits in `ScopeFlags`. #198436 recently freed up a
bit for this, so switch to using it instead.
Fixes #207774.
Commit: 1dd5ad4c3342313a7b8804277db9395c5326eb9b
https://github.com/llvm/llvm-project/commit/1dd5ad4c3342313a7b8804277db9395c5326eb9b
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
A clang/test/CodeGenCXX/msvc-global-delete-scalar-array-split.cpp
A clang/test/CodeGenCXX/msvc-global-delete-scope-no-dtor.cpp
A clang/test/CodeGenCXX/msvc-no-global-delete-forwarding.cpp
M clang/test/CodeGenCXX/msvc-vector-deleting-dtors-sized-delete.cpp
M clang/test/Modules/glob-delete-with-virtual-dtor.cpp
M clang/test/Modules/msvc-vector-deleting-destructors.cpp
M clang/test/PCH/glob-delete-with-virtual-dtor.cpp
M clang/test/PCH/msvc-vector-deleting-destructors.cpp
Log Message:
-----------
[clang][win] MSVC-compat: Use `__global_delete` wrapper in deleting destructors instead of directly referencing `::operator delete` (#188372)
When Clang emits scalar/vector deleting destructors for classes with a
class-level `operator delete`, it generates a conditional dispatch that
can call either the class-level or global `::operator delete`. The
global path directly referenced `::operator delete`, causing `LNK2001`
linker errors in environments where no global `::operator delete`
exists.
MSVC handles this by calling `__global_delete` (and
`__global_array_delete` for vector deletes) - this is a compiler
generated function that is ONLY defined if there is a direct call to
global `::operator delete` for type with non-trivial destructors.
Additionally, it always emits an empty `__empty_global_delete` and uses
`/ALTERNATIVENAME` linker arg to default `__global_delete` (and
`__global_array_delete`) to `__empty_global_delete` if there is NEVER an
delete operator call that would triffer the body to be emitted (thus the
empty function should never be called).
This change aligns Clang's behavior with MSVC when MSVC compatibility
mode and non-LLVM 21 ABI is used, with one difference: the LLVM
generated `__empty_global_delete` traps since it should never be called.
Commit: 1b879464b362c7dc591ac7b5ce4fd78b2353fe30
https://github.com/llvm/llvm-project/commit/1b879464b362c7dc591ac7b5ce4fd78b2353fe30
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
A clang/include/clang/Basic/AtomicLineLogger.h
A clang/lib/Basic/AtomicLineLogger.cpp
M clang/lib/Basic/CMakeLists.txt
A clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/Basic/CMakeLists.txt
Log Message:
-----------
[clang] Adding an Atomic Line Logger (#205395)
This PR adds an atomic line logger to `clang`.
Situations have arisen where `clang` performs multi-threaded tasks (such
as dependency scanning), and race conditions may happen. Such race
conditions are difficult to debug using either `lldb` or with
`llvm::errs()`.
This logger provides atomic logging per line to a file on disk with time
stamps at each line to facilitate such investigations. Specifically, the
logger is designed with the following properties:
1. Each line is atomically written to the backing file. This avoids
concurrent writes making the output text interleaving.
2. Each line is prefixed with a timestamp, a process ID and a thread ID.
3. `LogLine` implements a `<<` operator to allow arbitrary printable
types to be piped into it.
4. The `LogLine`'s user does not need to check if it is setup or valid.
A LogLine is always valid and can always accept input from `<<`. It
becomes a no-op if the `LogLine` object is returned from a default
constructed `AtomicLineLogger`.
5. The write happens when a `LogLine` object goes out of scope.
The logger is inspired by the
[OnDiskCASLogger](https://github.com/llvm/llvm-project/blob/09abee845d2136630fc3f50524148daa55a740a8/llvm/include/llvm/CAS/OnDiskCASLogger.h#L33).
A followup PR https://github.com/llvm/llvm-project/pull/195896 wires up
this logger to clang's dependency scanning stack.
Assisted-by: claude-opus-4.6
rdar://39907408
Commit: b5a7d1e675f222f7e6a3d3e6536e2214c415e1b6
https://github.com/llvm/llvm-project/commit/b5a7d1e675f222f7e6a3d3e6536e2214c415e1b6
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
Log Message:
-----------
[lldb] Fix SymbolFilePDBTests build for StringRef FileSpec getters (#208857)
f9b5264523b1 changed FileSpec::GetDirectory() to return llvm::StringRef
instead of ConstString. ConstString had an operator bool, so the guard
```
if (left.GetDirectory() && right.GetDirectory())
```
compiled. StringRef has neither a bool conversion nor operator&&, so the
test no longer builds. Check for a non-empty directory instead, which
preserves the original "if BOTH have a directory" intent.
Commit: 18f8a356957608d8b6c4318698af53aa4f27a36f
https://github.com/llvm/llvm-project/commit/18f8a356957608d8b6c4318698af53aa4f27a36f
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/include/lldb/Utility/Policy.h
M lldb/source/Utility/Policy.cpp
Log Message:
-----------
[lldb] Make PolicyStack::Get() out-of-line (#208815)
LLDB builds with hidden visibility by default, so a function-local
static in an inline function is not shared across shared library
boundaries: each dylib that includes this header and calls an inline
Get() gets its own private copy of the thread_local stack, silently
splitting one logical per-thread stack into several. Declaring it
out-of-line ensures every dylib resolves to the single instance defined
in Policy.cpp.
Nothing currently pushes a policy from outside liblldb, so this has no
observable effect yet, but any future capability that needs to be set in
one shared library and read in another depends on this.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: a35565161078268c253df85369b3878ca33c726b
https://github.com/llvm/llvm-project/commit/a35565161078268c253df85369b3878ca33c726b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/test/API/functionalities/statusline/TestStatusline.py
A lldb/test/API/functionalities/statusline/statusline_flood.py
Log Message:
-----------
[lldb] Serialize scripted-command output with the statusline (#208609)
A Python command's print() writes to sys.stdout, which the interpreter
session pointed at the debugger's raw terminal descriptor via
PyFile_FromFd. Those writes bypass the debugger's output lock, so they
can race with the statusline, resulting in truncated output. Back the
session's terminal stdout and stderr with a pipe instead. A reader
thread drains the pipe and writes to the terminal through
Debugger::PrintAsync, which takes the same output lock as the
statusline.
Only redirect when a statusline could actually be drawing: the pipe and
reader thread are set up only when StatuslineSupported() holds
(show-statusline is enabled and the output is an escape-code-capable
terminal) and the target is the debugger's own terminal. The interactive
interpreter opts out entirely, since input()'s readline line editing and
echo need both sys.stdin and sys.stdout to be the real terminal.
Python still gets a real line-buffered text file over the pipe, so
output stays live and file objects passed to SB APIs
(SetImmediateOutputFile, subprocess, fileno) keep working. On session
teardown the wrappers are flushed before the pipe is closed so a
retained sys.stdout does not strand a trailing line or write into a
closed descriptor.
rdar://181841574
Commit: 8e955ee22fbd1bd41e8adb9a0c333113824f1dfe
https://github.com/llvm/llvm-project/commit/8e955ee22fbd1bd41e8adb9a0c333113824f1dfe
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
M lldb/source/DataFormatters/TypeCategoryMap.cpp
Log Message:
-----------
[lldb] TypeCategoryMap: Replace ConstString with StringRef (#208117)
I plan on removing ConstStrings from DataFormatters where possible.
There's a lot of entangled classes in DataFormatters but TypeCategoryMap
feels approachable to start with.
Commit: ea2148117950cbc0236ff3416fffa58a44f58fb1
https://github.com/llvm/llvm-project/commit/ea2148117950cbc0236ff3416fffa58a44f58fb1
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaExpand.cpp
Log Message:
-----------
[Clang] Fix APSInt width of template argument in FinishCXXExpansionStmt() (#208859)
After merging #169680, we started getting assertions in
IntegerLiteral::Create() on some ARM systems:
```
Assertion `V.getBitWidth() == C.getIntWidth(type) &&
"Integer type is not the correct size for constant."'
```
The expansion statements patch doesn't ever create an IntegerLiteral
directly, but there is one place where we create a TemplateArgument of
type 'ptrdiff_t', but we unconditionally set the bit width of its APSInt
to 64 bits.
Presumably, the assertion is due to 'ptrdiff_t' not being a 64-bit type
on these systems, so make sure that we query its bit width and use that
as the width of the APSInt.
I don't have a way of verifying if this patch fixes the CI issue since
pre-commit CI doesn't run on the affected system and I don't have an ARM
machine, but I'm merging this anyway since this issue is breaking CI and
querying the width of 'ptrdiff_t' is something we should be doing here regardless.
Commit: 20e952ec610f0ff99fe67dd69f1eac86b6132bda
https://github.com/llvm/llvm-project/commit/20e952ec610f0ff99fe67dd69f1eac86b6132bda
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/include/clang/Basic/OpenCLOptions.h
M clang/lib/Sema/SemaOpenCL.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaOpenCL/access-qualifier.cl
M clang/test/SemaOpenCL/fp64-fp16-options.cl
M clang/test/SemaOpenCL/storageclass.cl
M clang/test/SemaOpenCL/unsupported-image.cl
Log Message:
-----------
[OpenCL] Fix extensions checks for 3.1 (#208370)
These extension checks apply to 3.1 as well.
This fix kernel build fails when OpenCL 3.1 is enabled in
https://github.com/intel/opencl-clang/pull/752
Assisted-by: Claude
Commit: 43ef833f39af617eea9850a1818d74ac376296ae
https://github.com/llvm/llvm-project/commit/43ef833f39af617eea9850a1818d74ac376296ae
Author: Andrew Haberlandt <ahaberlandt at apple.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/compiler_rt_scalbn_test.c
M compiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[Darwin] Mark scalbn tests unsupported on macOS 26.4 (#208858)
Commit: a1feacb3e4fdf447ca15052cf4124d06691bf56a
https://github.com/llvm/llvm-project/commit/a1feacb3e4fdf447ca15052cf4124d06691bf56a
Author: Jade Abraham <jademabraham17 at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/CMakeLists.txt
Log Message:
-----------
Add build option CLANG_INCLUDE_EXAMPLES (#187317)
Adds a new build option for clang, CLANG_INCLUDE_EXAMPLES, which
controls if the examples directory is included in the build. It defaults
to the value for LLVM_INCLUDE_EXAMPLES (same as CLANG_INCLUDE_DOCS and
CLANG_INCLUDE_TESTS)
Signed-off-by: Jade Abraham <jademabraham17 at gmail.com>
Commit: 7d38440aecf6c131f3c8887afea759b102ae2704
https://github.com/llvm/llvm-project/commit/7d38440aecf6c131f3c8887afea759b102ae2704
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
Log Message:
-----------
[libc++] Replace the of use custom sections for detecting overriden functions (#208330)
This is a follow up to #133876 and an alternative to #120805 which
doesn't rely on aliases and works across both ELF and Mach-O. This
mechanism is preferable in baremetal environments since it doesn't
require special handling of the custom sections.
Commit: a83ec0fb845e04b1b579decc4cc8f56245267c16
https://github.com/llvm/llvm-project/commit/a83ec0fb845e04b1b579decc4cc8f56245267c16
Author: Congzhe Cao <congzhe.cao at huawei.com>
Date: 2026-07-10 (Fri, 10 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Transforms/Utils/CloneFunction.cpp
Log Message:
-----------
[Utils] Improve documentation for `cloneLoopWithPreheader()` (#208817)
Fixed #191471.
The client needs to further update the CFG and DominatorTree after
calling `cloneLoopWithPreheader()` to ensure the IR remains valid,
the function itself does not automatically update the control flow fully.
Clarified and improved the comments for the function.
Commit: 184d97baded92622778a701b66e7f148903f3525
https://github.com/llvm/llvm-project/commit/184d97baded92622778a701b66e7f148903f3525
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
Log Message:
-----------
[Clang] [Docs] Add release note for expansion statements (#208878)
This was supposed to be part of the original patch, but we lost it
because I didn't pay enough attention when I was merging the release
notes after the migration from RST -> MD (I deleted the RST file but
forgot to move the release note to the MD file...)
Commit: 1a8a53f30e386b0b136e833bfd7fb83839035f37
https://github.com/llvm/llvm-project/commit/1a8a53f30e386b0b136e833bfd7fb83839035f37
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M orc-rt/lib/executor/Logging.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Hold log level names as uppercase (#208880)
orc_rt_log_Level_getName is used primarily in text prefixes (e.g. the
upcoming printf backend's "[orc-rt:General:LEVEL]"), where uppercase is
the intended rendering. Storing the names as uppercase lets the backend
use them directly without case conversion. orc_rt_log_Level_parse
performs a case-insensitive parse, so ORC_RT_LOG=info and similar still
work.
[orc-rt] Hold log level names as uppercase.
orc_rt_log_Level_getName is expected to be primarily used in
text-prefixes (e.g. in the upcoming printf backend), where it should be
printed as uppercase. Storing as uppercase in the first place will save
us a toupper conversion on each log call.
Commit: 4d5856669efa7a1271d2f5201bb3ebf32420ffde
https://github.com/llvm/llvm-project/commit/4d5856669efa7a1271d2f5201bb3ebf32420ffde
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
Log Message:
-----------
[GlobalISel][AArch64] Improve legalization of shift amounts (#208676)
Fixes crashes when the shift amount type is already between s32 and s64,
but not s32 or s64.
The shift amount should have the same type with the shifted value for
the shift instructions, so add the same `widenScalarToNextPow2`
legalization that we apply to the shifted value, to the shift amount.
Fixes crashes in programs like:
define i8 @test(i48 %a) {
entry:
%b = lshr i48 %a, 15
%c = trunc i48 %b to i8
ret i8 %c
}
The new test crashes before this PR.
Commit: 0730f680b6ac237ee1c81b2c55a741ba7065ee97
https://github.com/llvm/llvm-project/commit/0730f680b6ac237ee1c81b2c55a741ba7065ee97
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-auto-parameters.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-auto.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-lambdas.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-pointer-as-pointers.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-pointer-as-values.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-templates.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-transform-values.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-values.cpp
Log Message:
-----------
[clang-tidy] make `misc-const-correctness` work with `auto` variables and lambdas (#157319)
Fixes #60789.
Currently, the check will never make `auto` variables `const`. Here's
the relevant bit of code:
https://github.com/llvm/llvm-project/blob/6b200e21adec0e28407def6fcb2e6c7359fd881b/clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp#L108-L110
Notice how the matcher's name is `AutoTemplateType`, but it has nothing
to do with templates. What it *was* intended to do, I'm not sure, but
excluding all `auto` variables can't be right.
For lambdas, this is the only justification I can find:
https://github.com/llvm/llvm-project/blob/36627e1724504d783dc1cbc466666516d28260e4/clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-values.cpp#L30-L34
Which doesn't convince me.
Looking at the test changes, I believe there's only one new false
positive, and that one seems to be a symptom of an existing problem that
was only being masked by `auto`, but we can absolutely discuss whether
the now-diagnosed cases are correct.
---------
Co-authored-by: Victor Baranov <bar.victor.2002 at gmail.com>
Commit: b2f93b13fea00ea6550b7154a16548f8fe952b63
https://github.com/llvm/llvm-project/commit/b2f93b13fea00ea6550b7154a16548f8fe952b63
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M offload/test/offloading/fortran/declare-target-common-block-main.f90
Log Message:
-----------
[OpenMP][Offload] Fix flang offload test (#208829)
This PR attempts to address the remaining flang offload test failure
after https://github.com/llvm/llvm-project/pull/208617. Bot:
https://lab.llvm.org/buildbot/#/builders/67/builds/8412
The problem with is test is that `foo__l8` kernel was not linked into
device image without explicitly use the amdgpu-amd-amdhsa triple in the
compilation. It only happened to this specific test.
Local test results after fix:
```
Testing Time: 146.44s
Total Discovered Tests: 3478
Skipped : 77 (2.21%)
Unsupported : 341 (9.80%)
Passed : 3055 (87.84%)
Expectedly Failed: 5 (0.14%)
```
Commit: e2223e665eccd0580c3f1c9d4d31b2262a8ca823
https://github.com/llvm/llvm-project/commit/e2223e665eccd0580c3f1c9d4d31b2262a8ca823
Author: David Green <david.green at arm.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
M llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
Log Message:
-----------
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
A TBL with out-of-range values will place zero into the respective
vector lane. Use this to generate a more efficient 1 operand TBL where
possible.
Commit: ced9fa35844724063b20d4b0d67a7960247c8067
https://github.com/llvm/llvm-project/commit/ced9fa35844724063b20d4b0d67a7960247c8067
Author: wanglei <wanglei at loongson.cn>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/test/Interpreter/emulated-tls.cpp
Log Message:
-----------
[clang][test] Fix emulated-tls.cpp failure on LoongArch (#208886)
The LoongArch backend does not support emulated TLS, so
mark the test as unsupported to fix the LoongArch buildbot
failure.
Failure: https://lab.llvm.org/staging/#/builders/20/builds/28875
Commit: 290279b6b69138f4162cace4865713efa12ec262
https://github.com/llvm/llvm-project/commit/290279b6b69138f4162cace4865713efa12ec262
Author: dong jianqiang <dongjianqiang2 at huawei.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/test/CodeGen/ARM/elf-preemption.ll
M llvm/test/CodeGen/ARM/weak-hidden-pic.ll
Log Message:
-----------
[ARM] Use .reloc for weak symbols in PIC mode instead of GOT indirection (#208372)
In ARM ELF PIC mode, weak symbols referenced via the constant pool use a
PC-relative expression like `.long sym-(.LPC+8)`. The assembler eagerly
resolves this when both the symbol and reference are in the same
section, which prevents the linker from overriding a weak definition
with a strong one from another object file.
The previous approach (#198577) forced weak symbols to go through GOT
indirection to avoid this, but that adds an extra load. This patch
instead emits a `.reloc` directive alongside the local PC-relative
expression, forcing the assembler to emit a proper `R_ARM_REL32`
relocation. This lets the linker perform the override without the
runtime cost of a GOT load.
Commit: 72af746a3e19627fc1d1c40bf6eabb2887850ac5
https://github.com/llvm/llvm-project/commit/72af746a3e19627fc1d1c40bf6eabb2887850ac5
Author: Osama Abdelkader <osama.abdelkader at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/DeclSpec.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.stc/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3.cpp
M clang/test/CXX/dcl/dcl.fct/p17.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/Parser/c2x-auto.c
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/static-data-member.cpp
Log Message:
-----------
Reject auto combined with type specifiers in C++ (#208552)
Follow-up of https://github.com/llvm/llvm-project/pull/166004
- Diagnose C++ declarations that combine `auto` with another type
specifier, such as `auto int` .
- Preserve C/C23 handling where `auto` can still be interpreted as a
storage-class specifier in valid combinations.
- Fix parser disambiguation so `auto Use = 0` treats `Use` as the
declarator name before type lookup, avoiding ambiguous lookup
regressions.
---------
Signed-off-by: Osama Abdelkader <osama.abdelkader at gmail.com>
Commit: cce2b5acd7b0307c7985d58e7348a3e06b928eb4
https://github.com/llvm/llvm-project/commit/cce2b5acd7b0307c7985d58e7348a3e06b928eb4
Author: Yanzuo Liu <zwuis at outlook.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/RedundantParenthesesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/redundant-parentheses.cpp
Log Message:
-----------
[clang-tidy] Support parentheses around subscript operators in readability-redundant-parentheses (#208759)
Subscript operators have the same operator procedure as function calls.
Treat overloaded `()` as built-in operators as a drive-by. I missed this
case when reviewing #192254.
Commit: d5ff29d5b4b9cd7ba446d1cff138a8e626ec27d0
https://github.com/llvm/llvm-project/commit/d5ff29d5b4b9cd7ba446d1cff138a8e626ec27d0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
M llvm/test/CodeGen/AMDGPU/a-v-ds-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-ds-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/aa-as-infer.ll
M llvm/test/CodeGen/AMDGPU/aa-points-to-constant-memory.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/abs_i16.ll
M llvm/test/CodeGen/AMDGPU/abs_i32.ll
M llvm/test/CodeGen/AMDGPU/absdiff.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/add-debug.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/add.i16.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add3.ll
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/add_shl.ll
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
M llvm/test/CodeGen/AMDGPU/add_u64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-captured.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-cse.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
M llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-av-scopes.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis-heuristics.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (5) (#208834)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: a9987b7049c11e2f5694a4ab69ffcfc785080758
https://github.com/llvm/llvm-project/commit/a9987b7049c11e2f5694a4ab69ffcfc785080758
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-export-kernel-runtime-handles.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare-crash-splat.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-libcall-sincos-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-miscellaneous-uniform-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-nsa-threshold.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-num-agpr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-prepare-agpr-alloc.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-demanded-bits-for-target-node.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ceil.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-copysign.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-exp.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-exp2.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-fabs.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-floor.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-fma.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-fmax-splat.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-fmax.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-fmin-splat.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-fmin.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp-splat.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-log.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-log10.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-log2.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-mad.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rint.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-round.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.defined.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.defined.sin.cos.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.nobuiltins.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.weak.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sqrt.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-trunc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-unexpected-types.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-lower-all.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-lower-none.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (6) (#208835)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4f94d25bc15865037cf5fd7c228012f8204d3eda
https://github.com/llvm/llvm-project/commit/4f94d25bc15865037cf5fd7c228012f8204d3eda
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-alloca-placement.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-none.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-O0.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-unroll-threshold.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-chain-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal.ll
M llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
M llvm/test/CodeGen/AMDGPU/and-gcn.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/and_or.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/annotate-existing-abi-attributes.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll
M llvm/test/CodeGen/AMDGPU/annotate-noclobber.ll
M llvm/test/CodeGen/AMDGPU/anonymous-gv.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float.ll
M llvm/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
M llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
M llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/ashr64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-merge-empty-other.mir
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_add.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_sub.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (7) (#208836)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: d90e6c8674724dedb21bc20e2b47c378a471275b
https://github.com/llvm/llvm-project/commit/d90e6c8674724dedb21bc20e2b47c378a471275b
Author: Philipp Rados <philipp.rados at openchip.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/StackColoring.cpp
A llvm/test/CodeGen/RISCV/stack-coloring-large-stack.ll
Log Message:
-----------
[StackColoring] Change TotalStackSize from unsigned to int64_t (#208671)
StackColoring tracks the total size of the stack as `unsigned int`. This
will wrap around, even on 64-bit systems, if the stack is greater than
that resulting in a wrong size. This can happen on both PPC and RISCV64.
Commit: 4125b6fce8bab893145b265f112d9c9fb2ea609b
https://github.com/llvm/llvm-project/commit/4125b6fce8bab893145b265f112d9c9fb2ea609b
Author: David Green <david.green at arm.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
Log Message:
-----------
[GlobalISel] Improve bf16 converts with fast-math flags. (#200741)
This alters the lowering of bf16 G_TRUNC to exclude the check for nan if
the operation being extended is nnan. Flags are then threaded through so
that the G_FPEXT and G_FPTRUNC from promoted nodes keep the same FMF.
Commit: a54fc1f407d4d05a51688638230e54761831d31a
https://github.com/llvm/llvm-project/commit/a54fc1f407d4d05a51688638230e54761831d31a
Author: David Green <david.green at arm.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
Log Message:
-----------
[AArch64][GlobalISel] Extend handling to bf16 vecreduce. (#208684)
This alters the extension of f16 vecreduce to bf16, allowing us to
handle the non-strict fadd and fmul reductions, along with fmin and fmax
variants.
Commit: 79ebcadfd492bb22c2c96e651146bd10b6bd8ae9
https://github.com/llvm/llvm-project/commit/79ebcadfd492bb22c2c96e651146bd10b6bd8ae9
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
A clang/test/Analysis/block-in-critical-section-raii.cpp
Log Message:
-----------
[analyzer] Prevent inlining RAII ctors/dtors (#208729)
BlockInCriticalSectionChecker registers the pre-call for the RAII ctors
and Dtors - and also the raw 'lock' and 'unlock' handlers.
However, pre-call does not prevent inlining. This means that (in the
likely case of) that the body is present, the analyzer will model the
effect of the lock twice. This happens on libc++ unique_lock.
We really should have eval-called the ctor/dtor to avoid the inlining of
those, but here we are.
rdar://175814310
Commit: e490b437555b1f5fce7636d383fc2d7f22097577
https://github.com/llvm/llvm-project/commit/e490b437555b1f5fce7636d383fc2d7f22097577
Author: Luan Rabelo <96793857+Lu4nScr1pt1ng at users.noreply.github.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
A clang/test/Analysis/html_diagnostics/variable-popups-eol.c
Log Message:
-----------
[analyzer] Fix invalid HTML nesting for popups at end of line (#207793)
The static analyzer's HTML reports contain misnested tags whenever a
variable with a `variable_popup` is the last token on a source line.
`AddLineNumber` inserts the row-closing `</td></tr>` with `InsertTextBefore`, which
places it in front of text previously inserted at the same offset. As a result,
the popup's closing `</table></span>` tags and the arrow anchor `</span>`
tags end up outside the table row. HTML parsers (jsoup, pup) and validators
reject the file from that point on.
Before:
<span class='variable'>b</td></tr><table
class='variable_popup'>...</table></span></span></span>
<img width="786" height="414" alt="image"
src="https://github.com/user-attachments/assets/023461ad-73e4-424e-a4fb-42faf7a945f0"
/>
After:
<span class='variable'>b<table
class='variable_popup'>...</table></span></span></span></td></tr>
<img width="877" height="477" alt="image"
src="https://github.com/user-attachments/assets/cf8aada4-21c8-4af7-9e07-c2d8cc1d0724"
/>
The fix inserts `</td></tr>` with `InsertTextAfter` so tags closing at
the end-of-line offset stay inside the row. To keep the message bubbles
outside the code rows, the line number table is now added before the path pieces
are processed, and bubbles are inserted after the newline, between the
current and the next row.
The pre-existing tests only exercised popups on variables followed by
more tokens (`if (b)`), which is why this was never caught; the new test
places the variable at the end of the line. This has been broken since at least
clang 10; the earlier fix (D73993 / commit 482e236e569e)
only covered the macro popup variant.
I verified this with the Analysis/html_diagnostics tests, the full
clang/test/Analysis suite, and by running generated reports through an
HTML parser that checks tag nesting: 4 errors before / 0 after on the
reproducer above, and 8 → 0 on a larger file with macro popups, multiple
events per line, and mid-line popups. The visible report content is
unchanged.
Fixes #46089
Commit: 847fe431d082fe134ea88031ca3705792fb1bb61
https://github.com/llvm/llvm-project/commit/847fe431d082fe134ea88031ca3705792fb1bb61
Author: Jerry Dang <kuroyukiasuna at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
A llvm/test/CodeGen/AArch64/preserve-all-large-csr.ll
Log Message:
-----------
[AArch64] Fix miscompilation due to integer overflow in immediate offset for stack store/load instructions with preserve_all (#207026)
Fix AArch64 framelowering bug exposed by a preserve_all function that
spills 30+ callee-saved registers: paired stp/ldp offsets overflows the
signed 7-bit immediate, fixed by spilling those registers as single
str/ldr instead.
AI Usage Disclosure
AI was used to help the:
- investigation process
- suggestion of solution
- suggestion of comment wordings
Fixes #204564
Commit: 9d5d8834793da9efe297620db3ef39633688f830
https://github.com/llvm/llvm-project/commit/9d5d8834793da9efe297620db3ef39633688f830
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
Log Message:
-----------
[AggressiveInstCombine] Fix crash when folding consecutive loads into a type smaller than the combined load (#207229)
Commit: a11e844f4e3302d47c7934e4817f14639e510aad
https://github.com/llvm/llvm-project/commit/a11e844f4e3302d47c7934e4817f14639e510aad
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
Log Message:
-----------
[clang][LifetimeSafety] Short-circuit joins of identical immutable containers (#208908)
Commit: 31ddc7e564814a42af39f0e71371469d0b1fca24
https://github.com/llvm/llvm-project/commit/31ddc7e564814a42af39f0e71371469d0b1fca24
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M mlir/lib/Analysis/Presburger/Matrix.cpp
Log Message:
-----------
[mlir][presburger] Avoid redundant zero-initialization in insertColumns (#199911)
When insertColumns does not trigger a physical reallocation, the inner
loop needlessly loops up to nReservedColumns - 1. This causes massive
redundant zero-writes on trailing columns that are already zero. This
patch truncates the inner loop start boundary to nColumns - 1, when the
reserved capacity is unchanged, optimizing the non-realloc path from
O(nRows * nReservedColumns) to O(nRows * nColumns).
Commit: 670e0a0c147aeade297b3235f5ade3786abd7d4c
https://github.com/llvm/llvm-project/commit/670e0a0c147aeade297b3235f5ade3786abd7d4c
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M clang/test/CodeGen/AArch64/strictfp-builtins.c
M clang/test/CodeGen/X86/strictfp_builtins.c
M clang/test/CodeGen/builtin_float.c
M clang/test/CodeGen/builtin_float_strictfp.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/isfpclass.c
M clang/test/CodeGen/strictfp_builtins.c
M clang/test/Headers/amdgcn-openmp-device-math-complex.c
M clang/test/Headers/amdgcn-openmp-device-math-complex.cpp
M clang/test/Headers/hip-header.hip
M clang/test/Headers/nvptx_device_math_complex.c
M clang/test/Headers/nvptx_device_math_complex.cpp
M clang/test/Headers/openmp_device_math_isnan.cpp
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/Intrinsics.cpp
M llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
A llvm/test/Assembler/print-formatted.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
M llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
M llvm/test/Transforms/Attributor/nofpclass-select.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll
M llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll
M llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/fadd.ll
M llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
M llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
M llvm/test/Transforms/InstCombine/freeze-fp-ops.ll
M llvm/test/Transforms/InstCombine/freeze-phi.ll
M llvm/test/Transforms/InstCombine/is_fpclass.ll
M llvm/test/Transforms/InstCombine/pr80941.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
M llvm/test/Transforms/InstSimplify/canonicalize.ll
M llvm/test/Transforms/LoopVectorize/is_fpclass.ll
M llvm/test/Transforms/SLPVectorizer/is_fpclass.ll
M llvm/test/Transforms/Scalarizer/intrinsics.ll
M llvm/test/Transforms/SpeculativeExecution/spec-calls.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
M llvm/test/tools/llubi/intr_fp_is_fpclass.ll
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Log Message:
-----------
[IR] Use pretty printing for mask in is_fpclass (#207653)
The second argument of `llvm.is_fpclass` is a mask, where each bit
represents a floating-point class. Understanding the check that the call
makes in an IR dump requires additional effort. To simplify the
interpretation of IR dumps, a previously implemented pretty-printing
mechanism can be used:
https://github.com/llvm/llvm-project/commit/39e7712ac520ccfc43383b3e9d6ea8cf2958b8e3.
This commit implements this mechanism for printing the arguments of
`llvm.is_fpclass`.
This change also fixes the printing of argument names: if an argument
name is absent, it is simply not printed.
Commit: 419cce0bb5e5fea52f701a20124f88ea1eee3e29
https://github.com/llvm/llvm-project/commit/419cce0bb5e5fea52f701a20124f88ea1eee3e29
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/docs/ReleaseNotes/23.rst
Log Message:
-----------
[libcxx][NFC] Move release notes for MSVC's implementation of exception_ptr (#208883)
These were accidentally placed in LLVM 22 rather than 23 file.
Commit: 6e01e7334d7b9f8696f5b883b433d56e7a8b2851
https://github.com/llvm/llvm-project/commit/6e01e7334d7b9f8696f5b883b433d56e7a8b2851
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M libcxx/utils/ci/images/libcxx_runners.txt
Log Message:
-----------
[libcxx] Bump runner set (#208929)
This pulls in 6d3cf7f436a01f4622fb660e413a4020209777b8, and
8ece73c9f8b54fea6a98e9e4c55f9a2e6ccc9b3c.
Commit: 09796808802f99c30a23bc0f2cd68243764e84ab
https://github.com/llvm/llvm-project/commit/09796808802f99c30a23bc0f2cd68243764e84ab
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Remove dead member functions (NFC) (#208936)
Remove member functions with no remaining callers anywhere in the tree:
- VPExpressionRecipe::getOperandOfResultType
- VPBlockBase::getSingleHierarchicalSuccessor
- VPIRFlags::hasNonNegFlag
- VPWidenIntOrFpInductionRecipe::getStartValue, which is an exact
duplicate of the inherited VPWidenInductionRecipe::getStartValue.
Commit: 030fdcef27fe29b5e2c1ef0c6c9df6050b51569a
https://github.com/llvm/llvm-project/commit/030fdcef27fe29b5e2c1ef0c6c9df6050b51569a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Re-use VPSlotTracker when printing recipes for costs (NFC). (#203386)
VPRecipeBase::dump() constructs a fresh VPSlotTracker instance on each
call. VPSlotTracker construction requires iterating over all recipes in
the plan, to number all VPValues.
To avoid doing lots of unnecessary work when printing VPlan costs,
construct a shared VPSlotTracker in VPCostContext, re-used by all
prints.
This can speed up debug output for large loops.
PR: https://github.com/llvm/llvm-project/pull/203386
Commit: 5742a30a749a5cc9271bd5bd8945c3033285c775
https://github.com/llvm/llvm-project/commit/5742a30a749a5cc9271bd5bd8945c3033285c775
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_single_lane.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-cas-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups_error_check.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/attr-unparseable.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
M llvm/test/CodeGen/AMDGPU/av-invalid-scope.ll
M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
M llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
M llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/basic-call-return.ll
M llvm/test/CodeGen/AMDGPU/basic-loop.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16-ops.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
M llvm/test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx10.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_sat.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-unsupported-errors.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-intrinsic-mmo-type.ll
M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/buffer-store-dwordx4-vpk-mul-war-hazard-gfx942.mir
M llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (8) (#208837)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c84e264eb8539f05a7347fb12183ea04001bc1a9
https://github.com/llvm/llvm-project/commit/c84e264eb8539f05a7347fb12183ea04001bc1a9
Author: David Green <david.green at arm.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
Log Message:
-----------
[AArch64][GlobalISel] Add test coverage for bf16 fptosi.sat. NFC (#208955)
Commit: 63f4d28adf0af9f275f6c09450d5a48d451b59b1
https://github.com/llvm/llvm-project/commit/63f4d28adf0af9f275f6c09450d5a48d451b59b1
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M lld/ELF/RelocScan.h
M lld/test/ELF/i386-tls-ie-shared.s
Log Message:
-----------
[ELF] Fix data race when handleTlsIe adds a RELATIVE relocation (#208956)
The ieExpr == R_GOT PIC case (e.g. R_386_TLS_IE in -shared links) calls
the unsynchronized addRelativeReloc from concurrent scanSectionImpl
tasks, racing on relaDyn->relativeRelocs. Use the sharded variant like
processAux. Split i386-tls-ie-shared.s into two input files so that a
ThreadSanitizer build detects the race.
Commit: 905f654bb721f1df119bd2cfaa23736e30838e90
https://github.com/llvm/llvm-project/commit/905f654bb721f1df119bd2cfaa23736e30838e90
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SPARCV9.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/RelocScan.h
M lld/ELF/Relocations.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Target.h
Log Message:
-----------
[ELF] Replace getThreadIndex with explicit shards in RelocScan. NFC (#208959)
Parallel relocation scanning (https://reviews.llvm.org/D133003) appends
dynamic relocations to `relocsVec[parallel::getThreadIndex()]`.
`getThreadIndex` returns -1u on main, which is a known hazard.
Instead, run one scan task per worker via `parallelFor`, with tasks
claiming object files off a shared counter, and pass the task index
through scanSection/RelocScan as the relocsVec shard.
Commit: 410a2a236355a432c6a73cbd3338badabd280dc8
https://github.com/llvm/llvm-project/commit/410a2a236355a432c6a73cbd3338badabd280dc8
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.reverse/pstl.reverse_copy.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Default implementation of parallel std::reverse_copy (#208085)
This PR adds a default parallel implementation of `std::reverse_copy`
based on `std::reverse_iterator` + parallel `std::copy`.
Effectively it's a one-liner:
```c++
return _Copy()(__policy,
std::reverse_iterator<_BidirectionalIterator>(std::move(__last)),
std::reverse_iterator<_BidirectionalIterator>(std::move(__first)),
std::move(__result));
```
Included tests check that:
- Semantics of the function is correct.
- The function correctly SFINAE out when the first argument is not an
execution policy.
- The `nodiscard` policy is followed.
- The `noexcept` policy is followed.
- `static_assert` verifies iterators' categories (bidirectional and
forward).
Part of #99938.
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: d6d0ccce19d1dee79fd9b5b655aae554e7455d97
https://github.com/llvm/llvm-project/commit/d6d0ccce19d1dee79fd9b5b655aae554e7455d97
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/JSONTransport.h
M lldb/include/lldb/Protocol/MCP/Client.h
M lldb/include/lldb/Protocol/MCP/Server.h
M lldb/source/Protocol/MCP/Client.cpp
M lldb/source/Protocol/MCP/Server.cpp
M lldb/tools/lldb-mcp/Multiplexer.cpp
M lldb/tools/lldb-mcp/Multiplexer.h
M lldb/tools/lldb-mcp/lldb-mcp.cpp
M lldb/unittests/Host/JSONTransportTest.cpp
M lldb/unittests/Protocol/MCPServerInfoTest.cpp
M lldb/unittests/tools/CMakeLists.txt
A lldb/unittests/tools/lldb-mcp/CMakeLists.txt
A lldb/unittests/tools/lldb-mcp/MultiplexerTest.cpp
Log Message:
-----------
[lldb-mcp] Multiplex across all discovered LLDB instances (#208827)
Connect to every LLDB MCP server advertised under ~/.lldb rather than a
single one, and present them to the client as one server. A stale
registry entry from a crashed instance simply fails to connect and is
skipped.
Each instance is identified by the pid of its lldb process, now recorded
in the ServerInfo registry file. Tools and resources are addressed with
instance-qualified URIs, e.g. lldb-mcp://instance/{pid}/debugger/{id}
and lldb://instance/{pid}/debugger/{id}/target/{idx}. Listing requests
(sessions_list, resources/list) fan out to every backend and aggregate;
targeted requests (command, resources/read) are routed by the pid parsed
from the URI. Backends only know their local lldb-mcp://debugger/{id}
form, so URIs are rewritten in both directions.
Add Binder::FailPendingRequests (and Client::CancelPendingRequests) so
that when the client disconnects with a request still in flight to a
backend, the abandoned reply is satisfied with an error instead of being
destroyed unanswered, which would trip the binder's "must reply" assert.
The multiplexer cancels its backends on shutdown before unwinding.
Assisted-by: Claude
Commit: 074c4b35fba7eb7bfbb514e5ebdf16b1ff074311
https://github.com/llvm/llvm-project/commit/074c4b35fba7eb7bfbb514e5ebdf16b1ff074311
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
Log Message:
-----------
[ELF] Replace getThreadIndex with explicit shards in markLive. NFC (#208974)
The parallel mark loop appends deeper discoveries to per-thread queues
indexed by `parallel::getThreadIndex()`, the last getThreadIndex user in
lld. Instead, have each worker claim frontier items off a shared
counter, accumulating into an explicit shard.
The finer-grained item claiming improves load balancing: the markLive
--time-trace phase is ~5% faster for a clang --gc-sections link and ~4%
for a larger chromium one.
Commit: 61b5d7802713e9634750d24456597b28ca85a335
https://github.com/llvm/llvm-project/commit/61b5d7802713e9634750d24456597b28ca85a335
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
Log Message:
-----------
[CIR][NFC] Add missing enum values related to CXXExpansionStmt (#208919)
Add missing enum values related to CXXExpansionStmt
Commit: 3a6048dbea15390c20e4ea063ffed2c2610fcaaf
https://github.com/llvm/llvm-project/commit/3a6048dbea15390c20e4ea063ffed2c2610fcaaf
Author: Tony Guillot <tony.guillot at protonmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/test/CodeGen/ARM/elf-preemption.ll
M llvm/test/CodeGen/ARM/weak-hidden-pic.ll
Log Message:
-----------
Revert "[ARM] Use .reloc for weak symbols in PIC mode instead of GOT indirection" (#208968)
There is a few breakages between `clang-armv8-quick` failing the
`Interpreter/execute-weak.cpp` test and bots failing linking
`libclang_rt.atomic.so`.
Reverts llvm/llvm-project#208372
Commit: e9e21f520ccd8f4c292686dfdeb04eae080110e3
https://github.com/llvm/llvm-project/commit/e9e21f520ccd8f4c292686dfdeb04eae080110e3
Author: Adam Scott <adamscott200322 at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-load-store.ll
M llvm/test/CodeGen/X86/avx512-mask-op.ll
M llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
R llvm/test/CodeGen/X86/buildvec-strided-loads.ll
M llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
M llvm/test/CodeGen/X86/vector-compress.ll
Log Message:
-----------
Revert [X86] EltsFromConsecutiveLoads - handle trunc(wideload()) patterns (#199371) (#208960)
Reverts llvm/llvm-project#199371.
The strided path emits wide loads without checking that the widened
range is dereferenceable. The last wide load reads up to (stride -
element) bytes past the last element and faults when the data ends at a
page boundary. Flagged by @nikic in
https://github.com/llvm/llvm-project/pull/199371#issuecomment-4947406318.
Reproducer on current main **MADE WITH CLAUDE OPUS**
strided.ll, 8 x i16 at a 4 byte stride, the source only touches bytes
[0, 30):
```llvm
define void @strided8i16(ptr %p, ptr %out) {
%g0 = getelementptr inbounds i8, ptr %p, i64 0
%g1 = getelementptr inbounds i8, ptr %p, i64 4
%g2 = getelementptr inbounds i8, ptr %p, i64 8
%g3 = getelementptr inbounds i8, ptr %p, i64 12
%g4 = getelementptr inbounds i8, ptr %p, i64 16
%g5 = getelementptr inbounds i8, ptr %p, i64 20
%g6 = getelementptr inbounds i8, ptr %p, i64 24
%g7 = getelementptr inbounds i8, ptr %p, i64 28
%v0 = load i16, ptr %g0, align 1
%v1 = load i16, ptr %g1, align 1
%v2 = load i16, ptr %g2, align 1
%v3 = load i16, ptr %g3, align 1
%v4 = load i16, ptr %g4, align 1
%v5 = load i16, ptr %g5, align 1
%v6 = load i16, ptr %g6, align 1
%v7 = load i16, ptr %g7, align 1
%r0 = insertelement <8 x i16> undef, i16 %v0, i32 0
%r1 = insertelement <8 x i16> %r0, i16 %v1, i32 1
%r2 = insertelement <8 x i16> %r1, i16 %v2, i32 2
%r3 = insertelement <8 x i16> %r2, i16 %v3, i32 3
%r4 = insertelement <8 x i16> %r3, i16 %v4, i32 4
%r5 = insertelement <8 x i16> %r4, i16 %v5, i32 5
%r6 = insertelement <8 x i16> %r5, i16 %v6, i32 6
%r7 = insertelement <8 x i16> %r6, i16 %v7, i32 7
store <8 x i16> %r7, ptr %out, align 1
ret void
}
```
driver.c, puts the 30 data bytes flush against a PROT_NONE page:
```c
#include <sys/mman.h>
#include <unistd.h>
#include <string.h>
#include <stdint.h>
#include <stdio.h>
void strided8i16(void *p, void *out);
int main(void) {
long pg = sysconf(_SC_PAGESIZE);
char *m = mmap(0, 2*pg, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
mprotect(m + pg, pg, PROT_NONE); /* unmapped guard page right after */
memset(m, 0x11, pg);
char *p = m + pg - 30; /* data [0,30) ends exactly at page end */
uint16_t out[8];
strided8i16(p, out); /* source touches only bytes [0,30) */
printf(" returned OK, out[0]=%u\n", out[0]);
return 0;
}
```
```
$ llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 -filetype=obj strided.ll -o strided.o
$ cc driver.c strided.o -o repro
$ ./repro; echo "exit: $?"
Segmentation fault (core dumped)
exit: 139
$ llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 -filetype=obj strided.ll -o strided_sse2.o
$ cc driver.c strided_sse2.o -o repro_sse2
$ ./repro_sse2; echo "exit: $?"
returned OK, out[0]=4369
exit: 0
```
With +avx2 the fold fires and emits a 32 byte `vmovdqu (%rdi), %ymm0`
over the 30 byte footprint. With plain sse2 the buildvector stays scalar
and only the accessed bytes are read.
Commit: 9dffcd2752af16a09eeb4131f90a1a0fe2b76a1f
https://github.com/llvm/llvm-project/commit/9dffcd2752af16a09eeb4131f90a1a0fe2b76a1f
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/aarch64-reloc-pauth.s
Log Message:
-----------
[PAC][lld] Properly handle `.relr.auth.dyn` -> `.rela.dyn` movement (#195649)
Address the following issues reported in #171475:
1. Proper adjustment of `__rela_iplt_end` address if a move from
`.relr.auth.dyn` to `.rela.dyn` took place
2. Set `__rela_iplt_start` properly if prior to such movement from
`.relr.auth.dyn`, the `.rela.dyn` was empty
3. Allocate enough space for both RELA* and AARCH64_AUTH_RELR* tags in
the `.dynamic` section in case we end up with both `.relr.auth.dyn` and
`.rela.dyn`. If one of the sections becomes empty - just pad the
`.dynamic` section with null tags in the end.
Resolves #171475
---------
Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>
Commit: 77929619bc93b86e99f6ae6a9b10ef85a27c4c18
https://github.com/llvm/llvm-project/commit/77929619bc93b86e99f6ae6a9b10ef85a27c4c18
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][bytecode] Remove EvalEmitter::OpPC (#208988)
We pass this when evaluting opcodes in EvalEmitter, but we never set it
to anything, so the underlying pointer is always null and we later and
up using the source location of the expression we're evaluating.
This seems to only cause problems when Statement expressions are
involved so far.
Commit: 02a38835c2f0cea609290ead1280d1102042081f
https://github.com/llvm/llvm-project/commit/02a38835c2f0cea609290ead1280d1102042081f
Author: amosher-nvidia <amosher at nvidia.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/LinkerScript.cpp
A lld/test/ELF/linkerscript/tbss-addr-expr.s
Log Message:
-----------
[lld][ELF] Allow explicit address expressions on .tbss output sections (#196447)
D107208 allows consecutive SHF_TLS SHT_NOBITS (.tbss) output sections by
making
each .tbss start at the end address of the previous one
(state->tbssAddr). This
happens unconditionally, so an explicit output section address
(`.tbss ADDR : { ... }`) is silently ignored, unlike GNU ld.
Apply the tbssAddr fallback only when the section has no address
expression.
Some embedded/RTOS applications link the kernel and several mutually
isolated
tasks into a single ELF and require every section, .tbss included, to
sit at a
specific address matching the memory map. Placing a task's .tbss in its
own
protected region is a security boundary: one task must not be able to
modify
another's TLS. Previously lld placed .tbss adjacent to .text in RX
memory
instead of where the linker script directed it, in RW memory.
Commit: 359b99c85332edc17ab5cdbcfb7d272d24509f60
https://github.com/llvm/llvm-project/commit/359b99c85332edc17ab5cdbcfb7d272d24509f60
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
M llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
M llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
M llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll
M llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/broadcast-load-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/broadcast.ll
M llvm/test/Transforms/SLPVectorizer/X86/broadcast_long.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvectors-parent-phi-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvectors-with-same-parents.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp-as-alternate-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-member-in-non-commutable-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
M llvm/test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
M llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll
M llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-child-node-used-outside.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-non-inst-in-stores.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-operands-reordering.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-scheduled-non-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-used-non-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-reduced-erased.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-used-outside-with-immediate-op.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-with-used-outside-bb.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyables-with-parent-scalars-in-phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
M llvm/test/Transforms/SLPVectorizer/X86/cse.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-node-with-copyable-operands.ll
M llvm/test/Transforms/SLPVectorizer/X86/diamond.ll
M llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast_extra_shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
M llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
M llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-doesnotneedschedule-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/expanded-operand-already-scheduled.ll
M llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
M llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-reduced-value-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/external_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-subvector-long-input.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-used-in-many-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-with-undef-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-non-schedulable-overlap.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/hoist.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/X86/identity-match-splat-less-defined.ll
M llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll
M llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertelement-with-copyable-args.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
M llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
M llvm/test/Transforms/SLPVectorizer/X86/inversed-icmp-to-gather.ll
M llvm/test/Transforms/SLPVectorizer/X86/landing-pad-for-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll
M llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
M llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
M llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
M llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/many-uses-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-gather-part-of-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
M llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll
M llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbw-bitcast-to-fp.ll
M llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-bswap.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-reduced-select-of-bits.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-extern-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll
M llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
M llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/parent-node-schedulable-with-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/parent-phi-node-reordered.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-node-with-cycle.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi3.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi_landingpad.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
M llvm/test/Transforms/SLPVectorizer/X86/phis-different-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr27163.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
M llvm/test/Transforms/SLPVectorizer/X86/propagate-mmra.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-bswap-with-larger-reduced-type.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-copyable-reused-scalars.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark-partial-loads-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
M llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/resched.ll
M llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
M llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-extract-scalar-lanes.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-extracts.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-reductions-with-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-fma-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-non-power-2-to-power-2-large-vect.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-scalar-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
M llvm/test/Transforms/SLPVectorizer/X86/same-operands-but-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
M llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/sibling-loops-mismatched-tripcount.ll
M llvm/test/Transforms/SLPVectorizer/X86/simplebb.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
M llvm/test/Transforms/SLPVectorizer/X86/small-graph-diff-block-instructions.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-last-inst-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-num-operands.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-parent-operands-in-spill.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reduce-root.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-throttled.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-vector-operand-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-gathered-def-after-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll
M llvm/test/Transforms/SLPVectorizer/X86/store-load-forward-conflict.ll
M llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/struct-return-extract-dominance.ll
M llvm/test/Transforms/SLPVectorizer/X86/struct-return-ordering-stress.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
M llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
M llvm/test/Transforms/SLPVectorizer/X86/trunc-store-value-ty-not-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/X86/trunced-buildvector-scalar-extended.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp-with-signed-value-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
M llvm/test/Transforms/SLPVectorizer/X86/user-node-with-same-last-instr.ll
M llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-gather-some-loads.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll
M llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/whole-registers-compare.ll
M llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
M llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
M llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll
M llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
M llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
M llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll
M llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
M llvm/test/Transforms/SLPVectorizer/ext-after-phi-node.ll
M llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
M llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
M llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
M llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
M llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll
M llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
M llvm/test/Transforms/SLPVectorizer/gathered-consecutive-loads-different-types.ll
M llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
M llvm/test/Transforms/SLPVectorizer/insert-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll
M llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
M llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
M llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
M llvm/test/Transforms/SLPVectorizer/last-buildvector-node.ll
M llvm/test/Transforms/SLPVectorizer/materialize-vector-of-consts.ll
M llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
M llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
M llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
M llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll
M llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
M llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
M llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
M llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
M llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
M llvm/test/Transforms/SLPVectorizer/reschedule.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/return.ll
M llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
M llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
M llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
M llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
M llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
M llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
M llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
M llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
M llvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll
M llvm/test/Transforms/SLPVectorizer/splat-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
M llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
M llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP] Use constant 64-bit indices for Extract/InsertElement (#208957)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: 76f0d4693463ec2c09b4e14eca8f96020bb710e6
https://github.com/llvm/llvm-project/commit/76f0d4693463ec2c09b4e14eca8f96020bb710e6
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/test/ELF/aarch64-reloc-pauth.s
M lld/test/ELF/pack-dyn-relocs-relr-loop.s
Log Message:
-----------
[ELF,test] Improve .relr.auth.dyn -> .rela.dyn movement coverage (#208991)
Test two behaviors of #195649 that were unasserted:
- .dynamic shrinks when all .relr.auth.dyn entries are moved to a
non-empty .rela.dyn. Check the section header size: readelf -d stops
at the first DT_NULL and cannot show stale padding. This subsumes
empty-relr.s (a size-neutral tag swap, which passed even without the
fix), so remove it.
- An empty .rela.dyn is removed when .relr.auth.dyn is unused. Assert
this in pack-dyn-relocs-relr-loop.s.
Commit: 7215a1a19c13c79e66a9e8661aa7798cb3261b94
https://github.com/llvm/llvm-project/commit/7215a1a19c13c79e66a9e8661aa7798cb3261b94
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll
Log Message:
-----------
[LoadStoreVectorizer] Use constant 64-bit indices for Extract/InsertElement (#208941)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: 2aab89554cbf800bf50928fe7b1b3de2cbd41b26
https://github.com/llvm/llvm-project/commit/2aab89554cbf800bf50928fe7b1b3de2cbd41b26
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
M clang/test/CodeGen/AArch64/neon-2velem.c
M clang/test/CodeGen/AArch64/neon-extract.c
M clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
M clang/test/CodeGen/AArch64/neon-ldst-one.c
M clang/test/CodeGen/AArch64/neon-misc.c
M clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
M clang/test/CodeGen/AArch64/neon-vcmla.c
M clang/test/CodeGen/AArch64/neon/fused-multiply.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
M clang/test/CodeGen/arm-neon-vst.c
M clang/test/CodeGen/arm64_vdupq_n_f64.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/cx-complex-range-real.c
M clang/test/CodeGen/cx-complex-range.c
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
M llvm/test/Transforms/SROA/basictest.ll
M llvm/test/Transforms/SROA/prefer-integer-partition.ll
M llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
M llvm/test/Transforms/SROA/struct-to-vector-fp-store-only-tail.ll
M llvm/test/Transforms/SROA/vector-conversion.ll
M llvm/test/Transforms/SROA/vector-promotion-rmw-cannot-tree-merge.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
Log Message:
-----------
[SROA] Use constant 64-bit indices for Extract/InsertElement (#208918)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: e62c0cb076fbcb70752530571726944648a48829
https://github.com/llvm/llvm-project/commit/e62c0cb076fbcb70752530571726944648a48829
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/test/PCH/cxx20-template-args.cpp
Log Message:
-----------
[clang][bytecode] Fix comparing `TemplateParamObjectDecl`s (#208734)
1) When creating the global variables for them, always use the first
decl
2) When converting null pointers to `APValue`, don't cast the nullptr
base to `Expr` or `ValueDecl`. Use `LValueBase()` instead, so the
internal `PointerUnion` has an all-zeros value as `getOpaqueValue()`. If
we don't do this, we run into problems with merging of
`TemplateParamObjectDecls` because they don't compare equal via
`::Profile()`.
Commit: 25a5b7869cd13698f7556af6b4084cca835ae988
https://github.com/llvm/llvm-project/commit/25a5b7869cd13698f7556af6b4084cca835ae988
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
Log Message:
-----------
[PatternMatch] Add capturing m_Phi matcher (NFC) (#208949)
Add a new capturing m_Phi matcher and use it in some patterns instead of
manually casting/checking if operand is a phi.
PR: https://github.com/llvm/llvm-project/pull/208949
Commit: af812fc18a8ab488bf8b70f9b8ae19bbdd1aea48
https://github.com/llvm/llvm-project/commit/af812fc18a8ab488bf8b70f9b8ae19bbdd1aea48
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvp-widening-convert.ll
Log Message:
-----------
[Clang][RISCV][P-ext] Support packed widening convert intrinsics (#208394)
This patch implements all packed widening convert intrinsics using
general vector operations. Low widening conversions use
`__builtin_convertvector`, while high-half conversions use general
shuffles.
The generated code for high-half conversions is correct but not yet
optimal.
Commit: 4c7948d06c93e8d233cd4733fd4107f3b68bc7bc
https://github.com/llvm/llvm-project/commit/4c7948d06c93e8d233cd4733fd4107f3b68bc7bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
Revert "[VPlan] Re-use VPSlotTracker when printing recipes for costs (NFC)." (#209003)
Reverts llvm/llvm-project#203386.
This causes a large compile-time regression.
Commit: a34cb573eae65f48f0e51147289e042a86b55d16
https://github.com/llvm/llvm-project/commit/a34cb573eae65f48f0e51147289e042a86b55d16
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
A clang/test/Analysis/string-search-modeling.c
Log Message:
-----------
[analyzer] Model strchr/strrchr/memchr/strstr/strpbrk/strchrnul (#207267)
CStringChecker did not model these buffer-search functions, so the
engine bound each call to a fresh conjured symbol unrelated to the source.
As a consequence, we could not track the origin of the returned pointer,
thus the fact that it shares provenance of the source pointer.
Fixes #203260
Assisted-by: Claude Opus 4.8
Commit: 97bceede1059b67d3491011f415856f32de21c9c
https://github.com/llvm/llvm-project/commit/97bceede1059b67d3491011f415856f32de21c9c
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-srl-bitcast-bv.ll
M llvm/test/CodeGen/RISCV/rvp-zip.ll
Log Message:
-----------
[RISCV][P-ext] Improve the codegen for unzip-like shuffle and buildvector (#208763)
This patch selects `pncvt*`/`unzip*` for unzip-like patterns.
On RV32, we select packed narrow shift for i8x4 and i16x2 BUILD_VECTOR
that are equivalent to deinterleave shuffle.
On RV64, we select packed unzip for i8x4 and i16x2 deinterleave shuffle.
Apart from the packed unzip intrinsics, this patch also adds support for
the codegen of two-source unzip.
Commit: a06b1c9f4bd49af7e2c68cacf5922136906bb335
https://github.com/llvm/llvm-project/commit/a06b1c9f4bd49af7e2c68cacf5922136906bb335
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/Logging_printf.cpp
M orc-rt/test/CMakeLists.txt
M orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/logging/lit.local.cfg
A orc-rt/test/regression/logging/printf-backend/bad-level.test
A orc-rt/test/regression/logging/printf-backend/debug-compiled-out.test
A orc-rt/test/regression/logging/printf-backend/debug-level.test
A orc-rt/test/regression/logging/printf-backend/format.test
A orc-rt/test/regression/logging/printf-backend/level-off.test
A orc-rt/test/regression/logging/printf-backend/lit.local.cfg
A orc-rt/test/regression/logging/printf-backend/output-redirect.test
A orc-rt/test/regression/logging/printf-backend/runtime-level.test
M orc-rt/test/tools/CMakeLists.txt
A orc-rt/test/tools/orc-rt-log-check.cpp
Log Message:
-----------
[orc-rt] Add printf logging backend (#209006)
Implement the printf backend, selected at configure-time with
ORC_RT_LOG_BACKEND=printf. Messages are written to stderr, or to the
file named by the ORC_RT_LOG_OUTPUT environment variable.
The ORC_RT_LOG environment variable sets the runtime level floor (error,
warning, info, debug, or off) -- only messages at or above it are shown.
When unset it defaults to warning, so warnings and errors are shown and
info and debug are opt-in. The runtime floor cannot go below the
compile-time ORC_RT_LOG_LEVEL floor (the lowest level built in).
Also add regression tests, driven by a new orc-rt-log-check tool that
reports the compiled-in backend and levels (which lit exposes as
features) and emits a message at each level.
Commit: 3187f2659848d0cfadc9caa601215afb8bd9b242
https://github.com/llvm/llvm-project/commit/3187f2659848d0cfadc9caa601215afb8bd9b242
Author: Zinovy Nis <zinovy.nis at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
Log Message:
-----------
[clang-tidy] Modernize-use-string-view: fix todo for ternary (#209008)
Add a support for any-depth ternary expressions
Commit: 3f2d8eb20a8d86d9aeea75a00e21a4ecff0a5234
https://github.com/llvm/llvm-project/commit/3f2d8eb20a8d86d9aeea75a00e21a4ecff0a5234
Author: Lukas <43409484+hertelukas at users.noreply.github.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
A llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
A llvm/test/Transforms/UnifyLoopExits/multiedge.ll
Log Message:
-----------
[FixIrreducible][UnifyLoopExits] Fix callbr multiedge splitting (#207598)
This fixes a bug where splitting `callbr` multiedges corrupts the
successor's PHI nodes.
Originally, the first split edge would replace all incoming edges from
the `callbr` block with the newly introduced target block by using
`replacePhiUsesWith`. Later edges would create new target blocks and
would try to update their edge's PHI as well, but would not find it,
leading to a corrupted PHI node.
To fix this, it is theoretically only necessary to ensure that exactly
one PHI argument is replaced per split edge. However, as all the PHI
nodes must have the same argument for every edge from one predecessor, a
single target block suffices, through which all traffic can be routed,
which will be especially useful for switches, where multiedges are
common.
[Trunk crashing](https://godbolt.org/z/4MM5eMrW5)
Found while working on PR #206567, cc @ro-i.
Commit: b82a9a57e72c29a5e8fc81109a62eb827fa5d8f0
https://github.com/llvm/llvm-project/commit/b82a9a57e72c29a5e8fc81109a62eb827fa5d8f0
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/include/llvm/ADT/ImmutableSet.h
Log Message:
-----------
[ADT] Fuse the two post-mutation tree walks in ImutAVLFactory (#208907)
Commit: f99f2a582e947af3f20580fa2674ca0c6bde1b2c
https://github.com/llvm/llvm-project/commit/f99f2a582e947af3f20580fa2674ca0c6bde1b2c
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
M clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
M clang/test/Analysis/debug-lifetime-bound.cpp
M clang/test/Analysis/lifetime-bound.cpp
Log Message:
-----------
[analyzer] Implement LifetimeModeling checker and refactor UseAfterLifetimeEnd (#205951)
Commit: 7c2f4db828e5b9fd391c7f69bdd7dfe866b41bc0
https://github.com/llvm/llvm-project/commit/7c2f4db828e5b9fd391c7f69bdd7dfe866b41bc0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/Environment.cpp
A orc-rt/lib/executor/Environment.h
M orc-rt/lib/executor/Logging_printf.cpp
Log Message:
-----------
[orc-rt] Add internal secureGetenv utility and use it in the printf b… (#209014)
…ackend
orc_rt::secureGetenv is like getenv, but returns null when the process
is running with elevated privileges (e.g. a set-user-ID or set-group-ID
program), so that a variable in an attacker-controlled environment
cannot influence a privileged host. On libcs where privilege can't be
checked (anything other than glibc or the BSDs/macOS), it fails secure
and returns null, so those environment variables are ignored until a
branch for the platform is added.
Switch the printf logging backend to read ORC_RT_LOG and
ORC_RT_LOG_OUTPUT through secureGetenv, so a redirected log file or
level can't be forced via the environment in a privileged process.
Note that running the ORC runtime in a process with elevated privileges
is extremely risky (since the JIT'd code will typically inherit these
elevated privileges), and expected to be rare. Exercise extreme caution
with such setups.
Commit: a259ffb45c84f930d3ad810dd4ddde50c2667766
https://github.com/llvm/llvm-project/commit/a259ffb45c84f930d3ad810dd4ddde50c2667766
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/minmax-main-opcode-copyables-cost.ll
A llvm/test/Transforms/SLPVectorizer/X86/minmax-main-opcode-copyables.ll
Log Message:
-----------
[SLP][NFC]Add tests for copyables in minmax int intrinsics, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209021
Commit: 7206149c21b420a3aa5a0c9a78f1a1ad6ff8ed89
https://github.com/llvm/llvm-project/commit/7206149c21b420a3aa5a0c9a78f1a1ad6ff8ed89
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/unittests/Lex/PPMemoryAllocationsTest.cpp
Log Message:
-----------
[NFC][clang] Adjust PPMemoryAllocationsTest threshold for ASan (#209024)
PPMemoryAllocationsTest.PPMacroDefinesAllocations measures the memory
footprint of the preprocessor allocator and asserts a strict threshold
of 130.0 bytes per define.
When built with ASan, the allocator adds redzones to allocations,
which increases the total memory reported by `getTotalMemory()` and
causes the test to fail (reporting ~136.8 bytes per define).
Adjust the threshold to 145.0 bytes per define when built with ASan
(detected via `LLVM_ADDRESS_SANITIZER_BUILD`) to account for this
overhead while maintaining the strict limit for standard builds.
Assisted-by: Gemini
Commit: 97e24c8d1cfd7259733ef4b3476f4429402415fb
https://github.com/llvm/llvm-project/commit/97e24c8d1cfd7259733ef4b3476f4429402415fb
Author: darkbuck <michael.hliao at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
M clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
M clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
Log Message:
-----------
[CIR] Fix lit tests after is.fpclass pretty printing. NFC (#209026)
Commit: 715cf355b1324117a4456cd79bd05df39f65643c
https://github.com/llvm/llvm-project/commit/715cf355b1324117a4456cd79bd05df39f65643c
Author: savchart <metaartem at protonmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/include/macro.h
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/subdir/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-macro-argument.cpp
Log Message:
-----------
[clang-tidy] Fix identifier-naming style lookup in macro arguments (#206809)
Problem statement: the var lambda parameter was written inside a macro
argument. The declaration location was treated as a macro location, and
the filename lookup returned an empty filename for that location.
Fix: use a file location for the style lookup. Alternative options
considered were spelling location and expansion location.
Fixes #154957
Assisted-by: GPT
---------
Co-authored-by: Zeyi Xu <mitchell.xu2 at gmail.com>
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: 4e15b551e06b188f8280c752b29e13ac53ddb70a
https://github.com/llvm/llvm-project/commit/4e15b551e06b188f8280c752b29e13ac53ddb70a
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/include/lld/Common/BPSectionOrdererBase.inc
M lld/test/ELF/bp-section-orderer.s
M lld/test/MachO/bp-section-orderer-errs.s
Log Message:
-----------
[lld] Report missing --irpgo-profile file instead of asserting (#209028)
When --irpgo-profile names a missing file, takeError() asserts
```
ld.lld: error: No such file or directory
ld.lld: Error.h:686: ... Assertion `!HasError && "Cannot get value when an error exists!"' failed.
```
Check the Expected before use. Fixes #203761
Co-authored-by: Peter Chen J. <peter941221 at gmail.com>
Co-authored-by: Peter Chen J. <peter941221 at gmail.com>
Commit: 5790cc0f6c7f1570f8cca222c19801a6c7c2f076
https://github.com/llvm/llvm-project/commit/5790cc0f6c7f1570f8cca222c19801a6c7c2f076
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/lib/IR/Instructions.cpp
Log Message:
-----------
[IR] Use constant 64-bit indices for Extract/InsertElement (#208996)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement
Commit: ede6a16b1bc4a870ff6180caeb87b727699cd9c1
https://github.com/llvm/llvm-project/commit/ede6a16b1bc4a870ff6180caeb87b727699cd9c1
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
Log Message:
-----------
[PowerPC] Use constant 64-bit indices for Extract/InsertElement (#209015)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: 66e9ac6aeab326e5d4f6e0c1cbdbc31bda5dec0e
https://github.com/llvm/llvm-project/commit/66e9ac6aeab326e5d4f6e0c1cbdbc31bda5dec0e
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Use constant 64-bit indices for InsertElement (#209017)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in InsertElement.
Commit: 83d95d89c520656306130b461252cd0ed9b4f542
https://github.com/llvm/llvm-project/commit/83d95d89c520656306130b461252cd0ed9b4f542
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Log Message:
-----------
[SimplifyLibCalls] Use constant 64-bit indices for ExtractElement (#209020)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement.
Commit: 3a27d292c353328a9a03422319ff1c0b9264648b
https://github.com/llvm/llvm-project/commit/3a27d292c353328a9a03422319ff1c0b9264648b
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Move markUsedLocalSymbols from Writer to markLive. NFC (#209035)
markUsedLocalSymbols (https://reviews.llvm.org/D77807) sets the USED
flag on local symbols referenced by relocations so that -r/--emit-relocs
with --discard-{locals,all} preserves them in the symbol table.
Move the scan into markLive's !gcSections branch to be closer to
MarkLive::resolveReloc. The scan now iterates sections via relsOrRelas,
handling CREL uniformly, and runs in parallel.
This is a step toward fixing #160789
Commit: 937ac000a69012546d851638b1410cfe9f07980f
https://github.com/llvm/llvm-project/commit/937ac000a69012546d851638b1410cfe9f07980f
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Debuginfod/BuildIDFetcher.cpp
M llvm/lib/HTTP/HTTPClient.cpp
A llvm/test/tools/llvm-debuginfod-find/Inputs/delay_req.py
M llvm/test/tools/llvm-debuginfod-find/headers-winhttp.test
A llvm/test/tools/llvm-debuginfod-find/timeout.test
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
Log Message:
-----------
[llvm][HTTP] Apply WinHTTP timeout setting after WinHttpOpen (#188969)
`setTimeout()` required the session handle, but it was only created
inside `HTTPClient::perform()`. This patch stores the incoming value and
applies it after the session handle is created with `WinHttpOpen()`.
---------
Co-authored-by: Nerixyz <nerixdev at outlook.de>
Commit: fafd0de9e4a84921cce55ea8c6da05b515006fa2
https://github.com/llvm/llvm-project/commit/fafd0de9e4a84921cce55ea8c6da05b515006fa2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/copyable-addsub-reorder.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect add/sub operands reorder, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209039
Commit: 2fdc877f7209a32d9632aafe75d2d61199a7089f
https://github.com/llvm/llvm-project/commit/2fdc877f7209a32d9632aafe75d2d61199a7089f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/copyable-addsub-reorder.ll
Log Message:
-----------
[SLP] Fix miscompile from unsafe operand-order normalization
IsCommutative(MainOp) is also true for a Sub/FSub feeding only
fabs/icmp-eq-0, but that doesn't make every lane swappable: a
converted Add/FAdd lane's operand order is fixed to preserve its
value, and swapping it into a native Sub/FSub's layout negates it.
Re-check each lane before swapping instead of trusting MainOp's.
Fixes #208944
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209041
Commit: 5485d624eb95bb7a753c6088e452d32d0bd0c03d
https://github.com/llvm/llvm-project/commit/5485d624eb95bb7a753c6088e452d32d0bd0c03d
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/test/ELF/emit-relocs-discard-locals.s
Log Message:
-----------
[ELF] --discard-{locals,all}: mark local symbols referenced by retained non-SHF_ALLOC sections (#209042)
With --gc-sections, mark() does not scan relocations of retained
non-SHF_ALLOC sections, so local symbols referenced only by such
sections (e.g. .L symbols in .debug_str_offsets referenced by
.debug_info) do not get the USED flag.
-r/--emit-relocs with --discard-{locals,all} would discard the symbols
and rewrite relocations to reference the null symbol, corrupting DWARF
in the output. This is common on RISC-V, where
RISCVELFObjectWriter::needsRelocateWithSymbol returns true, but is also
possible on other targets with --reloc-section-sym=none.
Call markUsedLocalSymbols from the retention loop (introduced by
#209035)
to set the flag.
Fix #160789
Commit: 36876394a96b053a03aecacec566eadc292d7053
https://github.com/llvm/llvm-project/commit/36876394a96b053a03aecacec566eadc292d7053
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-debuginfod-find/Inputs/delay_req.py
Log Message:
-----------
[llvm][HTTP] Increase request handler sleep (#209038)
Fixup for
https://github.com/llvm/llvm-project/pull/188969#issuecomment-4952185708.
The issue is likely the same as I described in
https://github.com/llvm/llvm-project/pull/192061#issuecomment-4926882131
where WinHTTP doesn't time out immediately but adds some delay. The fix
here is to increase the sleep in the mock server.
Commit: 65735abd4d0af888840929be6356628a05eaa179
https://github.com/llvm/llvm-project/commit/65735abd4d0af888840929be6356628a05eaa179
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/add-sub-nuw.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect nuw propagation in add/sub vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209045
Commit: 927878dab67545e7448a82921446e339b6b55f79
https://github.com/llvm/llvm-project/commit/927878dab67545e7448a82921446e339b6b55f79
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/add-sub-nuw.ll
Log Message:
-----------
[SLP] Drop nuw when add/sub interchange negates a nonzero constant
sub nuw X, C requires X u>= C, but add nuw X, -C requires X u< C, so
nuw must always be dropped on interchange.
Fixes #209023
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209047
Commit: b8d37cbc139a5adcd56611c21850e02600e560f2
https://github.com/llvm/llvm-project/commit/b8d37cbc139a5adcd56611c21850e02600e560f2
Author: David Green <david.green at arm.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/test/CodeGen/AArch64/verify-imm.mir
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
Log Message:
-----------
[AArch64] Add an OPERAND_IMM_UINT8 operand type. (#209050)
This helps verify that certain operands are in the correct range, in
this case
0-255.
Commit: 5566928ef0b0788da6582ea3bcc8ab9ae416e80f
https://github.com/llvm/llvm-project/commit/5566928ef0b0788da6582ea3bcc8ab9ae416e80f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
A llvm/test/Analysis/LoopAccessAnalysis/wide-pointer-index-distance.ll
Log Message:
-----------
[LAA] Bail out of dependence analysis when distance exceeds 64 bits. (#209052)
isDependent extracts the dependence distance into 64 bit integers.
Bail out conservatively when the constant distance or the signed minimum
distance needs more than 64 bits.
Commit: 349542f7e122b8fda1d60f0b37c8f92ad65635d6
https://github.com/llvm/llvm-project/commit/349542f7e122b8fda1d60f0b37c8f92ad65635d6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[VPlan] Add strided access test with disjoint or. (NFC) (#209051)
Currently this is missed by VPlan SCEV due to disjoint OR not being
handled.
Commit: 62377815c4cc03130608158a8d51cc37e4549288
https://github.com/llvm/llvm-project/commit/62377815c4cc03130608158a8d51cc37e4549288
Author: David Green <david.green at arm.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/verify-imm.mir
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
Log Message:
-----------
[AArch64] Add an OPERAND_IMM_UINT5 operand type. (#209057)
This helps verify that certain operands are in the correct range, in
this case
0-31.
Commit: fd6524963bf1ec6b4d2c688337af8f9f41562575
https://github.com/llvm/llvm-project/commit/fd6524963bf1ec6b4d2c688337af8f9f41562575
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
Log Message:
-----------
[VPlan] Handle AtomicRMW/AtomicCmpXchg/Fence in outer loop creation. (#209031)
Teach VPInstruction::getNumOperandsForOpcode about AtomicRMW,
AtomicCmpXchg and Fence, so VPlan construction over an outer loop that
still contains these operations does not crash before later legality
rejects the loop.
Fixes crashes in the added tests.
Commit: bb4aea6303e7470be3ccd37db9398fc9b8f03f50
https://github.com/llvm/llvm-project/commit/bb4aea6303e7470be3ccd37db9398fc9b8f03f50
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/ptrtoint-special-pointers.ll
M llvm/test/Transforms/GVN/ptrtoaddr.ll
A llvm/test/Transforms/IndVarSimplify/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
Log Message:
-----------
[SCEV,GVN] Add additional ptrtoaddr tests (NFC) (#209049)
Extend test coverage with files with mixied ptrtoaddr/ptrtoint, as well
as wide pointers.
Extra test coverage for
https://github.com/llvm/llvm-project/pull/180244.
Commit: d036d309eebee3ac0b8077f0cc6e3a318bc0e6ab
https://github.com/llvm/llvm-project/commit/d036d309eebee3ac0b8077f0cc6e3a318bc0e6ab
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/test/MachO/bp-section-orderer-errs.s
Log Message:
-----------
[test] Add REQUIRES: aarch64 (#209058)
Commit: 0188651ae4a0d38f014fc315f182aa813a73dfbe
https://github.com/llvm/llvm-project/commit/0188651ae4a0d38f014fc315f182aa813a73dfbe
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-signed-icmp-const.ll
Log Message:
-----------
[SLP][NFC]Add a test with the incorrect const trunc in signed compare, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209059
Commit: fe85b5be435add42d83d85e09059ae2e6e0896e4
https://github.com/llvm/llvm-project/commit/fe85b5be435add42d83d85e09059ae2e6e0896e4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-signed-icmp-const.ll
Log Message:
-----------
[SLP] Fix miscompile from truncating signed icmp constant
getActiveBits() ignores sign, so a positive constant needing the
narrower type's top bit was truncated to a negative value. Use
getSignificantBits() for signed comparisons.
Fixes #209010
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209061
Commit: 9083925dadb45d99836b75ac0354265d6cbd46ab
https://github.com/llvm/llvm-project/commit/9083925dadb45d99836b75ac0354265d6cbd46ab
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/retain-und.s
Log Message:
-----------
[ELF,test] Modernize --retain-symbols-file tests (#209062)
Switch to llvm-readelf, compact FileCheck directives, and
split-file-style naming. Prepares for a --retain-symbols-file behavior
change.
Commit: b6e77d6af14b6b4d0d98248c1579b1be0194187a
https://github.com/llvm/llvm-project/commit/b6e77d6af14b6b4d0d98248c1579b1be0194187a
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
Log Message:
-----------
[Clang][Test] Fix -Wctad-maybe-unsupported in OperatorNewDeletePointersExtractorTest.cpp (#209012)
Fix warning: `'std::set' may not intend to support class template
argument deduction [-Wctad-maybe-unsupported]`, which is error under
-Werror.
std::set{*PtrId} does implicitly deduce to std::set<EntityId>, but it
is not explicit or user-defined CATD guide. Opt-in warning
-Wctad-maybe-unsupported flags it as maybe unsafe and unintended. The
warning is enabled at
https://github.com/llvm/llvm-project/blob/9083925dadb4/llvm/cmake/modules/HandleLLVMOptions.cmake#L977
Relates to #206600.
Commit: c847ddf8f18d3edde84fa99bf9d15511a7978cdd
https://github.com/llvm/llvm-project/commit/c847ddf8f18d3edde84fa99bf9d15511a7978cdd
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/Writer.cpp
M lld/unittests/AsLibELF/CMakeLists.txt
A lld/unittests/AsLibELF/OutputStream.cpp
Log Message:
-----------
[ELF] Write the output to lld::outs() when -o is - (#209064)
When the output file is "-", write the image to lld::outs() (the
stdoutOS
argument of lld::elf::link()) instead of committing the
FileOutputBuffer,
which writes to the process's stdout. This lets lld used as a library
capture
the output in a raw_ostream without an open syscall.
This reimplements the stale #72061 and adds a unittest.
Commit: 7d24dfa5f29e1794e452aadaa27f994f15568763
https://github.com/llvm/llvm-project/commit/7d24dfa5f29e1794e452aadaa27f994f15568763
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/docs/ReleaseNotes.rst
Log Message:
-----------
ReleaseNotes: add lld/ELF notes (#209066)
Summarize `git log origin/release/22.x..main` entries, excluding
cherry-picked notes `git rev-list main..origin/release/22.x -- lld/ELF`,
following the style of my previous release notes.
Commit: c7812f661d843e666c6ab3ab9c4a33b83e930c29
https://github.com/llvm/llvm-project/commit/c7812f661d843e666c6ab3ab9c4a33b83e930c29
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/copyable-repeated-operand-partial-commutativity.ll
Log Message:
-----------
[SLP] Fix crash from repeated operand with mixed commutativity
A value used as both a commutable and non-commutable operand of the
same call got double-counted in dependency tracking, adding a
dependency scheduling never releases and tripping an assertion.
Fixes #209005
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209067
Commit: 692d89dc02deb30d14bcaa2dbb2ed91ea8f88acd
https://github.com/llvm/llvm-project/commit/692d89dc02deb30d14bcaa2dbb2ed91ea8f88acd
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/source/Host/freebsd/Host.cpp
Log Message:
-----------
[LLDB][FreeBSD] Fill pgid and sid in ProcessInfo (#209009)
These two fields are required by HostTest.cpp. Although I don't see any
usecase, we add these two fields to prevent failure.
Commit: 461f0b699c8dbcafaec0e4b2d171d42ee05f6999
https://github.com/llvm/llvm-project/commit/461f0b699c8dbcafaec0e4b2d171d42ee05f6999
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/JSONTransport.h
Log Message:
-----------
[LLDB] Fix use-after-free destroying a Binder from its OnClosed handler (#209019)
transport::Binder::OnClosed() holds m_mutex (a recursive_mutex) while
invoking m_disconnect_handler. In the MCP server, that handler removes
the disconnected client, which owns the transport and therefore the
Binder itself. As a result, the Binder -- and its m_mutex -- are
destroyed while the scoped_lock in OnClosed still holds the lock.
This is a use-after-free everywhere, as the lock guard later unlocks
freed memory.
Move the disconnect handler out of the critical section and release the
lock before invoking it, so the Binder can be safely destroyed without
holding or destroying a locked mutex.
Commit: 171ba71128eec9f1859bb995c597dcff296ee730
https://github.com/llvm/llvm-project/commit/171ba71128eec9f1859bb995c597dcff296ee730
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/test/X86/dwarf4-cross-cu-ranges.test
M bolt/test/X86/dwarf5-debug-names-cross-cu.s
Log Message:
-----------
[BOLT] fix DIE traversal incorrect loop termination condition. (#208450)
The DIE traversal loop in partitionCUs() used an incorrect termination
condition, causing it to read past the end of the CU. Fix the loop to
stop at NextCUOffset so traversal no longer runs beyond the unit's
boundary.
Fixed [#208440](https://github.com/llvm/llvm-project/issues/208440).
Commit: e6673bd0377104b681ad9f456f3b7742c8f3a9a9
https://github.com/llvm/llvm-project/commit/e6673bd0377104b681ad9f456f3b7742c8f3a9a9
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][Modularization][NFC] Extract type and constant helpers into SLPUtils (1/3) (#206881)
As we discussed on RFC:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
This patch introduces the SLPVectorizer/ subdirectory and adds
SLPUtils.{h,cpp} under namespace llvm::slpvectorizer, then moves the
type and constant query helpers into it:
- isConstant
- isVectorLikeInstWithConstOps
- isSplat
- allConstant
- allSameBlock
- allSameType
- allSameOpcode
- getNumElements
- getPartNumElems
- getNumElems
- getInsertExtractIndex
- getExtractIndex
Commit: d91a1e88891d9737535198137c73632f57cc629a
https://github.com/llvm/llvm-project/commit/d91a1e88891d9737535198137c73632f57cc629a
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
[libc++] Switch use llvm-premerge-libcxx-runner (#208928)
Signed-off-by: yronglin <yronglin777 at gmail.com>
Co-authored-by: Aiden Grossman <aidengrossman at google.com>
Commit: d8df9b5e925c580f076779e5cbfe2bffc451c3b6
https://github.com/llvm/llvm-project/commit/d8df9b5e925c580f076779e5cbfe2bffc451c3b6
Author: ejose02 <ejose at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-call.cpp
A flang/test/Semantics/call48.f90
Log Message:
-----------
[Flang] Fix for the spurious error for VOLATILE actual argument in implicit interface CALL (#192605)
Fixes #191343
Replaced the error with warning. Now it permits calling an external
procedure with implicit interface and passing a volatile argument. There
will be a warning that the procedure should have an explicit interface.
In addition to fixing the VOLATILE error, I updated the semantic check
for the ASYNCHRONOUS attribute. Both attributes were incorrectly
throwing a hard error when used as actual arguments in an implicit
interface call. According to the Fortran 2018 standard, an explicit
interface is only mandatory when the dummy argument has the VOLATILE or
ASYNCHRONOUS attribute. Since the standard doesn't restrict actual
arguments in this scenario, I downgraded both to emit a
-Wimplicit-interface-actual warning instead.
Commit: b1c56fb53a9c76d6b045ede49083b647ae049ffe
https://github.com/llvm/llvm-project/commit/b1c56fb53a9c76d6b045ede49083b647ae049ffe
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/Logging_oslog.cpp
M orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/logging/os_log/delivery.test
A orc-rt/test/regression/logging/os_log/lit.local.cfg
A orc-rt/test/regression/logging/os_log/no-printf-output.test
M orc-rt/test/tools/orc-rt-log-check.cpp
Log Message:
-----------
[orc-rt] Add os_log logging backend (Darwin only) (#209081)
Implement the os_log backend, selected with ORC_RT_LOG_BACKEND=os_log.
With this backend selected, the ORC_RT_LOG macros expand at the call
site to os_log_with_type. Each ORC runtime log level maps to an
os_log_type_t (error -> ERROR, warning -> DEFAULT, info -> INFO, debug
-> DEBUG). The compile-time ORC_RT_LOG_LEVEL floor still applies, but
runtime filtering is left to the system (e.g. `log config`), so the
printf backend's ORC_RT_LOG and ORC_RT_LOG_OUTPUT have no effect.
Records go to the "org.llvm.orc-rt" subsystem with the category as the
os_log category. (Per-category handles are created on first use and
cached).
Add regression tests under test/regression/logging/os_log:
no-printf-output.test checks that the backend produces no console
output, and an opt-in delivery test (llvm-lit --param
run-os-log-tests=1) scrapes `log show` to confirm records reach the
expected subsystem and category.
Commit: 9b9f44d1c55ca4f3e8d6d5d9350ef872e000df0a
https://github.com/llvm/llvm-project/commit/9b9f44d1c55ca4f3e8d6d5d9350ef872e000df0a
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/include/llvm/ADT/Eytzinger.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/EytzingerTest.cpp
Log Message:
-----------
[ADT] Introduce EytzingerTableSpan (#208885)
This patch introduces EytzingerTableSpan, a non-owning view of a buffer
formatted as a complete binary search tree in Eytzinger (breadth-first)
order.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/7
Assisted-by: Antigravity
Commit: fd17f88189525a81488294912bff8b9f429585a2
https://github.com/llvm/llvm-project/commit/fd17f88189525a81488294912bff8b9f429585a2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV][P-ext] Replace RISCVISD::PPAIRE_DB with RISCVISD::PPAIRE. NFC (#208980)
This replaces RISCVISD::PPAIRE_DB with the RISCVISD::PPAIRE added by
#208763.
This adds two CONCAT_VECTORS and two EXTRACT_SUBVECTORs during lowering
instead of waiting until isel to form the GPR pairs.
Commit: 11112ed9b7eb7deb69b97178a0c4921e6222049c
https://github.com/llvm/llvm-project/commit/11112ed9b7eb7deb69b97178a0c4921e6222049c
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libc/src/__support/CPP/expected.h
M libc/test/src/__support/CPP/CMakeLists.txt
A libc/test/src/__support/CPP/expected_test.cpp
Log Message:
-----------
[libc] Make cpp::expected::operator bool explicit (#208681)
Without explicit, expected<T, E> implicitly converts to bool in all
sorts of unexpected contexts (e.g. `EXPECT_EQ(ErrorOr<int>(47), 1)`),
and also deviates from std::expected in C++23.
While in there, add basic unit tests for expected and unexpected (we
didn't have any tests for this utility yet), and update the file header.
Assisted by Gemini.
Commit: 26e34c6896626f0874a1eface84b8fb25111f4b0
https://github.com/llvm/llvm-project/commit/26e34c6896626f0874a1eface84b8fb25111f4b0
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/IR/Constants.cpp
M llvm/test/Transforms/TailCallElim/accum_recursion.ll
M llvm/test/Transforms/TailCallElim/tre-minmax-intrinsic.ll
Log Message:
-----------
[IR] Handle vector tys in ConstantExpr::getIntrinsicIdentity for smin/max. (#208367)
The code was using getIntegerBitWidth() when it should have been using
getScalarSizeInBits(). This resulted in an assert in debug builds, and
who-knows-what in opt builds.
Reproducer:
```
define <4 x i32> @f(<4 x i32> %a, i32 %b) {
%c = call <4 x i32> @f(<4 x i32> %a, i32 %b)
%m = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %c, <4 x i32> %a)
ret <4 x i32> %m
}
$ opt -passes=tailcallelim repro.ll
Casting.h:572: Assertion `isa<To>(Val) && "cast<Ty>() argument of
incompatible type!"' failed.
```
Bug found and fixed by Claude Mythos 5.
Commit: 3f80df8698145f0188f305b748e60e70bf942d3d
https://github.com/llvm/llvm-project/commit/3f80df8698145f0188f305b748e60e70bf942d3d
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M bolt/test/X86/match-blocks-with-pseudo-probes-inline.test
M bolt/test/X86/pseudoprobe-decoding-inline.test
M bolt/test/X86/pseudoprobe-decoding-noinline.test
A llvm/test/tools/llvm-profgen/AArch64/aarch64-disassemble-all-features.test
A llvm/test/tools/llvm-profgen/AArch64/lit.local.cfg
A llvm/test/tools/llvm-profgen/ARM/Inputs/etm-opencsd.yaml
A llvm/test/tools/llvm-profgen/ARM/etm-arch.test
A llvm/test/tools/llvm-profgen/ARM/etm-opencsd.test
A llvm/test/tools/llvm-profgen/ARM/lit.local.cfg
R llvm/test/tools/llvm-profgen/Inputs/artificial-branch.perfscript
R llvm/test/tools/llvm-profgen/Inputs/callback-external-addr.perfbin
R llvm/test/tools/llvm-profgen/Inputs/callback-external-addr.perfscript
R llvm/test/tools/llvm-profgen/Inputs/coff-profile.exe
R llvm/test/tools/llvm-profgen/Inputs/coff-profile.pdb
R llvm/test/tools/llvm-profgen/Inputs/coff-profile.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cold-profile-trimming.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/coroutine.perfbin
R llvm/test/tools/llvm-profgen/Inputs/coroutine.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cs-interrupt.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cs-invalid-ret-addr.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cs-preinline-cost.perfbin
R llvm/test/tools/llvm-profgen/Inputs/cs-preinline-cost.perfscript
R llvm/test/tools/llvm-profgen/Inputs/css-pgo-perf.script
R llvm/test/tools/llvm-profgen/Inputs/dap-perf-trace.txt
R llvm/test/tools/llvm-profgen/Inputs/dap-pie.bin
R llvm/test/tools/llvm-profgen/Inputs/dap.bin
R llvm/test/tools/llvm-profgen/Inputs/etm-opencsd.yaml
R llvm/test/tools/llvm-profgen/Inputs/external-address.perfscript
R llvm/test/tools/llvm-profgen/Inputs/filter-ambiguous-profile.prof
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator-probe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator-probe.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator.perfbin
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/func-split.perfbin
R llvm/test/tools/llvm-profgen/Inputs/func-split.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe2.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe2.perfscript
R llvm/test/tools/llvm-profgen/Inputs/invalid-range.perfscript
R llvm/test/tools/llvm-profgen/Inputs/lbr-perf-for-dap.script
R llvm/test/tools/llvm-profgen/Inputs/missing-dwarf.exe
R llvm/test/tools/llvm-profgen/Inputs/multi-load-segs.perfbin
R llvm/test/tools/llvm-profgen/Inputs/multi-load-segs.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.aggperfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.aggperfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-tailcall-probe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noinline-tailcall-probe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noprobe.aggperfscript
R llvm/test/tools/llvm-profgen/Inputs/noprobe.mmap.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/out-of-bounds.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/pie-dap-perf.txt
R llvm/test/tools/llvm-profgen/Inputs/pie-lbr-perf.script
R llvm/test/tools/llvm-profgen/Inputs/profile-density-cs.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/profile-density.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe-nommap.perfscript
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-single.exe
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-single.o.yaml
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-split.dwo.yaml
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-split.exe
R llvm/test/tools/llvm-profgen/Inputs/symbolize.ll
R llvm/test/tools/llvm-profgen/Inputs/symbolize.perfbin
R llvm/test/tools/llvm-profgen/Inputs/truncated-pseudoprobe.ll
R llvm/test/tools/llvm-profgen/Inputs/truncated-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/truncated-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-dwarf.perfbin
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-dwarf.perfscript
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-probe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-probe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/artificial-branch.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/callback-external-addr.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/callback-external-addr.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/coff-profile.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/coff-profile.pdb
A llvm/test/tools/llvm-profgen/X86/Inputs/coff-profile.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cold-profile-trimming.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/coroutine.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/coroutine.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-interrupt.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-invalid-ret-addr.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-preinline-cost.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-preinline-cost.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/css-pgo-perf.script
A llvm/test/tools/llvm-profgen/X86/Inputs/dap-perf-trace.txt
A llvm/test/tools/llvm-profgen/X86/Inputs/dap-pie.bin
A llvm/test/tools/llvm-profgen/X86/Inputs/dap.bin
A llvm/test/tools/llvm-profgen/X86/Inputs/external-address.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/filter-ambiguous-profile.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator-probe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator-probe.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/func-split.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/func-split.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe2.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe2.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/invalid-range.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/lbr-perf-for-dap.script
A llvm/test/tools/llvm-profgen/X86/Inputs/missing-dwarf.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/multi-load-segs.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/multi-load-segs.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-noprobe.aggperfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-pseudoprobe.aggperfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-tailcall-probe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-tailcall-probe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.aggperfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.mmap.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/out-of-bounds.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/pie-dap-perf.txt
A llvm/test/tools/llvm-profgen/X86/Inputs/pie-lbr-perf.script
A llvm/test/tools/llvm-profgen/X86/Inputs/profile-density-cs.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/profile-density.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-pseudoprobe-nommap.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-single.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-single.o.yaml
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-split.dwo.yaml
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-split.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/symbolize.ll
A llvm/test/tools/llvm-profgen/X86/Inputs/symbolize.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/truncated-pseudoprobe.ll
A llvm/test/tools/llvm-profgen/X86/Inputs/truncated-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/truncated-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-dwarf.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-dwarf.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-probe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-probe.perfscript
A llvm/test/tools/llvm-profgen/X86/afdo-with-vtable-pie.test
A llvm/test/tools/llvm-profgen/X86/afdo-with-vtable.test
A llvm/test/tools/llvm-profgen/X86/callback-external-addr.test
A llvm/test/tools/llvm-profgen/X86/coff-profile.test
A llvm/test/tools/llvm-profgen/X86/cold-profile-trimming-symbolized.test
A llvm/test/tools/llvm-profgen/X86/cold-profile-trimming.test
A llvm/test/tools/llvm-profgen/X86/context-depth.test
A llvm/test/tools/llvm-profgen/X86/coroutine.test
A llvm/test/tools/llvm-profgen/X86/cs-extbinary.test
A llvm/test/tools/llvm-profgen/X86/cs-external-address.test
A llvm/test/tools/llvm-profgen/X86/cs-interrupt.test
A llvm/test/tools/llvm-profgen/X86/cs-invalid-ret-addr.test
A llvm/test/tools/llvm-profgen/X86/cs-preinline-cost.test
A llvm/test/tools/llvm-profgen/X86/cs-preinline-sample-profile.test
A llvm/test/tools/llvm-profgen/X86/cs-preinline.test
A llvm/test/tools/llvm-profgen/X86/cs-tailcall.test
A llvm/test/tools/llvm-profgen/X86/disassemble.test
A llvm/test/tools/llvm-profgen/X86/etm-non-arm.test
A llvm/test/tools/llvm-profgen/X86/filter-ambiguous-profile.test
A llvm/test/tools/llvm-profgen/X86/fname-canonicalization.test
A llvm/test/tools/llvm-profgen/X86/fs-discriminator-probe.test
A llvm/test/tools/llvm-profgen/X86/fs-discriminator.test
A llvm/test/tools/llvm-profgen/X86/func-split.test
A llvm/test/tools/llvm-profgen/X86/inline-cs-noprobe.test
A llvm/test/tools/llvm-profgen/X86/inline-cs-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/inline-force-dwarf.test
A llvm/test/tools/llvm-profgen/X86/inline-noprobe.test
A llvm/test/tools/llvm-profgen/X86/inline-noprobe2.test
A llvm/test/tools/llvm-profgen/X86/inline-probe-afdo.test
A llvm/test/tools/llvm-profgen/X86/inline-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/invalid-perfscript.test
A llvm/test/tools/llvm-profgen/X86/invalid-range.test
A llvm/test/tools/llvm-profgen/X86/lit.local.cfg
A llvm/test/tools/llvm-profgen/X86/merge-cold-profile.test
A llvm/test/tools/llvm-profgen/X86/missing-dwarf.test
A llvm/test/tools/llvm-profgen/X86/mmapEvent.test
A llvm/test/tools/llvm-profgen/X86/multi-load-segs.test
A llvm/test/tools/llvm-profgen/X86/noinline-cs-noprobe.test
A llvm/test/tools/llvm-profgen/X86/noinline-cs-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/noinline-noprobe.test
A llvm/test/tools/llvm-profgen/X86/noinline-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/profile-density.test
A llvm/test/tools/llvm-profgen/X86/pseudo-probe-desc-mismatch.test
A llvm/test/tools/llvm-profgen/X86/pseudoprobe-decoding-discriminator.test
A llvm/test/tools/llvm-profgen/X86/pseudoprobe-decoding.test
A llvm/test/tools/llvm-profgen/X86/recursion-compression-noprobe.test
A llvm/test/tools/llvm-profgen/X86/recursion-compression-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/separate-debuginfo-binary.test
A llvm/test/tools/llvm-profgen/X86/split-dwarf.test
A llvm/test/tools/llvm-profgen/X86/symbolize.test
A llvm/test/tools/llvm-profgen/X86/truncated-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/update-samples.test
R llvm/test/tools/llvm-profgen/aarch64-disassemble-all-features.test
R llvm/test/tools/llvm-profgen/afdo-with-vtable-pie.test
R llvm/test/tools/llvm-profgen/afdo-with-vtable.test
R llvm/test/tools/llvm-profgen/callback-external-addr.test
R llvm/test/tools/llvm-profgen/coff-profile.test
R llvm/test/tools/llvm-profgen/cold-profile-trimming-symbolized.test
R llvm/test/tools/llvm-profgen/cold-profile-trimming.test
R llvm/test/tools/llvm-profgen/context-depth.test
R llvm/test/tools/llvm-profgen/coroutine.test
R llvm/test/tools/llvm-profgen/cs-extbinary.test
R llvm/test/tools/llvm-profgen/cs-external-address.test
R llvm/test/tools/llvm-profgen/cs-interrupt.test
R llvm/test/tools/llvm-profgen/cs-invalid-ret-addr.test
R llvm/test/tools/llvm-profgen/cs-preinline-cost.test
R llvm/test/tools/llvm-profgen/cs-preinline-sample-profile.test
R llvm/test/tools/llvm-profgen/cs-preinline.test
R llvm/test/tools/llvm-profgen/cs-tailcall.test
R llvm/test/tools/llvm-profgen/disassemble.test
R llvm/test/tools/llvm-profgen/etm-arch.test
R llvm/test/tools/llvm-profgen/etm-opencsd.test
R llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test
R llvm/test/tools/llvm-profgen/fname-canonicalization.test
R llvm/test/tools/llvm-profgen/fs-discriminator-probe.test
R llvm/test/tools/llvm-profgen/fs-discriminator.test
R llvm/test/tools/llvm-profgen/func-split.test
R llvm/test/tools/llvm-profgen/inline-cs-noprobe.test
R llvm/test/tools/llvm-profgen/inline-cs-pseudoprobe.test
R llvm/test/tools/llvm-profgen/inline-force-dwarf.test
R llvm/test/tools/llvm-profgen/inline-noprobe.test
R llvm/test/tools/llvm-profgen/inline-noprobe2.test
R llvm/test/tools/llvm-profgen/inline-probe-afdo.test
R llvm/test/tools/llvm-profgen/inline-pseudoprobe.test
R llvm/test/tools/llvm-profgen/invalid-perfscript.test
R llvm/test/tools/llvm-profgen/invalid-range.test
M llvm/test/tools/llvm-profgen/lit.local.cfg
R llvm/test/tools/llvm-profgen/merge-cold-profile.test
R llvm/test/tools/llvm-profgen/missing-dwarf.test
R llvm/test/tools/llvm-profgen/mmapEvent.test
R llvm/test/tools/llvm-profgen/multi-load-segs.test
R llvm/test/tools/llvm-profgen/noinline-cs-noprobe.test
R llvm/test/tools/llvm-profgen/noinline-cs-pseudoprobe.test
R llvm/test/tools/llvm-profgen/noinline-noprobe.test
R llvm/test/tools/llvm-profgen/noinline-pseudoprobe.test
R llvm/test/tools/llvm-profgen/profile-density.test
R llvm/test/tools/llvm-profgen/pseudo-probe-desc-mismatch.test
R llvm/test/tools/llvm-profgen/pseudoprobe-decoding-discriminator.test
R llvm/test/tools/llvm-profgen/pseudoprobe-decoding.test
R llvm/test/tools/llvm-profgen/recursion-compression-noprobe.test
R llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test
R llvm/test/tools/llvm-profgen/separate-debuginfo-binary.test
R llvm/test/tools/llvm-profgen/split-dwarf.test
R llvm/test/tools/llvm-profgen/symbolize.test
R llvm/test/tools/llvm-profgen/truncated-pseudoprobe.test
R llvm/test/tools/llvm-profgen/update-samples.test
Log Message:
-----------
[llvm-profgen][test] Split tests by target architecture (#207724)
The top-level llvm-profgen lit configuration previously disabled the
entire test directory unless the X86 target was registered. As a result,
target-independent tests and tests for ARM and AArch64 also implicitly
depended on X86.
Split target-specific tests and inputs into X86, ARM, and AArch64
directories with per-directory lit.local.cfg files. Leave help.test at
the top level because it is target-independent. Existing X86 tests
remain guarded by X86 and run as before, while ARM and AArch64 tests no
longer require the X86 target. The X86 non-ARM ETM rejection case also
no longer requires the ARM target; it only requires X86 and OpenCSD.
Split the former etm-arch.test into ARM/etm-arch.test, containing the
two ARM-specific checks, and X86/etm-non-arm.test, containing the
existing X86 rejection check. The tested inputs and expected diagnostics
are preserved.
Update match-blocks-with-pseudo-probes-inline.test,
pseudoprobe-decoding-inline.test, and pseudoprobe-decoding-noinline.test
in BOLT to refer to the relocated X86 inputs. All other llvm-profgen
tests and inputs are pure renames.
This does not change llvm-profgen runtime behavior; it only removes
unnecessary cross-target dependencies from its test suite.
This is a preparatory change for extending llvm-profgen profiling
support to AArch64 and for introducing the universal profile-guided
automatic software loop data prefetcher described in the RFC:
https://discourse.llvm.org/t/rfc-universal-profile-guided-automatic-software-loop-data-prefetcher-for-llvm/90916
Commit: 6e7afc10170d711659cbbf0dc25e81f457bda409
https://github.com/llvm/llvm-project/commit/6e7afc10170d711659cbbf0dc25e81f457bda409
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
Log Message:
-----------
[orc-rt] Remove doxygen comments from logging implemenetation APIs (#209086)
These APIs are intended for internal consumption by the ORC runtime's
logging system: plain comments are more appropriate here than doxygen
comments.
Commit: 2bcb848904ae3a2bd7bd3bfb8a8f562529ccb318
https://github.com/llvm/llvm-project/commit/2bcb848904ae3a2bd7bd3bfb8a8f562529ccb318
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
Log Message:
-----------
[orc-rt] Require ORC_RT_LOG format strings to be string literals (#209090)
os_log needs the format string as a literal (it builds format metadata
at the call site), while the none and printf backends accept a runtime
const char*. That mismatch let a non-literal format compile on
none/printf and fail only on an os_log build. Enforce the literal
requirement uniformly in the ORC_RT_LOG macro via an unevaluated
sizeof("" ...) check, so it is caught at the call site on every backend.
Commit: a0f98011c4a82aab540fe9efa68aafb251a3b1b7
https://github.com/llvm/llvm-project/commit/a0f98011c4a82aab540fe9efa68aafb251a3b1b7
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVMacroFusion.td
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir
Log Message:
-----------
[RISCV] Fuse QC_E_LI to Loads/Store (#208134)
The QC Access relocations require the `qc.e.li` to be adjacent to its
load/store. This ensures that happens, and allows more relaxation
opportunities.
Commit: fb8c7da5b86b9911e1ae677e147bead6e9b115b8
https://github.com/llvm/llvm-project/commit/fb8c7da5b86b9911e1ae677e147bead6e9b115b8
Author: Matthias Wippich <mfwippich at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/TokenKinds.h
Log Message:
-----------
[clang][NFC] move TokenKey to TokenKinds.h (#208867)
This patch moves the `TokenKey` enum closer to where it's actually used.
This is in preparation to generate it from tablegen once the definition
has been moved.
Commit: ca970f3bb3ce41365dfc85049db44489c88cb0a5
https://github.com/llvm/llvm-project/commit/ca970f3bb3ce41365dfc85049db44489c88cb0a5
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
Log Message:
-----------
[VPlan] Simplify reverses through unary ops (fneg) (#208257)
By marking fneg as elementwise
Commit: f97cdc4aaad6990f6c9adfad50f67acf9c5349ac
https://github.com/llvm/llvm-project/commit/f97cdc4aaad6990f6c9adfad50f67acf9c5349ac
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
Log Message:
-----------
[PowerPC] Specify inlining behavior in TableGen (#206938)
Remove the custom areInlineCompatible() implementation and specify the
inlining behavior in TableGen instead.
I've tried to classify these to the best of my ability. Most features
stay at InlineDefault with the usual "caller can have more features than
callee" semantics. Tuning features are InlineIgnore. This includes all
the directive features, which, as far as I can tell, are only used for
tuning heuristics.
I also marked a few InlineMustMatch/InlineInverse, though I'm not
particularly confident on which ones are required to match.
Commit: 2119e359b1f968da94ff27a4078d569e18903aef
https://github.com/llvm/llvm-project/commit/2119e359b1f968da94ff27a4078d569e18903aef
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/ELF/LinkerScript.cpp
A lld/test/ELF/gnu-build-attributes.s
Log Message:
-----------
[lld][ELF] Concatenate .gnu.build.attributes.* sections (#208737)
ld.bfd/ld.gold have been concatenating the GNU build attribute sections
since 2018:
https://gitlab.com/gnutools/binutils-gdb/-/commit/7d8a31665739412395f6dd370d2279acd322e78e
Do the same in LLD. These do not have a dedicated section type or flags,
so this is handled by the name-based logic. (Peculiarly, there used to
be SHF_GNU_BUILD_NOTE, but it was removed again.)
Not concatenating these results in a huge number of sections, which
breaks tools like `file`.
Commit: 56e62e539eb65ebe4ec9fc6de0328fea21ae86fd
https://github.com/llvm/llvm-project/commit/56e62e539eb65ebe4ec9fc6de0328fea21ae86fd
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/simd-arith.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/WebAssembly/vector-reduce.ll
Log Message:
-----------
[WebAssembly] Use generic pseudo_fmin/pseudo_fmax opcodes (#208454)
The pmin/pmax instructions are equivalent to these with operands
swapped.
The existing matching code for these instructions was incorrect, because
it failed to handle signed zeros and NaNs properly. You can't treat
strict and non-strict comparisons the same in this context.
Commit: 32f3f9dfce7ba9042ebfe7b42e72139454d29672
https://github.com/llvm/llvm-project/commit/32f3f9dfce7ba9042ebfe7b42e72139454d29672
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
Log Message:
-----------
[SLP][NFC] Pre-commit tests for select IR-flag/metadata propagation (#208150)
Pre-commits regression tests for an upcoming SLPVectorizer fix (see
#207982). These IR shapes are currently vectorized by SLP, and the
vectorization is functionally correct but when a bundle of
scalar`select` instructions is vectorized, the resulting vector `select`
drops the fast-math flags (and other IR flags/metadata such as
`!unpredictable`) that were common to every scalar lane.
This NFC patch records the current (buggy) behavior so that the
follow-up fix's diff is limited to the behavioural change: `select_nnan`
currently loses `nnan` on the vectorized select, while
`select_not_all_nnan` (one lane missing `nnan`) correctly has none.
Co-authored-by: Ayush Rai <Ayush.Rai at amd.com>
Commit: 2de67c330a9739e559f88de9874d4cba3ffc50ca
https://github.com/llvm/llvm-project/commit/2de67c330a9739e559f88de9874d4cba3ffc50ca
Author: David Green <david.green at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[AArch64] Clear kill flags from visitINSvi64lane (#209096)
If we replace a reg, we can have more uses meaning the kill flags are no
longer
valid. Make sure we remove them in case.
Commit: f48baca733790625d08b7bbfb64ada65516c06f3
https://github.com/llvm/llvm-project/commit/f48baca733790625d08b7bbfb64ada65516c06f3
Author: Alon Filler <alonfiller at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/docs/NewLLD.rst
Log Message:
-----------
[Docs][NFC] Fix a few typos in NewLLD.rst (#193569)
Commit: c47d1cf955f607fea1d089b9e05aedf8867231ff
https://github.com/llvm/llvm-project/commit/c47d1cf955f607fea1d089b9e05aedf8867231ff
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRTypes.td
M flang/lib/Optimizer/Dialect/FIRType.cpp
A flang/test/Fir/derived-type-aliases.fir
Log Message:
-----------
[flang][FIR] implement asm alias interface for fir.type under option (#208665)
FIR is extremely verbose with derived types because the type lists all
the component names and types, so in case of nested derived type, the
type length in the assembly may grow over thousands of characters.
This patch implements the `getAlias` that allows using the fir.type name
as the MLIR type alias. This significantly reduce the IR size in
application with derived type.
I am planning to enable this by default, but there will be some churn in
the lit test, so I am first adding it under a developer option.
Assisted-by: Cursor
Commit: 3a61e727bc056024bdf4960e914ec6651fd41a72
https://github.com/llvm/llvm-project/commit/3a61e727bc056024bdf4960e914ec6651fd41a72
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/test/CodeGen/ARM/estimate-size-copy.mir
Log Message:
-----------
[ARM][Thumb1] Improve EstimateFunctionSizeInBytes accuracy (#203318)
The estimate of a function size now includes (what I hope are) upper
bounds on the size of the prologue and epilogue; adds size estimates for
some pseudo-instructions that were previously counted as 0; and
increases the estimates for things that were previously optimistic, such
as assuming no constant pool entry ever needs to be duplicated. The
estimation function is also passed extra information to use for
adjusting its estimates, such as the BigFrameOffsets flag which makes
some pseudos have much longer expansions.
Background:
EstimateFunctionSizeInBytes is supposed to estimate how large a Thumb1
function will end up, in advance of actually doing the full code
generation. It must overestimate rather than underestimating, because
large functions need a special precaution (namely, making sure LR is
stacked, so that BL can be used for an intra-function long branch). In
multiple cases recently it has underestimated, leading to a crash later
in code generation, when ARMConstantIslandsPass needs to insert an
intra-function BL and finds that it isn't safe to corrupt LR.
Discussion on Discourse suggested that it's OK to overestimate by quite
a large factor, because any significantly large function won't be badly
impacted by a push of LR that turns out to be unnecessary. The main
place where we want to leave out those unnecessary pushes is _really_
small leaf functions, where the extra push and pop might be a
significant fraction of the whole call.
Commit: 1651159f32cfcf82ecbb364dbf879e97b53d8060
https://github.com/llvm/llvm-project/commit/1651159f32cfcf82ecbb364dbf879e97b53d8060
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/tools/mlir-irdl-to-cpp/CMakeLists.txt
M mlir/tools/mlir-src-sharder/CMakeLists.txt
Log Message:
-----------
[MLIR] Install missing standalone helper tools (#205066)
Standalone MLIR installs CMake package files that can reference helper
executables needed by downstream builds. Most helper tools already have
install paths available through existing LLVM tool and utility install
options, but `mlir-src-sharder` does not pass an install destination to
`add_tablegen` and `mlir-irdl-to-cpp` does not define an install rule.
Install those two missing helpers.
Co-authored-by: Luca Fancellu <luca.fancellu at arm.com>
Commit: 6e8a4ce8343f2d489f5ecdca5cd443a584f77e71
https://github.com/llvm/llvm-project/commit/6e8a4ce8343f2d489f5ecdca5cd443a584f77e71
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/docs/resources/build.md
Log Message:
-----------
[lldb][docs] Make it clear that we require SWIG >= 4 (#208687)
We said this in "Preliminaries", but later had a note about SWIG < 4. So
if you hadn't read
the first part properly, it looked like we allow < 4.
We do not, so I've removed the note about < 4 and
added SWIG to the "Optional Dependencies" table
for extra emphasis.
Commit: cec7cf4c3dd71068495245111553e4fba3d35c5e
https://github.com/llvm/llvm-project/commit/cec7cf4c3dd71068495245111553e4fba3d35c5e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir
M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
M llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll
M llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll
M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
M llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
M llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/callbr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/callbr.ll
M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/chain-node-divergence-update-crash-issue-173885.ll
M llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
M llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/cluster-dims.ll
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
M llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
M llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
M llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll
M llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
M llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
M llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
M llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
M llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
M llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null-vector.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (9) (#208893)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6e42e25efa9856d360fb38ef3a6e7a7c3334dd33
https://github.com/llvm/llvm-project/commit/6e42e25efa9856d360fb38ef3a6e7a7c3334dd33
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir
M llvm/test/CodeGen/AMDGPU/commute-op-sel.mir
M llvm/test/CodeGen/AMDGPU/commute-shifts.ll
M llvm/test/CodeGen/AMDGPU/commute-vop3.mir
M llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll
M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
M llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/convergence-laneops.ll
M llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
M llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg.ll
M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
M llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
M llvm/test/CodeGen/AMDGPU/csr-gfx10.ll
M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
M llvm/test/CodeGen/AMDGPU/ctls.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll
M llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
M llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/dead-lane.mir
M llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/debug-frame.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
M llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/debug.ll
M llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
M llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
M llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
M llvm/test/CodeGen/AMDGPU/divergence-at-use.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/divrem24-assume.ll
M llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (10) (#208894)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 9e8b030aa80b78abaa054b5f75c36f51d1995088
https://github.com/llvm/llvm-project/commit/9e8b030aa80b78abaa054b5f75c36f51d1995088
Author: Hugo Trachino <hugo.trachino at huawei.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/test/Dialect/Linalg/flatten-elementwise.mlir
M mlir/test/Dialect/Linalg/flatten-unsupported.mlir
Log Message:
-----------
[MLIR][Linalg] Fix FlattenElementwiseOp on broadcasted linalgs (#207005)
Applying FlattenElementwiseLinalgOp on Broadcasted linalg would break.
This transformation is not valid for those usecase, so I added a
condition to exit gracefully instead.
Commit: abd72b0eb7807a98c261a6cac35a969f954a76cd
https://github.com/llvm/llvm-project/commit/abd72b0eb7807a98c261a6cac35a969f954a76cd
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A offload/test/offloading/fortran/target-teams-if-runtime-init.f90
M openmp/device/src/Kernel.cpp
Log Message:
-----------
[OpenMP] Publish target-init team state with acq_rel barrier (#208701)
In __kmpc_target_init, thread 0 initializes the team state in LDS
(HasThreadState = 0, ThreadStates = nullptr) and then releases the other
threads with synchronize::threadsAligned(atomic::relaxed). Because the
relaxed ordering emits no memory fence, the initializing LDS stores are
not guaranteed to be visible to the worker threads before they proceed.
A worker thread can then read the uninitialized team state and produce
wrong results or crash. This is the flow that causes the race as I
understand it.
```
__kmpc_target_init (Kernel.cpp:107)
-> initializeRuntime (Kernel.cpp:38)
-> state::init (State.cpp:286)
-> TeamState.init(IsSPMD) (State.cpp:295)
-> HasThreadState = false (State.cpp:248) // <-- the value later read stale
ThreadStates = nullptr (State.cpp:296)
-> synchronize::threadsAligned(atomic::relaxed) (Kernel.cpp:115) // <-- insufficient barrier:
// relaxed emits no fence, so the state stores above are not published to the other threads
... worker threads continue past the barrier ...
__kmpc_parallel_60 (Parallelism.cpp:143)
if (OMP_UNLIKELY(!if_expr || state::HasThreadState || ...)) (Parallelism.cpp:158)
^ reads HasThreadState from LDS; a stale/unpublished value (!= 0)
diverts the worker onto the wrong (serialized) path
```
The fix changes the barrier at Kernel.cpp:115 from atomic::relaxed to
atomic::acq_rel so that the memory fences are emitted.
Reproducing the problem requires an `if` clause with a non-constant
condition on the target region. The worker's read of HasThreadState
originates from the serialized-region check in __kmpc_parallel_60. When
the `if` condition is constant (or absent), the optimizer can prove that
branch is dead and eliminates the HasThreadState load entirely, so the
race has nothing to observe. A non-constant `if` keeps if_expr, and
hence the LDS read alive, exposing the problem.
I have added a Fortran offload regression test that launches a target
region many times to make the timing-dependent race likely to surface.
Fixes https://github.com/llvm/llvm-project/issues/208698.
Assisted-by: Cursor
Commit: 3de2e4a3f11390db0c026f54edf86bd8f6997947
https://github.com/llvm/llvm-project/commit/3de2e4a3f11390db0c026f54edf86bd8f6997947
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] diagnose reads from non-constant local variables... (#208990)
... if we're in the bottom frame.
Commit: 13dbff365eabc45fcc26a36ef077f52b6e168347
https://github.com/llvm/llvm-project/commit/13dbff365eabc45fcc26a36ef077f52b6e168347
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/unroll-partial01.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Dialect/OpenMP/cli-unroll-partial.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
A mlir/test/Target/LLVMIR/openmp-unroll-partial01.mlir
A mlir/test/Target/LLVMIR/openmp-unroll-partial02.mlir
Log Message:
-----------
[Flang][Openmp] Implement support for partial in unroll construct (#206642)
As described in section 9.2.2 of openmp 5.2 spec, the patch implements
support for partial in unroll construct.
Commit: e3e15695a0e9b1acd3a4821cdeea353ce951f5da
https://github.com/llvm/llvm-project/commit/e3e15695a0e9b1acd3a4821cdeea353ce951f5da
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
M llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
M llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
M llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir
M llvm/test/CodeGen/AMDGPU/dumpcode.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-indirect.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16_anon.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/early-inline-alias.ll
M llvm/test/CodeGen/AMDGPU/early-inline.ll
M llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir
M llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir
M llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir
M llvm/test/CodeGen/AMDGPU/early-term.mir
M llvm/test/CodeGen/AMDGPU/eh_frame.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
M llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
M llvm/test/CodeGen/AMDGPU/elf-note-null-terminator.ll
M llvm/test/CodeGen/AMDGPU/elf.ll
M llvm/test/CodeGen/AMDGPU/elf.metadata.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/else.ll
M llvm/test/CodeGen/AMDGPU/emit-high-vgprs.mir
M llvm/test/CodeGen/AMDGPU/empty-function.ll
M llvm/test/CodeGen/AMDGPU/empty-text.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
M llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling-no-outstanding.ll
M llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
M llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
M llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx1250.mir
M llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir
M llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
M llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
M llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extload.ll
M llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
M llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll
M llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-binop-build-vector.ll
M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (11) (#208895)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b4698d8d53e9b228bd84676ae83637b52a30d0e9
https://github.com/llvm/llvm-project/commit/b4698d8d53e9b228bd84676ae83637b52a30d0e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.ll
M llvm/test/CodeGen/AMDGPU/fadd64.ll
M llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
M llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
M llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcmp64.ll
M llvm/test/CodeGen/AMDGPU/fconst64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
M llvm/test/CodeGen/AMDGPU/ffloor.ll
M llvm/test/CodeGen/AMDGPU/finalizebundle.mir
M llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-block-end-iterator-debugloc.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-av-classes.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-readfirstlane-av-register-regression.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-sgpr32-to-vgpr16.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wmma-scale-lo256.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.mir
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/flat-address-space.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma-mix.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fma.f64.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
M llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll
M llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (12) (#208896)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b5e94d5ffca8fe3d7b063af48d9535d7b13af66a
https://github.com/llvm/llvm-project/commit/b5e94d5ffca8fe3d7b063af48d9535d7b13af66a
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/test/Lower/MIF/image_index.f90
Log Message:
-----------
[flang][MIF] Fix lowering sub argument in IMAGE_INDEX #208318 (#208544)
This PR fixes issue #208318, which did not correctly prepare the SUB
argument for IMAGE_INDEX in the correct type.
Commit: d097c2b764460284b186636b547573d309eaba8d
https://github.com/llvm/llvm-project/commit/d097c2b764460284b186636b547573d309eaba8d
Author: disservin <disservin.social at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[IR][NFC] Add parentheses around logical AND (#208512)
Fixes a `-Wparentheses` warning about unclear priority of operators.
Commit: d62c903ffd049da2a80acc7f0c0671447adc76f7
https://github.com/llvm/llvm-project/commit/d62c903ffd049da2a80acc7f0c0671447adc76f7
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Refactor the string benchmarks (#185397)
Fixes #179696
Commit: 95f1eab03f35545eb308246376541a7150a7a4e4
https://github.com/llvm/llvm-project/commit/95f1eab03f35545eb308246376541a7150a7a4e4
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
A llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
M llvm/test/CodeGen/RISCV/jump-is-expensive.ll
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
Log Message:
-----------
[RISCV] Add getJumpConditionMergingParams to support branch condition merging (#206897)
Override `getJumpConditionMergingParams` so that
`shouldKeepJumpConditionsTogether`
can decide whether to keep `br (and/or cond1, cond2)` merged into a
single
branch or split it into two branches, based on a configurable cost
threshold.
Previously RISC-V used the default cost `{-1, -1, -1}`, which always
split
the conditions. Now it returns a base cost calculated from
`MispredictPenalty`
(via scaling it down by an assumed misprediction rate 25%).
These values are controllable via
`riscv-br-merging-base-cost/-likely-bias/-unlikely-bias`.
This is another approach to #191158 when `TuneJumpIsExpensive` is not
set.
Commit: f8b07132c195ce2823f6a54cd978301af8c6d551
https://github.com/llvm/llvm-project/commit/f8b07132c195ce2823f6a54cd978301af8c6d551
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
Log Message:
-----------
[NFC][SPIR-V] Add emitSimpleExecutionMode helper to dedup single imm OpExecutionMode emission (#208674)
Commit: d0ac84b54b90c03f0ba54b7f1b75b43941d7a6b1
https://github.com/llvm/llvm-project/commit/d0ac84b54b90c03f0ba54b7f1b75b43941d7a6b1
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
Log Message:
-----------
[lldb][test] Fix XML register info test (#209124)
Missed by #208838, which is a follow up to #188049 which changed the
alignment rules.
Some of these tests have incorrect outputs now
and I will fix that later. For now at least
they pass again.
XML related tests are not being run in CI,
which I will also address later.
Commit: dc8ee15f2bbc5b18316f071c5ae746bd95609ade
https://github.com/llvm/llvm-project/commit/dc8ee15f2bbc5b18316f071c5ae746bd95609ade
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM conversion for SNegate (#206950)
Commit: 19f997320131c3d01e8ee32e1f22ee98a1ee0ec7
https://github.com/llvm/llvm-project/commit/19f997320131c3d01e8ee32e1f22ee98a1ee0ec7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
Log Message:
-----------
[NFC][SPIR-V] Remove unused LowLevelType parameter from buildLoadInst (#208428)
Commit: 717615829bba4035897a4ebdbdef919f31529762
https://github.com/llvm/llvm-project/commit/717615829bba4035897a4ebdbdef919f31529762
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/typeid.cpp
Log Message:
-----------
[clang][bytecode] Improve diagnostics on typeid field access (#209101)
Do some extra work to extract the requested field name.
Commit: da138053e78c5af7b83f49674b4e190e1803102d
https://github.com/llvm/llvm-project/commit/da138053e78c5af7b83f49674b4e190e1803102d
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN rcp builtins (#197447)
Adds codegen for the following AMDGCN reciprocal builtins:
- __builtin_amdgcn_rcp (double)
- __builtin_amdgcn_rcpf (float)
- __builtin_amdgcn_rcph (half)
- __builtin_amdgcn_rcp_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.rcp` intrinsic.
Commit: a0df86deb4295ff9ebebe54eb515bc49a7fb65f8
https://github.com/llvm/llvm-project/commit/a0df86deb4295ff9ebebe54eb515bc49a7fb65f8
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add TuneNoDefaultUnroll to spacemit-x100 (#209069)
In the spec2k6int tests, some subtests improved while others
regressed. The overall score shows a 0.7% gain. Given that
most OoO CPUs enable this feature by default, also enable
it by default for X100.
Commit: cb71fefb2258fdd00747043a9c322f95d684b000
https://github.com/llvm/llvm-project/commit/cb71fefb2258fdd00747043a9c322f95d684b000
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/pr125278.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/pr38697.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/replace-first-order-recurrence-by-versioned-iv.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/scev-exit-phi-invalidation.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vplan-native-path-inner-loop-with-runtime-checks.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
Log Message:
-----------
[VPlan] Expand SCEV min/max via scalar intrinsic VPInstructions. (#207842)
Use the VPInstruction::Intrinsic opcode to expand min/max SCEV
expressions to LLVM min/max intrinsics as VPInstructions.
The operands are chained in reverse order, matching SCEVExpander's
expansion of min/max expressions.
This helps to clean up another set of duplicated vscale calls.
Depends on https://github.com/llvm/llvm-project/pull/207541
Depends on https://github.com/llvm/llvm-project/pull/207836
PR: https://github.com/llvm/llvm-project/pull/207842
Commit: 6461bd3749dc09698b76c3349e7b4befab7f7f9b
https://github.com/llvm/llvm-project/commit/6461bd3749dc09698b76c3349e7b4befab7f7f9b
Author: Le Gia Bao <legiabao7300 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M polly/lib/Support/ScopHelper.cpp
A polly/test/CodeGen/issue205137.ll
Log Message:
-----------
[Polly] Fix infinite recursion in `ScopExpander::visitAddRecExpr` (#206063)
visitUnknown follow VMap, call GenSE.getSCEV() on the mapped value, and
get back the original AddRec, recursing visitAddRecExpr infinitely.
Insert the result into SCEVCache before calling visit() to cut
recursion.
Fixes #205137.
Commit: 5db1f5442ef0c9bcb2f4ca362361daaf2a76acfb
https://github.com/llvm/llvm-project/commit/5db1f5442ef0c9bcb2f4ca362361daaf2a76acfb
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/make_signed.h
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/wrappers.h
A compiler-rt/test/ubsan/TestCases/Integer/suppressions-nested-calls.c
Log Message:
-----------
compiler-rt: ubsan: Add suppressions test for nested functions (#206962)
This is a test-only change to increase the test coverage of UBSan to
clarify that named suppressions only apply to the function itself and do
not cover (possibly inlined) called functions.
The background is that, while trying to fix
https://github.com/llvm/llvm-project/issues/132533, I discovered missing
test coverage and possibly confused myself into a wrong fix in
https://github.com/llvm/llvm-project/pull/206735#discussion_r3505816693
So I think it could make sense to add test coverage for the case that I
broke, which serves as a reference baseline ground truth.
---------
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: 6d026ea1d89795532c7ead1e57676bd1d1018afb
https://github.com/llvm/llvm-project/commit/6d026ea1d89795532c7ead1e57676bd1d1018afb
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
Log Message:
-----------
[AMDGPU] Remove option to disable SGPR hazard waits (#208720)
This was useful when initially implemented, but probably be removed now.
Commit: 13e9cc22ce4edfd4b1347d6bed9cd95868e2d4f4
https://github.com/llvm/llvm-project/commit/13e9cc22ce4edfd4b1347d6bed9cd95868e2d4f4
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/xsmtvdotii-invalid.s
A llvm/test/MC/RISCV/xsmtvdotii-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Support spacemit vsmtvdotii extensions (#202533)
SPEC: https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
Commit: 8cb0e63054ce96860b12d68218eb67c97bc6c378
https://github.com/llvm/llvm-project/commit/8cb0e63054ce96860b12d68218eb67c97bc6c378
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (#200751)
The `luti6` instruction (four registers, 8-bit) should only allow
assembly of `0 <= Zn <= 7`, since there's only 3 bits for `Zn`. It
actually allows > 7:
```
luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```
Update tablegen to handle the inferred register-class naming
collision caused by adding the explicit z0-z7 ZPR3 class.
Commit: 3966381ccbd135e34b44a746187ac6c5140df4cd
https://github.com/llvm/llvm-project/commit/3966381ccbd135e34b44a746187ac6c5140df4cd
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/source/Core/DumpRegisterValue.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
M lldb/test/API/linux/aarch64/permission_overlay/TestAArch64LinuxPOE.py
Log Message:
-----------
[lldb] Correct alignment of register fields (#209140)
In #188049 the alignment of register names for the raw value part "pc =
0x..." changed.
This resulted in many register fields being 2 spaces off where they
should be, because the stream we were printing to had a 2 space indent
set where it had none before.
This is actually a bug in the original field formatting code. It assumed
the stream had no indent level of its own. So the fix is to indent using
the stream (the 2 spaces), then indent to where the register name ends.
Commit: 6c009ff4b39ec2a0233c40c87f8f3709e9dc2eff
https://github.com/llvm/llvm-project/commit/6c009ff4b39ec2a0233c40c87f8f3709e9dc2eff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fminnum.f64.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
M llvm/test/CodeGen/AMDGPU/fmul64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
M llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-pk64.mir
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fold-literal-multiple-gfx10.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
M llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
M llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
M llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
M llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
M llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
M llvm/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
M llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
M llvm/test/CodeGen/AMDGPU/force-wait-after-always-gds.mir
M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp32_to_bf16.ll
M llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (13) (#208897)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: d76f677c075b71e2a5c2ee35539992d753258e2a
https://github.com/llvm/llvm-project/commit/d76f677c075b71e2a5c2ee35539992d753258e2a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpenv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fpext.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui_uitofp.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/fract.f64.ll
M llvm/test/CodeGen/AMDGPU/fract.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frame-index.mir
M llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/frexp-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/fshl-scalar-shift-zero.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/fsub64.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.ll
M llvm/test/CodeGen/AMDGPU/function-alignment.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-call-relocs.ll
M llvm/test/CodeGen/AMDGPU/function-esm2-prologue-epilogue.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gcn-reg-pressure-true16-integer-overflow.mir
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gds-atomic.ll
M llvm/test/CodeGen/AMDGPU/gds-unsupported.ll
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll
M llvm/test/CodeGen/AMDGPU/gfx10plus-wavefront-sgpr-count.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/gfx942-hazards.mir
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (14) (#209117)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b0158bbd4fec69feda78752270573e505d53ddcf
https://github.com/llvm/llvm-project/commit/b0158bbd4fec69feda78752270573e505d53ddcf
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/test/CMakeLists.txt
M orc-rt/test/regression/init.test
M orc-rt/test/regression/lit.cfg.py
M orc-rt/tools/CMakeLists.txt
A orc-rt/tools/ogre/CMakeLists.txt
A orc-rt/tools/ogre/ogre.cpp
R orc-rt/tools/orc-executor/CMakeLists.txt
R orc-rt/tools/orc-executor/orc-executor.cpp
Log Message:
-----------
[orc-rt] Rename orc-executor to ogre (#209143)
The ORC Generic Runtime Environment (OGRE) will serve as our canonical
"blank executor" program: A program that simply listens for an ORC
controller connection, then runs whatever program is provided to it by
the controller.
Commit: 3081049a69f85dd4079a959c4e50c6ccf9f691d0
https://github.com/llvm/llvm-project/commit/3081049a69f85dd4079a959c4e50c6ccf9f691d0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Opcode.h
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/unittests/Disassembler/CMakeLists.txt
A lldb/unittests/Disassembler/x86/TestGetOpcodeOversized.cpp
Log Message:
-----------
[lldb] Don't build an opcode from a failed disassembly (#208279)
lldb does not check if the instruction was decoded correctly. This
causes the following assert to hit:
https://github.com/llvm/llvm-project/blob/06499c927e5012166f4553c58f8af593521ea14d/lldb/include/lldb/Core/Opcode.h#L214
due to a buffer overflow. This happens when starting `lldb-dap` on
Windows with `lldb-server`.
This patch clamps the instruction size to the maximum possible
instruction size possible to avoid the assert to hit. It also adds a
regression test.
Related:
- https://github.com/llvm/llvm-project/pull/208277.
Commit: efd160260d8437710714d8a3ba9301f45d61ee95
https://github.com/llvm/llvm-project/commit/efd160260d8437710714d8a3ba9301f45d61ee95
Author: Aleksandr Popov <42888396+aleks-tmb at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
Log Message:
-----------
[SCEV][NFC] Address post-merge comments on precommit test (#209094)
Drop unnecessary atomic/unordered loads, unify block label naming.
Follow-up to b33af86b032e (#208784).
Commit: a5fc1d68f995744af71b91663e9f46910d9345ca
https://github.com/llvm/llvm-project/commit/a5fc1d68f995744af71b91663e9f46910d9345ca
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
A llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
Log Message:
-----------
[gn] port cc048e80b670 more (#209156)
00cd65638a7cf attempted this, but it was incomplete.
Commit: a4364df185433cd37b793aa4ff64cba1c72dcbda
https://github.com/llvm/llvm-project/commit/a4364df185433cd37b793aa4ff64cba1c72dcbda
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode] Handle invalid function in CXXInheritedCtorInitExpr (#209138)
Commit: db28e48d67e3b0c44d88be9ea2d28eca2d239a9a
https://github.com/llvm/llvm-project/commit/db28e48d67e3b0c44d88be9ea2d28eca2d239a9a
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/test/Analysis/ArrayBound/assumption-reporting.c
M clang/test/Analysis/bitwise-shift-common.c
M clang/test/Analysis/constant-folding.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/string.c
Log Message:
-----------
[analyzer] Smarter range inference for {+,-,*} (#209048)
SymbolicRangeInferrer previously fell back to the full range of the
result type for BO_Add, BO_Sub and BO_Mul, discarding any constraints
known about the operands.
This caused a false positive in optin.taint.TaintedAlloc: a bounded
tainted value multiplied by a constant
(e.g. `malloc(groups * sizeof(gid_t))` with `groups` bounded) was
treated as unbounded whenever the multiplication was done in a wide
(e.g. 64-bit size_t) type, because the operand's range was lost. A
32-bit multiplication accidentally avoided the warning only because the
narrow result type already bounds the value below SIZE_MAX/4. Fixes
#173113
---
With `inferFromCorners` we compute the smallest and largest possible
outcome of the two range sets for `LHS {+,-,*} RHS`. If fails for some
reason, it falls back to the previous behavior and takes [MIN, MAX] for
type T - the most conservative range.
This patch also covers some pre-existing FIXMEs in the tests. I didn't
evaluate this change - however, I think it's harmless.
Assisted-by: Claude Opus 4.8
Commit: 3ae6937d0491665c2f47505e71e53ce5ef758424
https://github.com/llvm/llvm-project/commit/3ae6937d0491665c2f47505e71e53ce5ef758424
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn
Log Message:
-----------
[gn build] Port 1b879464b362 (#209147)
Commit: 7a9bbe00493434ad70bd3de0840c980fd88abde6
https://github.com/llvm/llvm-project/commit/7a9bbe00493434ad70bd3de0840c980fd88abde6
Author: rdevshp <rdevshp at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/BasicValueFactory.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
M clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
A clang/test/Analysis/z3/z3-logicalexpr-eval.c
M clang/test/Analysis/z3/z3-unarysymexpr.c
Log Message:
-----------
[analyzer] Fix unary/binary op support for SMT symbolic execution (#205078)
SMT symbolic execution:
The patch fixes unary op support, converts operands of logical operators
to boolean in getBinExpr, and clears the hasComparison flag in
getSymExpr when a boolean operand is converted to a non-bool integer.
This PR allows C functions like
```
int f(int x, int y) {
if (~(x && y))
return 0;
return 1;
}
```
to be analyzed with `-cc1 -analyze -analyzer-checker=core
-analyzer-constraints=z3`
Fixes #205037.
Assisted-by: Codex
Commit: cc11dd4aa650abce746953c4c243427c2a6d16cc
https://github.com/llvm/llvm-project/commit/cc11dd4aa650abce746953c4c243427c2a6d16cc
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
Log Message:
-----------
[gn build] Port 3bc47c8dc927 (#209148)
Commit: fb0563958e113bf9d384284ec2be1a73cfe7ff3e
https://github.com/llvm/llvm-project/commit/fb0563958e113bf9d384284ec2be1a73cfe7ff3e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
Log Message:
-----------
[gn build] Port 640079288c5e (#209149)
Commit: af30b76228e315fac32b8cf0b8282841d839c365
https://github.com/llvm/llvm-project/commit/af30b76228e315fac32b8cf0b8282841d839c365
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
Log Message:
-----------
[gn build] Port 9b9f44d1c55c (#209150)
Commit: ff331ac51c37746f5f3ea9679f791992e3d93918
https://github.com/llvm/llvm-project/commit/ff331ac51c37746f5f3ea9679f791992e3d93918
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
Log Message:
-----------
[gn build] Port c847ddf8f18d (#209151)
Commit: 6da5260422379a53aadc0aedacded102fcff3fac
https://github.com/llvm/llvm-project/commit/6da5260422379a53aadc0aedacded102fcff3fac
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
[gn build] Port d09048a46401 (#209152)
Commit: d9a5286ac41e54ed8aa73b61a8f173a9d0460085
https://github.com/llvm/llvm-project/commit/d9a5286ac41e54ed8aa73b61a8f173a9d0460085
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
Log Message:
-----------
[gn build] Port d1dbd484ada2 (#209153)
Commit: 4df8add1fd27371378285cd68cbfd3474e3f84b5
https://github.com/llvm/llvm-project/commit/4df8add1fd27371378285cd68cbfd3474e3f84b5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[gn build] Port e6673bd03771 (#209154)
Commit: e2dee8e8d047f858b03d451c37b3cc21dcefe69c
https://github.com/llvm/llvm-project/commit/e2dee8e8d047f858b03d451c37b3cc21dcefe69c
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port f99f2a582e94 (#209155)
Commit: 477bb26c7c0c5eee0491ce058968ce3c4b89623b
https://github.com/llvm/llvm-project/commit/477bb26c7c0c5eee0491ce058968ce3c4b89623b
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sat.mir
Log Message:
-----------
[GlobalISel] Add G_SADDSAT/G_UADDSAT/G_SSUBSAT/G_USUBSAT to computeKnownBits (#209075)
Add known-bits handling for the saturating arithmetic opcodes G_SADDSAT,
G_UADDSAT, G_SSUBSAT and G_USUBSAT in GISelValueTracking, using the
existing
`KnownBits::{sadd,uadd,ssub,usub}_sat` helpers - the same ones
ValueTracking
uses for the corresponding IR intrinsics. (On the SelectionDAG side only
`ISD::USUBSAT` is currently handled.)
The new test covers exact constant folding, all four saturation clamps
(255, 127, 0, -128), partially known operands, a vector case, and fully
unknown operands. Without the change, all of these results are unknown.
Part of #150515.
---
Assisted by Claude (Anthropic).
Commit: 308393ede14cc8533d1be122b5df88bf9ba4173b
https://github.com/llvm/llvm-project/commit/308393ede14cc8533d1be122b5df88bf9ba4173b
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
Log Message:
-----------
[LV] Allow scalable epilogue VFs matching the MainLoop VF (#208686)
This effectively limited scalable epilogue VFs to the MainLoopVF/2, as
all VFs are powers-of-two. This restriction does not exist for fixed
vector VFs. This could result in worse VF selections for scalable
epilogues (at high interleave counts), or in many cases only fixed
vectors selected (as there would be no allowed scalable VF in
ProfitableVFs).
Commit: 8a337c88d64e8d3fe918ae9fdc740fadbba2368c
https://github.com/llvm/llvm-project/commit/8a337c88d64e8d3fe918ae9fdc740fadbba2368c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
Log Message:
-----------
Revert "[SPIR-V] Simplify and fix sign-extension bug in convertCharsToWord (#207769)" (#209162)
This reverts commit 503f0ca19cfcc9c0c88d6918939a2c0038ad0498.
This is obviously incorrect on big endian architectures.
Commit: 16bd5ce1184bb5683ea96290478e5912cf2975b9
https://github.com/llvm/llvm-project/commit/16bd5ce1184bb5683ea96290478e5912cf2975b9
Author: Alex Bradbury <asb at igalia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
Log Message:
-----------
Reland [AArch64] Copy x4/x5 vararg payload into the x64 stack in Arm64EC exit thunks (#208453)
Reland llvm/llvm-project#190933, which was reverted by
llvm/llvm-project#198540 due to an EXPENSIVE_CHECKS build failure.
The fix relative to the reverted patch is to do the memcpy before the
final CALLSEQ_START for the dispatch call, avoiding nested call-frame
pseudos if memcpy lowers to a call.
Original commit message:
Currently the x4/x5 in a variadic Arm64EC exit thunks are treated by
LLVM like any other outgoing arguments. x4/x5 contain a pointer to the
first stack parameter and the size of the parameters passed on the
stack, and the generated exit thunk must memcpy these to the x86-64
stack. Current MSVC does this correctly.
Rather than introducing a new entry to the CallingConv enum, we mark the
call as vararg in AArch64ArmECCallLowering so that the lowering logic in
AArch64ISelLowering.cpp can recognise this case, perform the necessary
memcpy, and drop the x4/x5 arguments.
LLVM should additionally ensure that x0-x3 are mirrored to f0-f3 in
order to match the Windows x86-64 vararg ABI, but that change is left
for a follow-up patch.
Commit: 5595710093f7f8b9cdb0ff4f8d7400e58bde09b2
https://github.com/llvm/llvm-project/commit/5595710093f7f8b9cdb0ff4f8d7400e58bde09b2
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Lower/MultiImageFortran.h
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/EmitMIFGlobalCtors.cpp
M flang/test/Fir/basic-program.fir
M flang/test/Lower/MIF/coarray_allocation4.f90
M flang/test/Lower/MIF/coarray_allocation5.f90
Log Message:
-----------
[Flang][MIF] Allocation of NON-ALLOCATABLE SAVE coarray (#205847)
The goal of this PR is to add support for allocating NON-allocatable
coarrays that are not in the `Main` program.
All allocations will be performed in a function called
`__mif_save_coarrays_allocate`. If this function exists, then
LLVM::GlobalCtors is created (or modified).
The initialization of the MIF with `mif.init` is moved too in a
GlobalCtors with a priority of 0 to ensure that the initialization takes
place before any MIF allocations.
---------
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
Commit: 40f2fda52c4b3b110f38acded24521217473d106
https://github.com/llvm/llvm-project/commit/40f2fda52c4b3b110f38acded24521217473d106
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[lldb-dap] Migrate all DAP variables test. (#208215)
migrate TestDAP_variables and TestDAP_variables_children.
Commit: fff064e93d144a6499efcf091e1f226d144e514f
https://github.com/llvm/llvm-project/commit/fff064e93d144a6499efcf091e1f226d144e514f
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Interpreter/Interpreter.cpp
M clang/test/Interpreter/cxx20-modules.cppm
M clang/test/Interpreter/execute-pch.cpp
A clang/test/Interpreter/pch-pic-mismatch.cpp
A clang/test/Interpreter/pcm-pic-mismatch.cpp
Log Message:
-----------
[Clang][Interpreter] Enable PIC to avoid 32-bit relocation overflows (#201286)
In clang-repl, R_*_32 relocations are emitted as direct 32-bit
PC-relative references. A conventional static linker can resolve
references to external symbols through the GOT or copy relocations, but
clang-repl directly mmaps shared objects into memory, bypassing the
static linker.
As a result, these relocations may exceed their 32-bit range if a
referenced symbol is located more than 2 GB away from the JIT
allocation, which can occur on FreeBSD.
Enable PIC to force accesses to external data through the GOT, avoiding
the generation of direct 32-bit relocations that are subject to the 2 GB
addressing limit.
Commit: a624d9999cf1ac83aa1fe0820c9311de8106175e
https://github.com/llvm/llvm-project/commit/a624d9999cf1ac83aa1fe0820c9311de8106175e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/AllocAction.h
Log Message:
-----------
[orc-rt] Remove redundant [[nodiscard]] from runFinalizeActions. NFC. (#209163)
runFinalizeActions returns an Expected, which already carries a
nodiscard attribute.
Commit: 9325f22f1cf17a6f192519163dd449d684700d2a
https://github.com/llvm/llvm-project/commit/9325f22f1cf17a6f192519163dd449d684700d2a
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/cmake/modules/CMakeLists.txt
Log Message:
-----------
[MLIR] Normalize path separator in MLIRConfig.cmake (#208659)
Under Windows, the paths may contain `\` path separators.
`MLIR_TABLEGEN_EXE` is added into MLIRConfig.cmake where backslashes are
interpreted as escape characters. This results in syntax errors during
`find_package(MLIR)`.
Fix by using CMake-normalized paths (`/` separator under all platforms).
LLVM/Clang do not put their tablegen paths in their config files.
Commit: 1884c7565155b603ec3946718801f53b276876bb
https://github.com/llvm/llvm-project/commit/1884c7565155b603ec3946718801f53b276876bb
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-invalid.mlir
Log Message:
-----------
[mlir][tosa] Validate variable element types (#205873)
I changed the TOSA validation path so unsupported types report a normal
diagnostic instead of crashing.
Fixes #205710
Commit: 0f69d2804b9b2542fde2ecafbb23f1e8a8b48d86
https://github.com/llvm/llvm-project/commit/0f69d2804b9b2542fde2ecafbb23f1e8a8b48d86
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/include/__iterator/segmented_iterator.h
Log Message:
-----------
[libc++][NFC] Remove unused includes from <__iterator/segmented_iterator.h> (#209105)
Commit: d4c6c8623e9bf9aa75ad049f55423223228116b3
https://github.com/llvm/llvm-project/commit/d4c6c8623e9bf9aa75ad049f55423223228116b3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP] Support memory runtime alias checks
Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.
Fixes #201534
Reviewers: RKSimon, bababuck, hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/203631
Commit: 7f35300f0deb972606082122e4c7d76dda03203c
https://github.com/llvm/llvm-project/commit/7f35300f0deb972606082122e4c7d76dda03203c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Compiler.h
M orc-rt/include/orc-rt/Error.h
Log Message:
-----------
[orc-rt] Replace ORC_RT_NODISCARD with [[nodiscard]]. NFCI. (#209169)
The ORC runtime requires C++17, so we can use the C++17 [[nodiscard]]
attribute directly, rather than going through a macro.
Commit: 06c23c41ec0035246ad37afff416b5b02b9c7bcd
https://github.com/llvm/llvm-project/commit/06c23c41ec0035246ad37afff416b5b02b9c7bcd
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/ids-check.yml
M .github/workflows/libcxx-build-and-test.yaml
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/dwarf4-cross-cu-ranges.test
M bolt/test/X86/dwarf5-debug-names-cross-cu.s
M bolt/test/X86/indirect-goto.test
M bolt/test/X86/match-blocks-with-pseudo-probes-inline.test
M bolt/test/X86/pseudoprobe-decoding-inline.test
M bolt/test/X86/pseudoprobe-decoding-noinline.test
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/support/File.h
M clang-tools-extra/clang-doc/support/Utils.h
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.h
M clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantParenthesesCheck.cpp
M clang-tools-extra/clangd/index/remote/marshalling/Marshalling.cpp
M clang-tools-extra/clangd/index/remote/server/Server.cpp
A clang-tools-extra/clangd/test/remote-index/cross-platform-root.test
M clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
M clang-tools-extra/clangd/unittests/IndexActionTests.cpp
M clang-tools-extra/clangd/unittests/remote/MarshallingTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-auto-parameters.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-auto.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-lambdas.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-pointer-as-pointers.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-pointer-as-values.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-templates.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-transform-values.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-values.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/misplaced-const-cxx17.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/include/macro.h
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/subdir/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-macro-argument.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/redundant-parentheses.cpp
M clang/CMakeLists.txt
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/ASTNodeTraverser.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtCXX.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
A clang/include/clang/Basic/AtomicLineLogger.h
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/OpenCLOptions.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Basic/TokenKinds.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Driver/Job.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/include/clang/Sema/DeclSpec.h
M clang/include/clang/Sema/Scope.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/BasicValueFactory.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprClassification.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/StmtCXX.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
A clang/lib/Basic/AtomicLineLogger.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/Driver/Compilation.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/TokenConcatenation.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseInit.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.cpp
R clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractor.cpp
M clang/lib/Sema/CMakeLists.txt
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/IdentifierResolver.cpp
M clang/lib/Sema/Scope.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
A clang/lib/Sema/SemaExpand.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOpenCL.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaStmtAttr.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
M clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/test/AST/ByteCode/invalid.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/AST/ByteCode/typeid.cpp
A clang/test/AST/ast-dump-expansion-stmt.cpp
A clang/test/AST/ast-print-expansion-stmts.cpp
M clang/test/Analysis/ArrayBound/assumption-reporting.c
M clang/test/Analysis/Checkers/WebKit/binding-to-refptr.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-loop-init-opaque-value.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-safe-functions.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-wtf-containers.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
M clang/test/Analysis/Checkers/WebKit/ref-countable-default-arg-nullptr.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-call-arg.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.mm
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-const-v-muable.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-member.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Analysis/Checkers/WebKit/unretained-obj-arg.mm
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-bad-id.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-no-key.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-bad-id.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-empty.json
A clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-no-key.json
A clang/test/Analysis/Scalable/OperatorNewDelete/operator-new-delete.cpp
A clang/test/Analysis/Scalable/OperatorNewDelete/tu-summary-serialization.test
A clang/test/Analysis/Scalable/OperatorNewDelete/wpa-result-serialization.test
M clang/test/Analysis/bitwise-shift-common.c
A clang/test/Analysis/block-in-critical-section-raii.cpp
M clang/test/Analysis/constant-folding.c
M clang/test/Analysis/debug-lifetime-bound.cpp
A clang/test/Analysis/html_diagnostics/variable-popups-eol.c
M clang/test/Analysis/lifetime-bound.cpp
M clang/test/Analysis/malloc.c
A clang/test/Analysis/string-search-modeling.c
M clang/test/Analysis/string.c
A clang/test/Analysis/z3/z3-logicalexpr-eval.c
M clang/test/Analysis/z3/z3-unarysymexpr.c
M clang/test/CIR/CodeGen/array-init-loop-exprs.cpp
M clang/test/CIR/CodeGen/ctor-try-body.cpp
M clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
M clang/test/CIR/CodeGen/inherited-ctors.cpp
M clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
M clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
M clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CIR/IR/func.cir
M clang/test/CIR/IR/invalid-func.cir
M clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.stc/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3.cpp
M clang/test/CXX/dcl/dcl.fct/p17.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
M clang/test/CodeGen/AArch64/neon-2velem.c
M clang/test/CodeGen/AArch64/neon-extract.c
M clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
M clang/test/CodeGen/AArch64/neon-ldst-one.c
M clang/test/CodeGen/AArch64/neon-misc.c
M clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
M clang/test/CodeGen/AArch64/neon-vcmla.c
M clang/test/CodeGen/AArch64/neon/fused-multiply.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/strictfp-builtins.c
M clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
A clang/test/CodeGen/SystemZ/zos-ppa1-name.c
M clang/test/CodeGen/X86/strictfp_builtins.c
M clang/test/CodeGen/arm-neon-vst.c
M clang/test/CodeGen/arm64_vdupq_n_f64.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/builtin_float.c
M clang/test/CodeGen/builtin_float_strictfp.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/cx-complex-range-real.c
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/isfpclass.c
M clang/test/CodeGen/strictfp_builtins.c
M clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
A clang/test/CodeGenCXX/cxx2c-destructuring-expansion-stmt.cpp
A clang/test/CodeGenCXX/cxx2c-enumerating-expansion-statements.cpp
A clang/test/CodeGenCXX/cxx2c-expansion-stmts-control-flow.cpp
A clang/test/CodeGenCXX/cxx2c-expansion-stmts-mangling.cpp
A clang/test/CodeGenCXX/cxx2c-expansion-stmts-templates.cpp
A clang/test/CodeGenCXX/cxx2c-iterating-expansion-stmt.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/ms-mangle-requires.cpp
A clang/test/CodeGenCXX/msvc-global-delete-scalar-array-split.cpp
A clang/test/CodeGenCXX/msvc-global-delete-scope-no-dtor.cpp
A clang/test/CodeGenCXX/msvc-no-global-delete-forwarding.cpp
M clang/test/CodeGenCXX/msvc-vector-deleting-dtors-sized-delete.cpp
A clang/test/Driver/amdgpu-openmp-gpu-max-threads-per-block.c
M clang/test/Driver/hip-include-path.hip
A clang/test/Driver/offload-parallel-device-cc1.cu
M clang/test/Driver/opencl-libclc.cl
M clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
A clang/test/Driver/zos-ppa1-name.c
A clang/test/Frontend/openmp-warn-gpu-max-threads-per-block.c
M clang/test/Headers/amdgcn-openmp-device-math-complex.c
M clang/test/Headers/amdgcn-openmp-device-math-complex.cpp
M clang/test/Headers/hip-header.hip
M clang/test/Headers/nvptx_device_math_complex.c
M clang/test/Headers/nvptx_device_math_complex.cpp
M clang/test/Headers/openmp_device_math_isnan.cpp
M clang/test/Interpreter/cxx20-modules.cppm
M clang/test/Interpreter/emulated-tls.cpp
M clang/test/Interpreter/execute-pch.cpp
A clang/test/Interpreter/pch-pic-mismatch.cpp
A clang/test/Interpreter/pcm-pic-mismatch.cpp
A clang/test/Lexer/dollar-idents.cpp
A clang/test/Lexer/invalid-directive.cpp
M clang/test/Modules/glob-delete-with-virtual-dtor.cpp
M clang/test/Modules/msvc-vector-deleting-destructors.cpp
M clang/test/OpenMP/error_codegen.cpp
M clang/test/PCH/cxx1z-decomposition.cpp
M clang/test/PCH/cxx20-template-args.cpp
M clang/test/PCH/glob-delete-with-virtual-dtor.cpp
M clang/test/PCH/msvc-vector-deleting-destructors.cpp
M clang/test/Parser/c2x-auto.c
M clang/test/Parser/cxx1z-decomposition.cpp
A clang/test/Parser/cxx2c-expansion-statements-not-backported.cpp
A clang/test/Parser/cxx2c-expansion-statements.cpp
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init.c
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/constexpr-array-unknown-bound.cpp
M clang/test/SemaCXX/cxx2c-constexpr-placement-new.cpp
A clang/test/SemaCXX/cxx2c-expansion-statements-shadow.cpp
A clang/test/SemaCXX/cxx2c-expansion-stmts-control-flow.cpp
A clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
M clang/test/SemaCXX/static-data-member.cpp
M clang/test/SemaOpenCL/access-qualifier.cl
M clang/test/SemaOpenCL/fp64-fp16-options.cl
M clang/test/SemaOpenCL/storageclass.cl
M clang/test/SemaOpenCL/unsupported-image.cl
M clang/test/SemaTemplate/GH176155.cpp
M clang/test/SemaTemplate/overload-candidates.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
A clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/Basic/CMakeLists.txt
M clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/CallOpTest.cpp
M clang/unittests/Lex/PPMemoryAllocationsTest.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
M clang/www/cxx_status.html
M compiler-rt/lib/builtins/hexagon/dffma.S
M compiler-rt/test/asan/TestCases/Posix/new_array_cookie_with_new_from_class.cpp
M compiler-rt/test/builtins/Unit/compiler_rt_scalbn_test.c
M compiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c
A compiler-rt/test/builtins/Unit/hexagon_fmadf5_test.c
M compiler-rt/test/lit.common.cfg.py
M compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-warnings.ll
A compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/make_signed.h
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/wrappers.h
A compiler-rt/test/ubsan/TestCases/Integer/suppressions-nested-calls.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Lower/MultiImageFortran.h
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Dialect/FIRTypes.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/EmitMIFGlobalCtors.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Driver/bbc-implicit-use-module.f90
M flang/test/Fir/basic-program.fir
A flang/test/Fir/derived-type-aliases.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M flang/test/Lower/MIF/coarray_allocation4.f90
M flang/test/Lower/MIF/coarray_allocation5.f90
M flang/test/Lower/MIF/image_index.f90
M flang/test/Lower/OpenACC/acc-bounds.f90
A flang/test/Lower/OpenACC/acc-loop-nested-in-do-concurrent.f90
M flang/test/Lower/OpenMP/defaultmap.f90
A flang/test/Lower/OpenMP/unroll-partial01.f90
A flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
A flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
A flang/test/Semantics/OpenMP/metadirective-loop-sequence.f90
A flang/test/Semantics/call48.f90
A libc/docs/arch_support.md
R libc/docs/arch_support.rst
A libc/docs/build_and_test.md
R libc/docs/build_and_test.rst
A libc/docs/build_concepts.md
R libc/docs/build_concepts.rst
A libc/docs/compiler_support.md
R libc/docs/compiler_support.rst
M libc/docs/conf.py
A libc/docs/contributing.md
R libc/docs/contributing.rst
A libc/docs/dev/building_docs.md
R libc/docs/dev/building_docs.rst
A libc/docs/dev/builtin_compatibility.md
R libc/docs/dev/builtin_compatibility.rst
A libc/docs/dev/code_style.md
R libc/docs/dev/code_style.rst
A libc/docs/dev/config_options.md
R libc/docs/dev/config_options.rst
A libc/docs/dev/date_and_time.md
A libc/docs/dev/entrypoints.md
R libc/docs/dev/entrypoints.rst
A libc/docs/dev/fuzzing.md
R libc/docs/dev/fuzzing.rst
A libc/docs/dev/header_generation.md
R libc/docs/dev/header_generation.rst
A libc/docs/dev/implementation_standard.md
R libc/docs/dev/implementation_standard.rst
A libc/docs/dev/implementing_a_function.md
R libc/docs/dev/implementing_a_function.rst
A libc/docs/dev/index.md
R libc/docs/dev/index.rst
A libc/docs/dev/modular_format.md
R libc/docs/dev/modular_format.rst
A libc/docs/dev/printf_behavior.md
R libc/docs/dev/printf_behavior.rst
A libc/docs/dev/source_tree_layout.md
R libc/docs/dev/source_tree_layout.rst
A libc/docs/dev/syscall_wrapper_refactor.md
R libc/docs/dev/syscall_wrapper_refactor.rst
A libc/docs/dev/undefined_behavior.md
R libc/docs/dev/undefined_behavior.rst
A libc/docs/full_cross_build.md
R libc/docs/full_cross_build.rst
A libc/docs/full_host_build.md
R libc/docs/full_host_build.rst
A libc/docs/getting_started.md
R libc/docs/getting_started.rst
A libc/docs/hand_in_hand.md
R libc/docs/hand_in_hand.rst
A libc/docs/index.md
R libc/docs/index.rst
A libc/docs/overlay_mode.md
R libc/docs/overlay_mode.rst
A libc/docs/platform_support.md
R libc/docs/platform_support.rst
A libc/docs/porting.md
R libc/docs/porting.rst
A libc/docs/talks.md
R libc/docs/talks.rst
M libc/src/__support/CPP/expected.h
M libc/src/time/CMakeLists.txt
M libc/src/time/time_constants.h
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/test/src/__support/CPP/CMakeLists.txt
A libc/test/src/__support/CPP/expected_test.cpp
M libc/test/src/time/CMakeLists.txt
M libc/test/src/time/gmtime_test.cpp
M libcxx/CREDITS.TXT
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__iterator/segmented_iterator.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/src/atomic.cpp
M libcxx/src/include/overridable_function.h
M libcxx/src/support/runtime/exception_pointer_msvc.ipp
A libcxx/test/benchmarks/algorithms/sorting/is_heap.bench.cpp
M libcxx/test/benchmarks/containers/string.bench.cpp
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.reverse/pstl.reverse_copy.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
M libcxx/test/support/min_allocator.h
M libcxx/utils/ci/docker/docker-compose.yml
M libcxx/utils/ci/docker/linux-builder-base.dockerfile
M libcxx/utils/ci/images/libcxx_runners.txt
M libcxxabi/include/cxxabi.h
M libcxxabi/src/abort_message.h
M libcxxabi/src/cxa_aux_runtime.cpp
M libcxxabi/src/cxa_default_handlers.cpp
M libcxxabi/src/cxa_exception.cpp
M libcxxabi/src/cxa_handlers.cpp
M libcxxabi/src/cxa_handlers.h
M libcxxabi/src/cxa_personality.cpp
M libcxxabi/src/cxa_vector.cpp
M libcxxabi/src/cxa_virtual.cpp
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SPARCV9.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/RelocScan.h
M lld/ELF/Relocations.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
M lld/docs/NewLLD.rst
M lld/docs/ReleaseNotes.rst
M lld/include/lld/Common/BPSectionOrdererBase.inc
M lld/test/ELF/aarch64-reloc-pauth.s
M lld/test/ELF/bp-section-orderer.s
M lld/test/ELF/emit-relocs-discard-locals.s
A lld/test/ELF/gnu-build-attributes.s
M lld/test/ELF/i386-tls-ie-shared.s
A lld/test/ELF/linkerscript/tbss-addr-expr.s
M lld/test/ELF/mips-tls-64-pic-local-variable.s
M lld/test/ELF/pack-dyn-relocs-relr-loop.s
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/retain-und.s
M lld/test/ELF/x86-64-tls-gd-local.s
M lld/test/MachO/bp-section-orderer-errs.s
M lld/unittests/AsLibELF/CMakeLists.txt
A lld/unittests/AsLibELF/OutputStream.cpp
M lldb/docs/python_extensions.md
M lldb/docs/resources/build.md
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/Opcode.h
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
M lldb/include/lldb/Host/JSONTransport.h
M lldb/include/lldb/Protocol/MCP/Client.h
M lldb/include/lldb/Protocol/MCP/Protocol.h
M lldb/include/lldb/Protocol/MCP/Server.h
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/include/lldb/Utility/Policy.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/Commands/CommandObjectRegister.cpp
M lldb/source/Core/DumpRegisterValue.cpp
M lldb/source/DataFormatters/TypeCategoryMap.cpp
M lldb/source/Host/freebsd/Host.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Protocol/MCP/Client.cpp
M lldb/source/Protocol/MCP/Protocol.cpp
M lldb/source/Protocol/MCP/Server.cpp
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/source/Utility/Policy.cpp
A lldb/test/API/commands/command/script/import/import-error/Makefile
A lldb/test/API/commands/command/script/import/import-error/TestImportError.py
A lldb/test/API/commands/command/script/import/import-error/fail_importerror.py
A lldb/test/API/commands/command/script/import/import-error/fail_valueerror.py
R lldb/test/API/commands/command/script/import/rdar-12586188/Makefile
R lldb/test/API/commands/command/script/import/rdar-12586188/TestRdar12586188.py
R lldb/test/API/commands/command/script/import/rdar-12586188/fail12586188.py
R lldb/test/API/commands/command/script/import/rdar-12586188/fail212586188.py
A lldb/test/API/commands/expression/int128/Test128BitsInteger.py
A lldb/test/API/commands/expression/int128/main.c
R lldb/test/API/commands/expression/rdar42038760/TestScalarURem.py
R lldb/test/API/commands/expression/rdar42038760/main.c
R lldb/test/API/commands/expression/rdar44436068/Test128BitsInteger.py
R lldb/test/API/commands/expression/rdar44436068/main.c
A lldb/test/API/commands/expression/urem-sign/TestScalarURem.py
A lldb/test/API/commands/expression/urem-sign/main.c
A lldb/test/API/driver/longpath/Makefile
A lldb/test/API/driver/longpath/TestLongPathDriver.py
A lldb/test/API/driver/longpath/main.c
R lldb/test/API/functionalities/data-formatter/summary-string-onfail/Test-rdar-9974002.py
A lldb/test/API/functionalities/data-formatter/summary-string-onfail/TestSummaryStringOnFail.py
M lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
A lldb/test/API/functionalities/longpath/Makefile
A lldb/test/API/functionalities/longpath/TestLongPath.py
A lldb/test/API/functionalities/longpath/main.c
M lldb/test/API/functionalities/statusline/TestStatusline.py
A lldb/test/API/functionalities/statusline/statusline_flood.py
M lldb/test/API/lang/c/blocks/TestBlocks.py
M lldb/test/API/lang/c/blocks/main.c
M lldb/test/API/lang/c/unions/TestUnionMembers.py
M lldb/test/API/lang/c/unions/main.c
A lldb/test/API/lang/cpp/builtin_types/char/Makefile
A lldb/test/API/lang/cpp/builtin_types/char/TestCharTypes.py
A lldb/test/API/lang/cpp/builtin_types/char/main.cpp
A lldb/test/API/lang/cpp/builtin_types/long_int/Makefile
A lldb/test/API/lang/cpp/builtin_types/long_int/TestLongIntTypes.py
A lldb/test/API/lang/cpp/builtin_types/long_int/main.cpp
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/Makefile
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/TestRecursiveTypesFuncPtrs.py
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/main.cpp
A lldb/test/API/lang/cpp/recursive_types/function-ptrs/recursive_types.cpp
A lldb/test/API/lang/objc/coalesced-cf-types/Makefile
A lldb/test/API/lang/objc/coalesced-cf-types/TestCoalescedCFTypes.py
A lldb/test/API/lang/objc/coalesced-cf-types/main.m
A lldb/test/API/lang/objc/dynamic-type-children/Makefile
A lldb/test/API/lang/objc/dynamic-type-children/TestDynamicTypeChildren.py
A lldb/test/API/lang/objc/dynamic-type-children/main.m
R lldb/test/API/lang/objc/rdar-10967107/Makefile
R lldb/test/API/lang/objc/rdar-10967107/TestRdar10967107.py
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M lldb/test/API/linux/aarch64/permission_overlay/TestAArch64LinuxPOE.py
A lldb/test/API/tools/lldb-dap/longpath/Makefile
A lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
A lldb/test/API/tools/lldb-dap/longpath/main.c
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
A lldb/test/Shell/Commands/command-register-read-alignment.test
M lldb/tools/lldb-mcp/CMakeLists.txt
A lldb/tools/lldb-mcp/Multiplexer.cpp
A lldb/tools/lldb-mcp/Multiplexer.h
M lldb/tools/lldb-mcp/lldb-mcp.cpp
M lldb/unittests/Disassembler/CMakeLists.txt
A lldb/unittests/Disassembler/x86/TestGetOpcodeOversized.cpp
M lldb/unittests/Host/JSONTransportTest.cpp
M lldb/unittests/Protocol/MCPServerInfoTest.cpp
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
M lldb/unittests/tools/CMakeLists.txt
A lldb/unittests/tools/lldb-mcp/CMakeLists.txt
A lldb/unittests/tools/lldb-mcp/MultiplexerTest.cpp
M llvm/CMakeLists.txt
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/cmake/modules/FindDIASDK.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/GettingStarted.md
M llvm/docs/LangRef.md
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
A llvm/include/llvm/ADT/Eytzinger.h
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/StackMaps.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/MC/ConstantPools.h
A llvm/include/llvm/TargetParser/TripleName.def
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/include/module.modulemap
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVIRReader.cpp
M llvm/lib/Debuginfod/BuildIDFetcher.cpp
M llvm/lib/HTTP/HTTPClient.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
M llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
M llvm/lib/Target/RISCV/RISCVMacroFusion.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Analysis/CostModel/AMDGPU/abs.ll
M llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
M llvm/test/Analysis/CostModel/AMDGPU/addrspacecast.ll
M llvm/test/Analysis/CostModel/AMDGPU/aggregates.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-sminmax.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-ssat.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-uminmax.ll
M llvm/test/Analysis/CostModel/AMDGPU/arith-usat.ll
M llvm/test/Analysis/CostModel/AMDGPU/arithmetic_fence.ll
M llvm/test/Analysis/CostModel/AMDGPU/bit-ops.ll
M llvm/test/Analysis/CostModel/AMDGPU/canonicalize.ll
M llvm/test/Analysis/CostModel/AMDGPU/cast.ll
M llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
M llvm/test/Analysis/CostModel/AMDGPU/div.ll
M llvm/test/Analysis/CostModel/AMDGPU/exp.ll
M llvm/test/Analysis/CostModel/AMDGPU/exp10.ll
M llvm/test/Analysis/CostModel/AMDGPU/exp2.ll
M llvm/test/Analysis/CostModel/AMDGPU/extractelement.ll
M llvm/test/Analysis/CostModel/AMDGPU/fabs.ll
M llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
M llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
M llvm/test/Analysis/CostModel/AMDGPU/fma.ll
M llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
M llvm/test/Analysis/CostModel/AMDGPU/fmuladd.ll
M llvm/test/Analysis/CostModel/AMDGPU/fneg.ll
M llvm/test/Analysis/CostModel/AMDGPU/fptosi.ll
M llvm/test/Analysis/CostModel/AMDGPU/fptoui.ll
M llvm/test/Analysis/CostModel/AMDGPU/frexp.ll
M llvm/test/Analysis/CostModel/AMDGPU/fround.ll
M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
M llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
M llvm/test/Analysis/CostModel/AMDGPU/gep.ll
M llvm/test/Analysis/CostModel/AMDGPU/insertelement.ll
M llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
M llvm/test/Analysis/CostModel/AMDGPU/ldexp.ll
M llvm/test/Analysis/CostModel/AMDGPU/load-to-trunc.ll
M llvm/test/Analysis/CostModel/AMDGPU/load.ll
M llvm/test/Analysis/CostModel/AMDGPU/log.ll
M llvm/test/Analysis/CostModel/AMDGPU/log10.ll
M llvm/test/Analysis/CostModel/AMDGPU/log2.ll
M llvm/test/Analysis/CostModel/AMDGPU/logicalop.ll
M llvm/test/Analysis/CostModel/AMDGPU/maximum.ll
M llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/maxnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/mul.ll
M llvm/test/Analysis/CostModel/AMDGPU/ptrmask.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-and.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-or.ll
M llvm/test/Analysis/CostModel/AMDGPU/rem.ll
M llvm/test/Analysis/CostModel/AMDGPU/shifts.ll
M llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
M llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
M llvm/test/Analysis/CostModel/AMDGPU/sqrt.ll
M llvm/test/Analysis/CostModel/AMDGPU/store.ll
A llvm/test/Analysis/LoopAccessAnalysis/wide-pointer-index-distance.ll
A llvm/test/Analysis/ScalarEvolution/ptrtoint-special-pointers.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/inline-asm.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/uses-value-from-cycle.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-subgraph.ll
A llvm/test/Assembler/print-formatted.ll
M llvm/test/Bitcode/DIModule-fortran-external-module.ll
A llvm/test/Bitcode/upgrade-cu-static-locals.ll
A llvm/test/Bitcode/upgrade-cu-static-locals.ll.bc
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
M llvm/test/CodeGen/AArch64/framelayout-fpr128-csr.ll
M llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
A llvm/test/CodeGen/AArch64/get-active-lane-mask-extract-nosve.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
A llvm/test/CodeGen/AArch64/neg-sign-masked-and.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
A llvm/test/CodeGen/AArch64/preserve-all-large-csr.ll
M llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/verify-imm.mir
M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
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M llvm/test/CodeGen/AMDGPU/add_shl.ll
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M llvm/test/CodeGen/AMDGPU/add_u64.ll
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M llvm/test/CodeGen/AMDGPU/amdgpu-nsa-threshold.ll
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M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
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M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups_error_check.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/attr-unparseable.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
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M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
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M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
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M llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
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M llvm/test/CodeGen/AMDGPU/basic-call-return.ll
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M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
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M llvm/test/CodeGen/AMDGPU/bf16-ops.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
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M llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
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M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
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M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
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M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
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M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
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M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
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M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
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M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
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M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
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M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
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M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
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M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
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M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
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M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
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M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
M llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
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M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
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M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gcn-reg-pressure-true16-integer-overflow.mir
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gds-atomic.ll
M llvm/test/CodeGen/AMDGPU/gds-unsupported.ll
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll
M llvm/test/CodeGen/AMDGPU/gfx10plus-wavefront-sgpr-count.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/gfx942-hazards.mir
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-func.ll
M llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll
M llvm/test/CodeGen/AMDGPU/hsa.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-attr.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
A llvm/test/CodeGen/AMDGPU/lower-kernargs-lds-ptr.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-invalid-signature.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-kernel-arguments.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/target-id-xnack-always-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-wcg-attributes.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/ARM/estimate-size-copy.mir
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
M llvm/test/CodeGen/BPF/BTF/static-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var.ll
M llvm/test/CodeGen/BPF/dwarfdump.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-mult-normalize-second-operand.mir
A llvm/test/CodeGen/Hexagon/pr196966.ll
A llvm/test/CodeGen/Hexagon/pr207422.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/setcc-redundant.ll
M llvm/test/CodeGen/Mips/cconv/vector.ll
M llvm/test/CodeGen/Mips/cmov.ll
A llvm/test/CodeGen/NVPTX/convert-fp-i128.ll
M llvm/test/CodeGen/NVPTX/i1-select.ll
M llvm/test/CodeGen/PowerPC/pr24546.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
M llvm/test/CodeGen/RISCV/jump-is-expensive.ll
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/rvp-srl-bitcast-bv.ll
A llvm/test/CodeGen/RISCV/rvp-widening-convert.ll
M llvm/test/CodeGen/RISCV/rvp-zip.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
A llvm/test/CodeGen/RISCV/stack-coloring-large-stack.ll
A llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir
M llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/i128-switch-condition-type.ll
M llvm/test/CodeGen/SPIRV/global-var-intrinsic.ll
A llvm/test/CodeGen/SPIRV/pointers/fun-ptr-as-data-load-store.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-ptr-to-itself.ll
A llvm/test/CodeGen/SPIRV/switch-odd-width-condition.ll
M llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll
M llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll
M llvm/test/CodeGen/SPIRV/transcoding/global_block.ll
M llvm/test/CodeGen/SystemZ/zos-ppa1.ll
M llvm/test/CodeGen/WebAssembly/simd-arith.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/WebAssembly/vector-reduce.ll
M llvm/test/CodeGen/X86/dbg-distringtype-uint.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
M llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
M llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
M llvm/test/CodeGen/X86/isel-select-cmov.ll
M llvm/test/CodeGen/X86/select-constant-xor.ll
M llvm/test/CodeGen/X86/select-mmx.ll
A llvm/test/CodeGen/X86/select-of-load-poison.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/DebugInfo/COFF/fortran-basic.ll
M llvm/test/DebugInfo/COFF/fortran-contained-proc.ll
M llvm/test/DebugInfo/COFF/global_visibility.ll
M llvm/test/DebugInfo/COFF/type-quals.ll
M llvm/test/DebugInfo/Generic/2009-11-05-DeadGlobalVariable.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
M llvm/test/DebugInfo/Generic/global-var-in-abstract-lexical-block.ll
M llvm/test/DebugInfo/Generic/inlined-static-var.ll
A llvm/test/DebugInfo/Generic/verifier-invalid-dicompileunit.ll
M llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll
M llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
M llvm/test/DebugInfo/X86/DW_AT_specification.ll
M llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll
M llvm/test/DebugInfo/X86/dimodule-external-fortran.ll
M llvm/test/DebugInfo/X86/distringtype.ll
M llvm/test/DebugInfo/X86/global-sra-struct-fit-segment.ll
M llvm/test/DebugInfo/X86/global-sra-struct-part-overlap-segment.ll
M llvm/test/DebugInfo/X86/gnu-public-names.ll
A llvm/test/DebugInfo/X86/lexical-block-static-var.ll
M llvm/test/DebugInfo/X86/namelist1.ll
M llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
M llvm/test/DebugInfo/duplicate_dbgvalue.ll
M llvm/test/Instrumentation/InstrProfiling/debug-info-correlate-bitmap.ll
M llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
M llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
M llvm/test/MC/RISCV/rv32-only-csr-names.s
A llvm/test/MC/RISCV/xsmtvdotii-invalid.s
A llvm/test/MC/RISCV/xsmtvdotii-valid.s
M llvm/test/Transforms/AggressiveInstCombine/X86/lower-table-based-log2-basics.ll
M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization-preserve-name.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-simplify-cfg-CAS-block.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-cmpxchg-flat-maybe-private.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-load.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-store.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll
M llvm/test/Transforms/Attributor/AMDGPU/do-not-replace-addrspacecast-with-constantpointernull.ll
M llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/address_space_info.ll
M llvm/test/Transforms/Attributor/nofpclass-select.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/addressing-modes.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll
M llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll
M llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll
M llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/convergent-call.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/memrealtime.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem-inf.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/missing-analysis.ll
M llvm/test/Transforms/ExpandIRInsts/AMDGPU/pass-parameters.ll
A llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/GVN/ptrtoaddr.ll
M llvm/test/Transforms/GlobalOpt/address_space_initializer.ll
M llvm/test/Transforms/GlobalOpt/shrink-global-to-bool.ll
M llvm/test/Transforms/HipStdPar/accelerator-code-selection.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-0.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-1.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-2.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-count.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-type.ll
M llvm/test/Transforms/HipStdPar/global-var-indirection.ll
M llvm/test/Transforms/HipStdPar/global-var.ll
M llvm/test/Transforms/HipStdPar/unsupported-asm.ll
M llvm/test/Transforms/HipStdPar/unsupported-builtins.ll
M llvm/test/Transforms/HipStdPar/unsupported-thread-local-direct-use.ll
M llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll
A llvm/test/Transforms/IndVarSimplify/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/IndVarSimplify/AMDGPU/no-widen-to-i64.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/address-space-id-funcs.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/assumed-addrspace.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/basic.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/builtin-assumed-addrspace.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/debug-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/icmp.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-address-space.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-addrspacecast.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-getelementptr.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/insert-pos-assert.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/intrinsics.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/is.constant.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue110433.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue53665.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/masked-load-store.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/mem-intrinsics.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/multiple-uses-of-val.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/no-flat-addrspace.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/phi-poison.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/prefetch.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/preserving-debugloc-addrspacecast.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/ptrmask.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/redundant-addrspacecast.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/select.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/self-phi.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/store-pointer-to-self.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/unreachable-code-assert.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/volatile.ll
M llvm/test/Transforms/InferFunctionAttrs/enable-builtin.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument-cost.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-only-one-live-use.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-argument-i64.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-array-ptr-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-indirect-call-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-ptr-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-struct-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-stack-vector-ptr-argument.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-vecbonus.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-atomicrmw-md-preserve.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-denormal-fp-math.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-hint.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-sram-ecc.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-xnack.ll
M llvm/test/Transforms/Inline/AMDGPU/load-intrinsics.ll
M llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
M llvm/test/Transforms/InstCombine/AMDGPU/addrspacecast.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics-gfx8.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-simplify-image-buffer-stores.ll
M llvm/test/Transforms/InstCombine/AMDGPU/canonicalize-add-to-gep.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmed3-fpext-fold.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
M llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
M llvm/test/Transforms/InstCombine/AMDGPU/issue68120.ll
M llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll
M llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll
M llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll
M llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
M llvm/test/Transforms/InstCombine/AMDGPU/sendmsg-m0-poison.ll
M llvm/test/Transforms/InstCombine/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll
M llvm/test/Transforms/InstCombine/AMDGPU/tan.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll
M llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstCombine/exp2-1.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/fadd.ll
M llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
M llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
M llvm/test/Transforms/InstCombine/freeze-fp-ops.ll
M llvm/test/Transforms/InstCombine/freeze-phi.ll
M llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll
M llvm/test/Transforms/InstCombine/is_fpclass.ll
M llvm/test/Transforms/InstCombine/pow-1.ll
M llvm/test/Transforms/InstCombine/pr80941.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
M llvm/test/Transforms/InstSimplify/canonicalize.ll
M llvm/test/Transforms/JumpThreading/divergent-target-test.ll
M llvm/test/Transforms/LICM/AMDGPU/bitcast.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/addrspace-7.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll
M llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-crash.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/cse-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/is_fpclass.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
A llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
M llvm/test/Transforms/LoopVectorize/pr125278.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/pr38697.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/replace-first-order-recurrence-by-versioned-iv.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/scev-exit-phi-invalidation.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
A llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vplan-native-path-inner-loop-with-runtime-checks.ll
M llvm/test/Transforms/MemCpyOpt/no-libcalls.ll
M llvm/test/Transforms/OpenMP/custom_state_machines.ll
M llvm/test/Transforms/OpenMP/custom_state_machines_pre_lto.ll
M llvm/test/Transforms/OpenMP/heap-to-shared-missing-declarations.ll
M llvm/test/Transforms/OpenMP/spmdization.ll
M llvm/test/Transforms/OpenMP/spmdization_indirect.ll
M llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll
M llvm/test/Transforms/PhaseOrdering/varargs.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
Log Message:
-----------
Merge branch 'main' into users/kovdan01/ptrauth-module-flags-mismatch
Commit: dd686bc09f68c4cd71a73f4fda15e3096cf2e120
https://github.com/llvm/llvm-project/commit/dd686bc09f68c4cd71a73f4fda15e3096cf2e120
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/CodeGen/AArch64/elf-pauthabi.c
M clang/test/CodeGen/ptrauth-module-flags.c
M llvm/test/CodeGen/AArch64/ptrauth-elf-got-function-symbols.ll
Log Message:
-----------
Test enhancements
Compare: https://github.com/llvm/llvm-project/compare/00fa7ea2a98d...dd686bc09f68
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