[all-commits] [llvm/llvm-project] b719e2: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Mon Jul 13 06:11:35 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b719e2e27ce121bec3afcf96f4806c0592ce95a1
      https://github.com/llvm/llvm-project/commit/b719e2e27ce121bec3afcf96f4806c0592ce95a1
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/idot2-test.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4-test.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
    M llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll
    M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
    M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
    M llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
    M llvm/test/CodeGen/AMDGPU/image-schedule.ll
    M llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
    M llvm/test/CodeGen/AMDGPU/imm.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/immv216.ll
    M llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
    M llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
    M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
    M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
    M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
    M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
    M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
    M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir
    M llvm/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
    M llvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll
    M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir
    M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
    M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-large.ll
    M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-leaf.ll
    M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-use-inactive.ll
    M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-sgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/inline-attr.ll
    M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
    M llvm/test/CodeGen/AMDGPU/inline-maxbb.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-16-fake16.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-16-true16.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-16.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll
    M llvm/test/CodeGen/AMDGPU/insert-branch-w32.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-attr.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-parse.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
    M llvm/test/CodeGen/AMDGPU/insert-handle-flat-vmem-ds.mir
    M llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-fence-soft.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-hang.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
    M llvm/test/CodeGen/AMDGPU/insert_subreg.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
    M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
    M llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
    M llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
    M llvm/test/CodeGen/AMDGPU/inst-prefetch-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
    M llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/internalize.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (16) (#209119)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> 
to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), 
dropping the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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