[all-commits] [llvm/llvm-project] da0045: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Mon Jul 13 06:10:44 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: da0045a12dbc6cc5b07534ca9ddcceaef49f05de
      https://github.com/llvm/llvm-project/commit/da0045a12dbc6cc5b07534ca9ddcceaef49f05de
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/global-constant.ll
    M llvm/test/CodeGen/AMDGPU/global-directive.ll
    M llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
    M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
    M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
    M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
    M llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll
    M llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir
    M llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir
    M llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir
    M llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
    M llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
    M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
    M llvm/test/CodeGen/AMDGPU/group-image-instructions.ll
    M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
    M llvm/test/CodeGen/AMDGPU/gv-offset-folding.ll
    M llvm/test/CodeGen/AMDGPU/gws-hazards.mir
    M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
    M llvm/test/CodeGen/AMDGPU/half-alloca-promotion.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/hard-clause-limit-attr.mir
    M llvm/test/CodeGen/AMDGPU/hard-clause-limit.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-load-monitor.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses.mir
    M llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
    M llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
    M llvm/test/CodeGen/AMDGPU/hazard-getreg-waitalu.mir
    M llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir
    M llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
    M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
    M llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
    M llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
    M llvm/test/CodeGen/AMDGPU/hazard-pseudo-machineinstrs.mir
    M llvm/test/CodeGen/AMDGPU/hazard-recognizer-meta-insts.mir
    M llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
    M llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/hazard-shift64.mir
    M llvm/test/CodeGen/AMDGPU/hazard.mir
    M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
    M llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
    M llvm/test/CodeGen/AMDGPU/hsa-func-align.ll
    M llvm/test/CodeGen/AMDGPU/hsa-globals.ll
    M llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v4.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-asan.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-uniform-workgroup-size-v5.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-wavefrontsize.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-workgroup-processor-mode-v5.ll
    M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
    M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
    M llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
    M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
    M llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
    M llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
    M llvm/test/CodeGen/AMDGPU/i8-extract-cost-comparison.ll
    M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
    M llvm/test/CodeGen/AMDGPU/icmp64.ll
    M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (15) (#209118)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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