[all-commits] [llvm/llvm-project] 3a6f32: [AArch64][SVE] Support lowering masked loads of <4...

[Shanzhi Chen via All-commits]

  Branch: refs/heads/users/chenshanzhi/fix-bf16-masked-store
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a6f32e806aef5f7a9770b4cd9cfc0700e04e684
      https://github.com/llvm/llvm-project/commit/3a6f32e806aef5f7a9770b4cd9cfc0700e04e684
  Author: Shanzhi Chen <chenshanzhi at huawei.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
    M llvm/test/CodeGen/AArch64/sve2p1-vector-shuffles.ll

  Log Message:
  -----------
  [AArch64][SVE] Support lowering masked loads of <4 x bf16> and <8 x bf16>

Add support for lowering masked loads of <4 x bf16> and <8 x bf16> when
target features contain "+sve".



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