[all-commits] [llvm/llvm-project] 6c009f: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Mon Jul 13 04:25:13 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c009ff4b39ec2a0233c40c87f8f3709e9dc2eff
      https://github.com/llvm/llvm-project/commit/6c009ff4b39ec2a0233c40c87f8f3709e9dc2eff
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
    M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmin3.ll
    M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
    M llvm/test/CodeGen/AMDGPU/fminimum.ll
    M llvm/test/CodeGen/AMDGPU/fminimum3.ll
    M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/fminnum.f64.ll
    M llvm/test/CodeGen/AMDGPU/fminnum.ll
    M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
    M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
    M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmul.ll
    M llvm/test/CodeGen/AMDGPU/fmul64.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
    M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg.ll
    M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
    M llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
    M llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
    M llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
    M llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
    M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-pk64.mir
    M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AMDGPU/fold-literal-multiple-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
    M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
    M llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index-agpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
    M llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
    M llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
    M llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
    M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
    M llvm/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
    M llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
    M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
    M llvm/test/CodeGen/AMDGPU/force-wait-after-always-gds.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
    M llvm/test/CodeGen/AMDGPU/fp-classify.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
    M llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp32_to_bf16.ll
    M llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (13) (#208897)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)

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