[all-commits] [llvm/llvm-project] cec7cf: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Mon Jul 13 01:52:18 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cec7cf4c3dd71068495245111553e4fba3d35c5e
      https://github.com/llvm/llvm-project/commit/cec7cf4c3dd71068495245111553e4fba3d35c5e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
    M llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir
    M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
    M llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll
    M llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll
    M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
    M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
    M llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
    M llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
    M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.ll
    M llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir
    M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
    M llvm/test/CodeGen/AMDGPU/bypass-div.ll
    M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-c-function.ll
    M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
    M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
    M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
    M llvm/test/CodeGen/AMDGPU/call-return-types.ll
    M llvm/test/CodeGen/AMDGPU/call-skip.ll
    M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/callbr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/callbr.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/cc-entry.ll
    M llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
    M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
    M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/chain-node-divergence-update-crash-issue-173885.ll
    M llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
    M llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll
    M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
    M llvm/test/CodeGen/AMDGPU/clamp.ll
    M llvm/test/CodeGen/AMDGPU/clmul.ll
    M llvm/test/CodeGen/AMDGPU/cluster-dims.ll
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
    M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
    M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
    M llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll
    M llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
    M llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
    M llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
    M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
    M llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
    M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
    M llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
    M llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
    M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null-vector.ll
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
    M llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
    M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
    M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (9) (#208893)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)

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