[all-commits] [llvm/llvm-project] c09d9a: [LSR] VScale doesn't occupy a register if it's a l...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c09d9a4d03a9211844e146b03ec41f957c74c4b7
      https://github.com/llvm/llvm-project/commit/c09d9a4d03a9211844e146b03ec41f957c74c4b7
  Author: John Brawn <john.brawn at arm.com>
  Date:   2026-07-09 (Thu, 09 Jul 2026)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll

  Log Message:
  -----------
  [LSR] VScale doesn't occupy a register if it's a legal offset (#206754)

When we have an AddRec where the step value is n*vscale this value
doesn't occupy a register if the target has an add instruction where
this value is a legal offset.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications