[all-commits] [llvm/llvm-project] 9623ae: [clang][bytecode] Add `PtrView` for non-tracking p...
Ryotaro Kasuga via All-commits
all-commits at lists.llvm.org
Sun Jun 14 23:08:26 PDT 2026
Branch: refs/heads/users/kasuga-fj/da-add-test-addrec-wrap-gcdmiv
Home: https://github.com/llvm/llvm-project
Commit: 9623ae8878b1d2d7ff39f9ce5c30e8bf82dd1896
https://github.com/llvm/llvm-project/commit/9623ae8878b1d2d7ff39f9ce5c30e8bf82dd1896
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Add `PtrView` for non-tracking pointers (#184129)
Currently, when creating a `Pointer` (of block type, which I will assume
here), the pointer will add itself (via its address) to its block's
pointer list. This way, a block always knows what pointers point to it.
That's important so we can handle the case when a block (which was e.g.
created for a local variable) is destroyed and we now need to update its
pointers.
However, since always do this for all `Pointer` instances, it creates a
weird performance problem where we do this dance all the time for no
reason, e.g. consider `Pointer::stripBaseCasts()`:
https://github.com/llvm/llvm-project/blob/88693c49d9ac58a33af5978d31f6c70fe1d5b45b/clang/lib/AST/ByteCode/Pointer.h#L778-L783
This will add and remove the newly created pointer from the block's
pointer list every iteration. Other offenders are `Pointer::toRValue()`,
`EvaluationResult::checkFullyInitialized()` or
`Pointer::computeOffsetForComparison()`.
This commit introduces a `PtrView` struct, which is like a
`BlockPointer`, but without the prev/next next links to other `Pointer`s
in the block's pointer list. It also moves a lot of the accessors from
`Pointer` to `PtrView` (e.g. `isRoot()` or `getFieldDesc()`, etc.).
compile-time-tracker:
https://llvm-compile-time-tracker.com/compare.php?from=4716dc8c51719cbcc82928cd00e41a29e5b9adff&to=28d69d4ec16e77370938675826b07752e108eede&stat=instructions:u
Commit: 2b4e89bc254dab3f18b59cd275519d256267b88e
https://github.com/llvm/llvm-project/commit/2b4e89bc254dab3f18b59cd275519d256267b88e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(permi(x,imm0),permi(y,imm1)) -> vpermv3(widen(x),m,widen(y)) (#203508)
Add handling for X86ISD::VPERMI nodes with different immediates -
folding to a X86ISD::VPERMV3 instead, replacing a
INSERT_SUBVECTOR+2xPERMI nodes with a mask load
We don't need to concat the source operands - we have other folds that
will do this if beneficial - we just rely on (free) implicit widening.
Commit: 8f069e7aea7dbf35d87c8a7a700ae6871b831298
https://github.com/llvm/llvm-project/commit/8f069e7aea7dbf35d87c8a7a700ae6871b831298
Author: Joachim Meyer <5982050+fodinabor at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/tests/substitutions.py
Log Message:
-----------
[lit] Add support for %{s:stem} substitution. (#202885)
It provides the source file name with the (last) extension removed.
This is to align with what is available for %t and actually needed
downstream.
Commit: 1f21f15e6503053b3f5cfed3689829ba16a60ce0
https://github.com/llvm/llvm-project/commit/1f21f15e6503053b3f5cfed3689829ba16a60ce0
Author: Rohit Aggarwal <Rohit.Aggarwal at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/test/CodeGen/X86/avx512f-builtins-constrained-cmp.c
Log Message:
-----------
[X86] - Prevent the wrong fold of x86_avx512_mask_cmp_ss/sd to fcmp (#202321)
The issue is based upon the SemiAnalysisAI by @jlebar.
[058-mask-cmp-ss-imm-immediate-not-validated](https://github.com/SemiAnalysisAI/FuzzX/blob/master/x86/bugs/058-mask-cmp-ss-imm-immediate-not-validated/NOTES.md)
It is not a real bug, just a warning for the future fold implementation
of mask_cmp → fcmp.
There is non to fix as of now in the source code. Added a few comments
and test cases for the future implementation of the folds.
@topperc @phoebewang
Commit: fb009c38d86c4a3c5b13b0ea90bbdb7665670096
https://github.com/llvm/llvm-project/commit/fb009c38d86c4a3c5b13b0ea90bbdb7665670096
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
A llvm/test/CodeGen/DirectX/DebugInfo/di-commonblock.ll
A llvm/test/tools/dxil-dis/di-commonblock.ll
Log Message:
-----------
[DirectX] Drop DICommonBlock metadata (#201948)
DICommonBlock cannot be represented in LLVM 3.7, but it is a scope
within a parent scope, so we can refer to the parent scope instead.
Commit: a4bdf9d6ccdfcd9300164d9d043d74c78b2624cc
https://github.com/llvm/llvm-project/commit/a4bdf9d6ccdfcd9300164d9d043d74c78b2624cc
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-assign.ll
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-value-arglist.ll
A llvm/test/tools/dxil-dis/dbg-assign.ll
A llvm/test/tools/dxil-dis/dbg-value-arglist.ll
Log Message:
-----------
[DirectX] Lower DbgAssign to DbgValue (#200267)
DbgAssign is not representable in LLVM 3.7.
Commit: f77a290a2ffeda2a9974e87fa9120044de0ed93f
https://github.com/llvm/llvm-project/commit/f77a290a2ffeda2a9974e87fa9120044de0ed93f
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/test/Transforms/MergeICmps/X86/no-gep-other-work.ll
M llvm/test/Transforms/MergeICmps/X86/opaque-ptr.ll
Log Message:
-----------
[MergeICmps] Perform dereferenceability check with context (#202884)
To support deref-at-point semantics, we need to check dereferenceability
with a context instruction. Currently, MergeICmps does the check for
each individual load instruction. In this PR, I'm replacing this with a
check for all the loads that are part of a chain after they have been
collected, so we do the context-sensitive check only once.
The choice of context instruction is a bit tricky: Normally, this would
just be the first block in the chain (the "entry block"), but it's also
possible for the block to "do extra work", in which case it will get
split. If this happens, we should be checking at the splitting point, as
the extra work might be freeing the pointer.
Another question to consider here is whether we need to be concerned
about frees at all: After all, the original code will be accessing at
least one byte of the two objects, so doesn't that imply that it wasn't
freed already? This is indeed the case, as long as allocations cannot
shrink. This is something we currently don't allow, but I think it's
something we want to allow, so I'm going with the conservative treatment
here.
Commit: 3b63f045b9a994e275d8fd186f2de96939c38378
https://github.com/llvm/llvm-project/commit/3b63f045b9a994e275d8fd186f2de96939c38378
Author: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
Log Message:
-----------
[mlir][vector] extend `createReadOrMaskedRead`/`createWriteOrMaskedWrite` with permutation map support (#202766)
Follow-up to #201180.
Extends the existing `createReadOrMaskedRead` and
`createWriteOrMaskedWrite` utilities in `VectorUtils` with two optional
trailing parameters:
- `ArrayRef<Value> indices`
- `AffineMap permutationMap`
The affine super-vectorizer is updated to call these functions instead
of constructing `TransferReadOp`/`TransferWriteOp` directly.
@banach-space, please correct me if this wasn't what you meant in the
previous PR.
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Co-authored-by: Andrzej Warzyński <andrzej.warzynski at gmail.com>
Commit: 055ef48e1a98545c7ebb9246bb134fecfcc23cae
https://github.com/llvm/llvm-project/commit/055ef48e1a98545c7ebb9246bb134fecfcc23cae
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] Add tests showing failure to concat 256-bit rotate nodes on non-vlx targets (#203517)
These are widened in tablegen, we don't need to limit these to VLX targets
Commit: fc15b715917aea09851c41a0c5406d820709d35b
https://github.com/llvm/llvm-project/commit/fc15b715917aea09851c41a0c5406d820709d35b
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/Targets/SystemZ.cpp
Log Message:
-----------
[SystemZ] Rename GetSingleElementType to getSingleElementType (#203078)
# Refactor: Rename GetSingleElementType to getSingleElementType in
SystemZ ABI
## Summary
This PR refactors the SystemZ ABI code to follow LLVM coding standards
by renaming `GetSingleElementType` to `getSingleElementType` (camelCase
convention).
## Motivation
Rename to avoid having 'GetSingleElementType` in one class and
`getSingleElementType` in another one.
Commit: 7c0a3a52cf967da9c41d009fb92453b272d0d04a
https://github.com/llvm/llvm-project/commit/7c0a3a52cf967da9c41d009fb92453b272d0d04a
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/Driver/hip-profile-rocm-runtime.hip
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Log Message:
-----------
[PGO][HIP] Fix HIP device profile collection and sections emission (#202095)
Several related HIP device-PGO fixes:
Windows device collection. HIP rejects a hipMemcpy that reads past the
bounds
of a symbol registered with __hipRegisterVar, but device
data/counters/names
live in merged linker sections. Register a separate shadow for each
device
data, counters, and names symbol and copy each one by its exact
hipGetSymbolSize
size; this also lets static TUs with several kernels keep all their
profile
data. Open the device profile file in binary mode and pass the device
names to
the correct lprofWriteDataImpl arguments so llvm-profdata can read the
raw
profile. Open the versioned amdhip64_7.dll first, falling back to
amdhip64.dll.
Per-TU sections struct. Clang CodeGen emitted the
__llvm_profile_sections_<CUID>
struct (and its section start/stop references) for any profiling-enabled
device
TU. A TU with no instrumented device functions then referenced sections
nothing
populates, so the RDC device link failed under --no-undefined (and
duplicated
__llvm_prf_nm before per-CUID naming). Move the struct emission from
CGCUDANV
into the InstrProfiling pass, which emits it only when the TU has
profile data;
clang emits only the per-TU names-postfix marker, also making names
unique per
TU so RDC builds do not clash.
Dynamic-module interceptors. The hipModuleLoad* interceptors live in a
constructor-only object in clang_rt.profile_rocm that nothing
references, so the
linker drops it and dynamic-module programs collect no device profile.
When
linking clang_rt.profile_rocm, emit a force-link reference (-u on ELF,
-include: on COFF); the constructor self-skips when the program does not
use
hipModuleLoad.
Multi-device profile collection. On Linux, static profile collection
used to
try reading profile data from every visible HIP device. This could fault
when a
device was visible but had not launched the instrumented kernel. Track
HIP
devices that successfully launch kernels, and skip unused devices during
static
profile collection. If tracking is not available, keep the old
collect-all
behavior.
Depends on #201607 (reland HIP offload PGO compiler support and link the
device-profile runtime); that PR must land first.
Commit: 7d42028e806ab2b17af22ddb8417432e4781d4aa
https://github.com/llvm/llvm-project/commit/7d42028e806ab2b17af22ddb8417432e4781d4aa
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Log Message:
-----------
[lldb][Windows] Make RM_RF a no-op on an empty argument and swallow errors (#203040)
This patch makes the Windows `RM_RF` a no-op on an empty argument and
swallow errors, matching Unix `rm -rf`. This fixes issues in swiftlang
on fresh builds.
This is needed for https://github.com/swiftlang/llvm-project/pull/13180
Commit: 1badbb2a77f6937c9af84a694e1d949c7952b744
https://github.com/llvm/llvm-project/commit/1badbb2a77f6937c9af84a694e1d949c7952b744
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Fix copy-paste in hasNon16BitAccesses OpIs16Bit check (#203499)
OpIs16Bit tested TempOtherOp width instead of TempOp, mismatching
symmetric OtherOpIs16Bit clause
No observed miscompiles or direct issues to due to that so far
Commit: 5096057eb8254c7d56e1b70c4ba2fbf3ac215b73
https://github.com/llvm/llvm-project/commit/5096057eb8254c7d56e1b70c4ba2fbf3ac215b73
Author: Aditya Trivedi <120598696+adit4443ya at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/linear-clause01.f90
Log Message:
-----------
[Flang][OpenMP] Fix crash when common block name is used in LINEAR clause (#203250)
[Flang][OpenMP] Fix crash when common block name is used in LINEAR
clause
Using a common block name in a LINEAR clause (e.g. linear(/c/))
caused
a symbol-must-have-a-type crash during lowering. The semantic checker
was not emitting an error because GetSymbolsInObjectList expands /c/
to its member variables before the check runs, so the
symbol->has<CommonBlockDetails>() guard was never reached.
Fix by checking for common block names directly on the OmpObjectList
before the expansion, where the Name variant of OmpObject still holds
the common block symbol.
Fixes #202329
Commit: b0cc3225b2f618b5760552b1dc7ce0ea26225c8f
https://github.com/llvm/llvm-project/commit/b0cc3225b2f618b5760552b1dc7ce0ea26225c8f
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A mlir/test/IR/test-func-erase-arg-error.mlir
M mlir/test/lib/IR/TestFunc.cpp
Log Message:
-----------
[mlir] Check for argument uses in test-func-erase-arg pass (#203367)
The -test-func-erase-arg pass crashed when erasing arguments that still
had uses. Diagnose every such argument and fail the pass without
erasing.
Fixes https://github.com/llvm/llvm-project/issues/203218
Assisted-by: Claude (Claude Code)
Commit: daa9ecff7ea3ed9a99fd5b486516495655259971
https://github.com/llvm/llvm-project/commit/daa9ecff7ea3ed9a99fd5b486516495655259971
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(roti(x,i),roti(y,i)) -> roti(concat(x,y),i) on non-vlx targets (#203528)
128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these
We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
Commit: 75383d62ecde9e4948c6146662707d53cb496e08
https://github.com/llvm/llvm-project/commit/75383d62ecde9e4948c6146662707d53cb496e08
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
clang-format/test: Anchor the empty .clang-format-ignore to test_exec_root (#203444)
The test suite's lit.local.cfg creates an empty .clang-format-ignore at
config discovery time to protect the multiple-inputs[-inplace].cpp tests
that work on files in temporary locations.
This file should be written to where the tests execute instead of the
CWD during config discovery. The CWD might not even be an ancestor of
where the tests execute, and it might be the repository root which does
have a .clang-format-ignore that is incorrectly clobbered without this
change.
An alternative would be to just fix the tests that need to be protected,
but having a blanket guard like this does seem like a reasonable thing
to do.
Fixes: 915de1a5889c ("Generate empty .clang-format-ignore before running
tests (#136154)")
Commit: 95ca0744abc76f10da86bdd6e74f674a10a869f2
https://github.com/llvm/llvm-project/commit/95ca0744abc76f10da86bdd6e74f674a10a869f2
Author: NeKon69 <nobodqwe at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
A clang/test/Sema/LifetimeSafety/inapplicable-lifetimebound.cpp
M clang/test/Sema/LifetimeSafety/lifetime-facts.cpp
M clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-cross-tu.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-macro.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/noescape-violation.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Warn on inapplicable [[clang::lifetimebound]] parameters (#201101)
Adds `-Wlifetime-safety-inapplicable-lifetimebound` to diagnose
`[[clang::lifetimebound]]` annotations that have no effect because the
parameter type cannot carry a lifetime.
This currently diagnoses scalar parameters and `gsl::Owner` parameters
and unannotated record values (because they currently do not have
origins), while still allowing references, pointers and `gsl::Pointer`
values.
Closes #177184
Commit: 0246e4c1322e833ab6eb92b73cb618a66e693282
https://github.com/llvm/llvm-project/commit/0246e4c1322e833ab6eb92b73cb618a66e693282
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
R clang/test/CodeGen/AArch64/poly-add.c
Log Message:
-----------
[CIR][AArch64] Upstream addition and polynomial-addition NEON builtins (#202005)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for
- addition intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition)
- polynomial-addition intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#polynomial-addition)
Port tests:
- `clang/test/CodeGen/AArch64/neon_intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`
- `clang/test/CodeGen/AArch64/poly-add.c` to
`clang/test/CodeGen/AArch64/neon/add.c`
Commit: 0e704a021a5b9c82ee59d855401ef427385e4af1
https://github.com/llvm/llvm-project/commit/0e704a021a5b9c82ee59d855401ef427385e4af1
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
Log Message:
-----------
[AMDGPU] Fix illegal AGPR reclassification in RewriteMFMAFormStage (#200972)
If src2 escapes rewrite group then bridge copy AGPR -> VGPR must be
inserted.
Fixes a regression after
https://github.com/llvm/llvm-project/pull/198555
Commit: d426cca8835e109069f60630f886574af273e803
https://github.com/llvm/llvm-project/commit/d426cca8835e109069f60630f886574af273e803
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
Log Message:
-----------
[mlir][SPIR-V] Guard UMod canonicalization against zero divisor (#203513)
Chained `spirv.UMod` with a zero outer divisor reached `APInt::urem`
which causes UB
Commit: 7125490395b06f850f3ae02ae7ae69a6b2a647c2
https://github.com/llvm/llvm-project/commit/7125490395b06f850f3ae02ae7ae69a6b2a647c2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
Log Message:
-----------
[mlir][SPIR-V] Collapse duplicated i1-extension patterns in ArithToSPIRV (NFC) (#203247)
Commit: 43dc65d46b54415ea474b0bf0ad8b761444a7ba2
https://github.com/llvm/llvm-project/commit/43dc65d46b54415ea474b0bf0ad8b761444a7ba2
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
A llvm/test/Analysis/ValueTracking/known-non-zero-shr-add.ll
Log Message:
-----------
[ValueTracking] Infer non-zero from shr (add nuw A, B), C (#203039)
...if either A or B has a known-one bit at position >= C.
https://alive2.llvm.org/ce/z/ELYTjh
This eliminates null checks in some internal workloads.
Assisted-by: claude
Commit: ad6449fa73fd27b6d3493ab1999befd272e7fb31
https://github.com/llvm/llvm-project/commit/ad6449fa73fd27b6d3493ab1999befd272e7fb31
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Log Message:
-----------
[gn] "port" 93e03fc2666e (#203536)
Commit: d6ddc21af729fc145477e75ada8621e27e017b4e
https://github.com/llvm/llvm-project/commit/d6ddc21af729fc145477e75ada8621e27e017b4e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port b000f9032911 (#203537)
Commit: c8711e5db4fbe436a5aeede159e1a3c3eae08bf5
https://github.com/llvm/llvm-project/commit/c8711e5db4fbe436a5aeede159e1a3c3eae08bf5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
Log Message:
-----------
[gn build] Port b57c32db810b (#203538)
Commit: e302e85180ab0601ee564237a8cd75184bef5feb
https://github.com/llvm/llvm-project/commit/e302e85180ab0601ee564237a8cd75184bef5feb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port caea95990515 (#203539)
Commit: 71ff21aa50f07b0cadb929fe14fafda8b1f8243f
https://github.com/llvm/llvm-project/commit/71ff21aa50f07b0cadb929fe14fafda8b1f8243f
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
Log Message:
-----------
[gn build] Port d0a1f86e7890 (#203540)
Commit: 422d559a3a3af94c9e74c098761b110d749e248a
https://github.com/llvm/llvm-project/commit/422d559a3a3af94c9e74c098761b110d749e248a
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/MC/BUILD.gn
Log Message:
-----------
[gn build] Port df75b5d458b9 (#203541)
Commit: 305faf498a4e0b52b40742c927af63ab2082e1a9
https://github.com/llvm/llvm-project/commit/305faf498a4e0b52b40742c927af63ab2082e1a9
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
Log Message:
-----------
[gn build] Port fc1f754c397b (#203542)
Commit: 3255d4d7628719c4b6254db5780ec50862584896
https://github.com/llvm/llvm-project/commit/3255d4d7628719c4b6254db5780ec50862584896
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
A llvm/test/Bitcode/byte-constants.ll
Log Message:
-----------
[Bitcode] Decode small byte constants as signed values (#203408)
Decode small byte constants the same way we encode them. The bitcode
writer stores ConstantByte values as signed integers, so the reader must
rebuild them using the signed ConstantByte::get path. This has high-bit
values like b8 255 round-trip as their canonical signed form, b8 -1,
instead of tripping the APInt width assertion. This matches current i8
behavior.
Before the fix, the new test crashes in llvm-dis with: "APInt.h:
Assertion `llvm::isUIntN(BitWidth, val) && "Value is not an N-bit
unsigned value"' failed."
Bug found while investigating this PR
(https://github.com/llvm/llvm-project/pull/177908), which transitions
the LSV to emitting the byte type. Fix assisted by AI.
Commit: 09e3e004c66bea58525385486ab04327a51af9de
https://github.com/llvm/llvm-project/commit/09e3e004c66bea58525385486ab04327a51af9de
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
Log Message:
-----------
[gn] port 127a4c1a883d333 (LLVM_TARGETS_TO_BUILD for lldb shell tests) (#203547)
Commit: 6c3d7edcfa4a266681f19e6a002766c5a7066e34
https://github.com/llvm/llvm-project/commit/6c3d7edcfa4a266681f19e6a002766c5a7066e34
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
Log Message:
-----------
[AMDGPU][GISel] Add register bank legalization rules for amdgcn_cvt_sr_f16_f32. (#203253)
Commit: d46513abff5bfaf58de8169db033e54b9e24d7c2
https://github.com/llvm/llvm-project/commit/d46513abff5bfaf58de8169db033e54b9e24d7c2
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/Heatmap.cpp
M bolt/test/X86/heatmap-preagg.test
Log Message:
-----------
[BOLT] Fix heatmap with external addresses (#203479)
External samples (X:0) were breaking heatmap printing, e.g.
```
0x00000000: O0x00000000: ........
```
Explicitly track `IsFirst` instead of relying on zero.
Test Plan:
updated heatmap-preagg.test
Commit: 52751a0fda17f0dac1c441aee6617ab1b1434f4d
https://github.com/llvm/llvm-project/commit/52751a0fda17f0dac1c441aee6617ab1b1434f4d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/hip-toolchain-no-rdc.hip
Log Message:
-----------
[AMDGPU][SPIR-V] Fix treating SPIR-V input as the wrong LLVM-IR (#202986)
Summary:
This hack is intended for non-RDC AMDGCN.
Commit: c3a146a4e8fab800c621acc401dbdf1d0c960be8
https://github.com/llvm/llvm-project/commit/c3a146a4e8fab800c621acc401dbdf1d0c960be8
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for sched barriers intrinsics (#203425)
Add rules for sched barrier intrinsics. Note, there are regressions due
to AGPR results being copied back to VGPR un-necessarily. That will be
addressed in a future follow-up patch.
Commit: 8d2661b2d54e9dec96cba72ff5089c6fa7482bf3
https://github.com/llvm/llvm-project/commit/8d2661b2d54e9dec96cba72ff5089c6fa7482bf3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(rotate(x,a),rotate(y,b)) -> rotate(concat(x,y),concat(a,b)) (#203553)
128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these
We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
Commit: bdc06892cdd37c0a52717373ad7774136ca72b63
https://github.com/llvm/llvm-project/commit/bdc06892cdd37c0a52717373ad7774136ca72b63
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/mem2reg.mlir
Log Message:
-----------
[flang] Avoid invalid declare_value for promoted dummy-scope variables (#202498)
This fixes a verifier failure in mem2reg after inlining a CUDA device
procedure. When a promoted FIR alloca had an associated fir.declare with
a dummy_scope, mem2reg could create a fir.declare_value at a loop header
where the original dummy scope did not dominate.
Skip creating block-argument fir.declare_value ops for such
declarations, matching the existing replaced-value handling. Add a FIR
mem2reg regression test for the loop-header block argument case.
Commit: bbeb2d519171b57bbabb25ca07223c286cdecea2
https://github.com/llvm/llvm-project/commit/bbeb2d519171b57bbabb25ca07223c286cdecea2
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
Log Message:
-----------
[OpenACC][flang] Emit NYI when unstructured loops are associated with OpenACC directives (#202948)
Commit: 168666950ea9cd85471053319e216399e9750028
https://github.com/llvm/llvm-project/commit/168666950ea9cd85471053319e216399e9750028
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
Log Message:
-----------
[IR] Make CanBeFreed calculation optional (NFC) (#203490)
Make the CanBeFreed argument of getPointerDereferenceableBytes() a
pointer, so that nullptr can be passed if we're not interested in
whether frees are possible or not.
Nearly all places don't actually care about frees, including BasicAA,
which is the hottest caller of this API. This improves compile-time when
deref-at-point semantics are enabled.
I've kept the argument required so that callers still have to make an
explicit choice to ignore frees. (I'd be open to making it optional
though, given that only a single caller actually cares...)
Commit: c5654d53c008522d2da165f05b682aafa36d7189
https://github.com/llvm/llvm-project/commit/c5654d53c008522d2da165f05b682aafa36d7189
Author: Yuan Suo <suoyuan666 at s5n.xyz>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Introduce buildOriginFlowChain for use-after-scope (#199345)
After adding `buildOriginFlowChain`, we need to choose a diagnostic type
that is as simple as possible to verify its feasibility during `Sema`
diagnostics.
I did not choose the annotation suggestions described in
https://github.com/llvm/llvm-project/pull/188467/#issuecomment-4359071778
as the first target to implement, because it does not seem to occur
within a single CFG block. The `IssueFact` always resides in the block
preceding the `OriginEscapesFact`, which causes me to always get an
empty `OriginFlowChain`.
Since we use `buildOriginFlowChain`, we can directly trace distinct
assignment steps that occur within a single source-level expression. For
example:
```cpp
#include <vector>
#include <string>
template<class... T> void use(T... arg);
void operator_star_arrow_of_iterators_false_positive_no_cfg_analysis() {
std::vector<std::pair<int, std::string>> v;
const char* p = v.begin()->second.data();
const char* q = (*v.begin()).second.data();
const std::string& r = (*v.begin()).second;
auto temporary = []() { return std::vector<std::pair<int, std::string>>{{1, "1"}}; };
const char* x = temporary().begin()->second.data();
const char* y = (*temporary().begin()).second.data();
const std::string& z = (*temporary().begin()).second;
use(p, q, r, x, y, z);
}
```
The code above produces the following diagnostic output:
```txt
pr.cpp:13:19: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~
pr.cpp:13:52: note: destroyed here
13 | const char* x = temporary().begin()->second.data();
| ^
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~~~
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pr.cpp:16:16: note: later used here
16 | use(p, q, r, x, y, z);
| ^
pr.cpp:15:28: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~
pr.cpp:15:49: note: destroyed here
15 | const std::string& z = (*temporary().begin()).second;
| ^
pr.cpp:15:28: note: expression aliases the storage of local temporary object
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:15:27: note: expression aliases the storage of local temporary object
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~~~~~~~~~~
pr.cpp:16:22: note: later used here
16 | use(p, q, r, x, y, z);
| ^
pr.cpp:14:21: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~
pr.cpp:14:54: note: destroyed here
14 | const char* y = (*temporary().begin()).second.data();
| ^
pr.cpp:14:21: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:14:20: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~~
pr.cpp:14:19: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pr.cpp:16:19: note: later used here
16 | use(p, q, r, x, y, z);
| ^
3 warnings generated.
```
---------
Signed-off-by: Yuan Suo <suoyuan666 at s5n.xyz>
Commit: 422af7cca672a717bd9505a486e287fa2734bbc9
https://github.com/llvm/llvm-project/commit/422af7cca672a717bd9505a486e287fa2734bbc9
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
Log Message:
-----------
[MIR] Save internal VirtRegMap state in MIR (#197361)
Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:
registers:
- { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }
Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.
So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.
Mechanism:
- For serialization:
- MIRPrinter emits the new fields only when the VirtRegMap is available.
- For deserialization:
- MIRParser stashes parsed entries in the MachineRegisterInfo object
- VirtRegMap::init() drains the stash via assignVirt2Phys and
setIsSplitFromReg, then clears it.
Validation at parse time:
- 'assigned-phys' must be a physical register.
- 'split-from' must reference a different vreg than 'id'.
- 'split-from' physregs / named-vreg references already rejected
by parseStandaloneVirtualRegister.
I'm not super happy about stashing the VRM info in the MRI, but that's
a small price to pay.
Commit: 1b774ab021698428374815fb8d4d88855c3b2a48
https://github.com/llvm/llvm-project/commit/1b774ab021698428374815fb8d4d88855c3b2a48
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
Log Message:
-----------
[StackColoring] Cleanup stack-coloring test (NFC) (#203551)
This simply applies postcommit suggestions made here:
https://github.com/llvm/llvm-project/pull/199959
Commit: 7814cc9454cf454acdc7385fc41809a6bdf5d7f8
https://github.com/llvm/llvm-project/commit/7814cc9454cf454acdc7385fc41809a6bdf5d7f8
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
Log Message:
-----------
[AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (#187046)
Add support for the following Armv9.7-A Lookup Table (lut)
instruction intrinsics, as defined in the ACLE[1]:
SVE2.3:
```c
// Variants are also available for: _u8 _mf8
svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```
SVE2.3 and SME2.3:
``` c
// Variants are also available for _u16_x2 and _f16_x2.
svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);
```
SME2.3:
```c
// Variants are also available for: _u16, _f16 and _bf16.
svint16x4_t svluti6_lane_s16_x4[_s16_x2](svint16x2_t table, svuint8x2_t indices, uint64_t imm_idx);
// Variants are also available for: _u8 and _mf8.
svint8x4_t svluti6_zt_s8_x4(uint64_t zt0, svuint8x3_t zn) __arm_streaming __arm_in("zt0");
// Variants are also available for: _u8 and _mf8.
svint8_t svluti6_zt_s8(uint64_t zt0, svuint8_t zn) __arm_streaming __arm_in("zt0");
```
[1] https://github.com/ARM-software/acle/pull/428/
Commit: 5906827e155cc5fca10cd505b88a4e21b861d65b
https://github.com/llvm/llvm-project/commit/5906827e155cc5fca10cd505b88a4e21b861d65b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
Log Message:
-----------
[lldb][Windows] Forward OUTPUT_DEBUG_STRING_EVENT through lldb-server (#203546)
Hoist `ReadDebugString` into `ProcessDebugger` so both plugins share it,
then add
`NativeProcessWindows::OnDebugString` that reads the string, converts
UTF-16 to
UTF-8 when needed, and delivers via `NativeDelegate::NewProcessOutput`.
Fixes `Process/Windows/output_debug_string.cpp` on Windows under
`LLDB_USE_LLDB_SERVER=1`.
Commit: 9f3ac763bd8c4be2db1a97cec13bb59c87a9595f
https://github.com/llvm/llvm-project/commit/9f3ac763bd8c4be2db1a97cec13bb59c87a9595f
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
Log Message:
-----------
[MLIR][XeGPU] Fix issue with expandDim (#203299)
In case, sgData is replicated or
bool sgDataReplicated = hasSgData && origSgDataDim ==
computeProduct(targetShape);
sgDataReplicate is evaluated to "true"
dimSizeCap and perSgShape shouldn't be divided by expSgLayout
Add a regression test (shape_cast_collapse_replicated) covering the
replicated sg_data collapse.
Commit: 9bbed741e260753de029fcf7b22844fe23362a39
https://github.com/llvm/llvm-project/commit/9bbed741e260753de029fcf7b22844fe23362a39
Author: dibrinsofor <64705019+dibrinsofor at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
Log Message:
-----------
[AArch64] Optimize vector slide shuffles with zeros to use shift instructions (#185170)
We currently emit `movi`+`ext` instructions when generating code for
shuffle slides of a 64-bit vector left/right and fill it with zeros.
This patch optimizes these patterns to use a single `ushr`/`shl`
instruction instead.
Example:
```llvm
define <8 x i8> @slide_left(<8 x i8> %v) {
%r = shufflevector <8 x i8> %v, <8 x i8> zeroinitializer,
<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
ret <8 x i8> %r
}
```
Before, we generate:
```
movi v1.2d, #0
ext v0.8b, v0.8b, v1.8b, #1
```
Now:
```
ushr d0, d0, #8
```
Fixes: #183398
Alive2 proof: https://alive2.llvm.org/ce/z/QaW5CQ
---------
Signed-off-by: Dibri Nsofor <dibrinsofor at gmail.com>
Commit: c9938eb76ca653abff8d0b7c99bd74aec57c4758
https://github.com/llvm/llvm-project/commit/c9938eb76ca653abff8d0b7c99bd74aec57c4758
Author: nirhersh <77844231+nirhersh at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
Log Message:
-----------
[mlir][arith] Implement ValueBoundsOpInterface for min/max ops (#203269)
Add ValueBoundsOpInterface external models for the arith integer min/max operations: arith.minsi and arith.maxsi.
---------
Co-authored-by: Nir Herscovici <nir.herscovici at mobileye.com>
Commit: c62768b10e5e16c494eef8289452a7d7d97798bf
https://github.com/llvm/llvm-project/commit/c62768b10e5e16c494eef8289452a7d7d97798bf
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Fix valid range of ord in tensormap.replace op (#202853)
Fixes the valid range of the `ord` attribute in the NVVM dialect
`tensormap.replace` op to be `0-4` as indicated in the PTX ISA.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-tensormap-replace
Commit: 2d1fb738d6f9eb109a2f1e0405397565f25fece4
https://github.com/llvm/llvm-project/commit/2d1fb738d6f9eb109a2f1e0405397565f25fece4
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
Log Message:
-----------
[mlir][LLVM][ROCDL] Add buffer oob mode module flags, flag interfaces (#202729)
Now that the out-of-bounds mode for buffer accesses will be controlled
by a module flag and is no longer a function of the subtarget triple (as
of #160922) and since `ptr addrpace(7)` lowering will start respecting
this mode soon, add MLIR-level support for setting this flag.
After a few iterations, I think adding this module flag to
`llvm.module.flags` but adding interfaces for module flag attributes (so
that those wishing to set this flag don't need to know it has `max`
combining semantics or look up the enum values) is a
minimally-disruptive way to get a more ergonomic wrapper around this
functionality.
AI note: AI generated the code hehe, I reviewed it. The documentation
update to ModuleFlagsOp is mine.
(The LLVM PR that would want people to start explicitly setting
`relaxed` is #134329)
Co-authored-by: Codex <codex at openai.com>
Commit: 484b955581d976f97a47ef621c441e21c231aa23
https://github.com/llvm/llvm-project/commit/484b955581d976f97a47ef621c441e21c231aa23
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
Log Message:
-----------
[CIR] Implement throw within an aggregate expression (#203404)
This implements CIR support for throwing an exception from within a
branch of a ternary expression that represents an aggregate prvalue. We
previously had support for throwing an exception within a ternary
aggregate expression, but when the expression uses a prvalue, it goes
through a different code path. The new implementation is just calling an
existing function from a different place. The bulk of what's being added
here is the testing.
Commit: 99a37aedebd7c69680e74ac83769a11eaefef1e7
https://github.com/llvm/llvm-project/commit/99a37aedebd7c69680e74ac83769a11eaefef1e7
Author: Quentin <qcoelho at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/StringExtras.h
Log Message:
-----------
[ADT][NFC] Fix documentation for arrayRefFromStringRef (#203430)
The documentation was describing the opposite behavior of what it does.
Commit: 17207c8feb9fc6c576ce820ff4583e337dc0452e
https://github.com/llvm/llvm-project/commit/17207c8feb9fc6c576ce820ff4583e337dc0452e
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Change "local temporary object" to "temporary object" in diagnostics (#203573)
Commit: 878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da
https://github.com/llvm/llvm-project/commit/878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
Log Message:
-----------
[win][x64] Windows x64 unwind v3: Update epilog inheritance per spec clarification (#202778)
The Windows x64 unwind v3 spec was clarified
(MicrosoftDocs/cpp-docs#5936) to state that an EPILOG_INFO_V3 record
with `NumberOfOps == 0` inherits its effective fields from the first
*preceding* descriptor with `NumberOfOps != 0` (the "base"), not the
immediately preceding one. Additionally, Flags bits 0 and 1 are no
longer inherited; the producer must replicate them so they match the
base descriptor.
- Encoder (MCWin64EH.cpp): compare each epilog against the tracked base
descriptor, and emit EPILOG_INFO_LARGE in inherited descriptors' own
flags byte.
- Decoder (Win64EH.cpp): track the base index and inherit from it; keep
the record's own flags byte instead of copying the previous record's.
- Dumpers (llvm-readobj, llvm-objdump): reword "previous epilog" to
"base epilog".
- Tests: update multi-epilog expectations and add a LARGE
inherited-epilog case to seh-unwindv3-inheritance.s.
Commit: 528e6f9a030c4b3bf760807c22c98f17fb582f5f
https://github.com/llvm/llvm-project/commit/528e6f9a030c4b3bf760807c22c98f17fb582f5f
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
Log Message:
-----------
[AArch64] Avoid creating a new generic constant in SelectSMETileSlice (#203344)
This was creating a new ISD::Constant node during instruction selection,
which may also need lowering (e.g., to a `mov gpr, wzr`). The issue with
this is the new constant node will not end up on the instruction
selection worklist, as the complex pattern executes after the worklist
has been prepared. This means the constant will lower directly to an
immediate. This issue was hidden in some cases by `getConstant()`
returning a pre-existing `ISD::Constant` node already within the
instruction selection worklist.
This patch works around this by directly emitting a `CopyFromReg WZR`
within SelectSMETileSlice, which does not need further instruction
selection.
Fixes #203295
Commit: 9240c64f4528064cec31e8875fb891b473f8ca7c
https://github.com/llvm/llvm-project/commit/9240c64f4528064cec31e8875fb891b473f8ca7c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/BundleAttributes.cpp
Log Message:
-----------
[LVI][ValueTracking] Merge checking whether assumes imply nonnull (#203523)
Commit: eaef650f57900b36751dea4e0383de1e73cdff29
https://github.com/llvm/llvm-project/commit/eaef650f57900b36751dea4e0383de1e73cdff29
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
Log Message:
-----------
[CIR] Implement handling for CXXConstructLValue expressions (#203402)
This implements the handling to emit an l-value for CXXConstructExpr and
CXXTemporaryObjectExpr expressions. This is a simple copy from the
equivalent code in classic codegen and uses existing CIR code for most
of the actual work.
A multi-argument constructor call written with explicit type syntax
produces a CXXTemporaryObjectExpr. Using it as the base of a member
access reaches emitLValue with that expression class. A single-argument
constructor call performs a constructor conversion, so the base of the
member access is a CXXFunctionalCastExpr whose subexpression is a
CXXConstructExpr. emitCastLValue forwards to the subexpression, reaching
emitLValue with the CXXConstructExpr class.
Commit: e476b23c5facd1705f06ee60f1e62869c638f395
https://github.com/llvm/llvm-project/commit/e476b23c5facd1705f06ee60f1e62869c638f395
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
Log Message:
-----------
[Fuzzer] Make signal tests work with internal shell (#203445)
Wrap some commands in bash as it seemed like the least bad option. The
alternative is to use setsid and run the other commands in the internal
shell, but them it's impossible to use wait and we run into reliability
issues because of that.
Commit: 473ca91cdb03d01394eea440ea4f3a14cdc04b6e
https://github.com/llvm/llvm-project/commit/473ca91cdb03d01394eea440ea4f3a14cdc04b6e
Author: Jan Korous <jkorous at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
Log Message:
-----------
[clang][ssaf] Add --ssaf-compilation-unit-id= flag (#203345)
The TU summary extractor previously sourced the CompilationUnit
namespace name from clang's `InFile` argument, which made the identity
of a TU summary depend on the file path the build system passed to
clang. Have the build system pass the identifier directly:
- New driver/cc1 option `--ssaf-compilation-unit-id=<id>`, marshalled
into `FrontendOptions::SSAFCompilationUnitId`.
- `TUSummaryRunner` builds its `BuildNamespace(CompilationUnit, ...)`
from the new option's value; `InFile` is no longer threaded into the
runner.
- New diagnostic `warn_ssaf_tu_summary_requires_compilation_unit_id`
(under `-Wscalable-static-analysis-framework`, `DefaultError`) fires
when `--ssaf-tu-summary-file=` is set without a non-empty
`--ssaf-compilation-unit-id=`. The runner falls back to the wrapped
consumer alone in that case, matching the existing setup-time SSAF
diagnostics.
Assisted-By: Claude Opus 4.7
Commit: fdd939dce1eb145e386dc3242661c3a73b759e4f
https://github.com/llvm/llvm-project/commit/fdd939dce1eb145e386dc3242661c3a73b759e4f
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XeGPU] Use context-aware type converter in WgToSgDistribute and Blocking pass (#194685)
This PR replaces the TypeConverter in xegpu-wg-to-sg-distribute and
xegpu-blocking with a context-aware converter that picks each value's
converted type from the layout attached to its defining op/use, removing
the need for the UnrealizedConversionCastOpPattern workaround for scf
ops.
Commit: 6dbe068edef96c13930471d602fd5fb876e9da04
https://github.com/llvm/llvm-project/commit/6dbe068edef96c13930471d602fd5fb876e9da04
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
Log Message:
-----------
[Win][x64] Fix -Wunused-variable (#203591)
BaseEpiFlags is only used in assertions, so mark it maybe_unused to
avoid the warning in release builds.
Commit: 0a9cf8c6c3038f1a02fa2051d12c9e9d7ddb4aad
https://github.com/llvm/llvm-project/commit/0a9cf8c6c3038f1a02fa2051d12c9e9d7ddb4aad
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes fdd939d (#203593)
This fixes fdd939dce1eb145e386dc3242661c3a73b759e4f.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e4a63425ba266f6027e7d257c9a79141c26aa8d8
https://github.com/llvm/llvm-project/commit/e4a63425ba266f6027e7d257c9a79141c26aa8d8
Author: Jiaqi He <heturing at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[RISC-V] Add newer Linux hwprobe extensions detection (#192761)
Commit: 660771d4359b14fe56a5eef19c33f93475aee39e
https://github.com/llvm/llvm-project/commit/660771d4359b14fe56a5eef19c33f93475aee39e
Author: Jiachen Yuan <jiacheny at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/Bitset.h
M llvm/unittests/ADT/BitsetTest.cpp
Log Message:
-----------
Reapply "[ADT] Bitset: add shift operators, word accessors, and etc" (#195874)
Reapplies #193400, which was reverted in #195848 because it broke
buildbots with:
```
Bitset.h:271: error: static assertion failed: Unsupported word size
```
Root cause: a `static_assert(BitwordBits == 32, ...)` inside the
discarded `else` branch of `if constexpr (BitwordBits == 64)` in
`getWord64()`. The assert's condition is non-template-dependent
(`BitwordBits` derives from `sizeof(uintptr_t)`, not from `NumBits`), so
it is checked even though the branch is discarded, and fires on 64-bit
hosts. Related:
https://stackoverflow.com/questions/38304847/how-does-a-failed-static-assert-work-in-an-if-constexpr-false-block
Fix: drop the redundant inner `static_assert`. The class-level
`static_assert(BitwordBits == 64 || BitwordBits == 32, ...)` already
enforces the same invariant.
No functional change beyond the original PR.
---------
Co-authored-by: Rahul Joshi <rjoshi at nvidia.com>
Commit: 5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9
https://github.com/llvm/llvm-project/commit/5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/test/MC/COFF/seh-unwindv3-error.s
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
Log Message:
-----------
[llvm-ml] Add MASM unwind v3 support for x64 exception handling and improve MSVC compat (#202809)
New command-line options:
- `/unwindv3`: Enable V3 unwind information format
New MASM directives:
- `.push2reg` / `.pop2reg`: Push/pop register pairs (PUSH2/POP2)
- `.beginepilog` / `.endepilog`: Delimit epilog unwind regions
- `.popreg`, `.freestack`, `.restorereg`, `.restorexmm128`,
`.unsetframe`: Epilog counterparts of existing prolog directives
- `.pushframe code`: MASM syntax for interrupt handlers with error codes
New built-in symbol:
- `@UnwindVersion`: Returns the current x64 unwind version being used.
Error diagnostics:
- Prolog directives after `.endprolog` are diagnosed
- Epilog directives outside `.beginepilog`/`.endepilog` are diagnosed
- Nested `.beginepilog` is diagnosed
- Unwind v3 directives or using extended registers in directives without
unwind v3 are diagnosed
Commit: f2957d7a56372cf8bd2b48aec81ae7c0fb38813f
https://github.com/llvm/llvm-project/commit/f2957d7a56372cf8bd2b48aec81ae7c0fb38813f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang][OpenMP] Add missing check for empty argument list (#203592)
Commit: 5036a80a20a6749f95b77a2c08786f42fdd056ac
https://github.com/llvm/llvm-project/commit/5036a80a20a6749f95b77a2c08786f42fdd056ac
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
Log Message:
-----------
[HLSL][NFC] Remove unused location argument (#203467)
The location argument was just passed around but never used.
Commit: 2a72cd87a5bb9db73708661e8760ff710460ae11
https://github.com/llvm/llvm-project/commit/2a72cd87a5bb9db73708661e8760ff710460ae11
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/unittests/Support/GlobPatternTest.cpp
Log Message:
-----------
[NFC][Support] Add test for inverted slash-agnostic matching (#203290)
Add a test case to GlobPatternTest to verify that inverted character
classes containing slashes (e.g. [^/] or [^\\]) behave correctly
under SlashAgnostic mode (i.e. they do not match either slash).
Assisted-by: Gemini
Commit: 64381998961b4b9324ab5a6f6015b285b59d6bb6
https://github.com/llvm/llvm-project/commit/64381998961b4b9324ab5a6f6015b285b59d6bb6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
Log Message:
-----------
[VPlan] Introduce m_SelectLike and use to support 2-operand blends. (#194729)
We should be able to treat 2-operand blends like select by most VPlan
code. Add a new m_SelectLike matcher and use in places that only use the
matcher to extract operands.
Overall this leads to a small number of improvements in RISCV (~10 files
changed in a large IR corpus) and 2 loops changed on AArch64 with
tail-folding forced.
PR: https://github.com/llvm/llvm-project/pull/194729
Commit: fda7a72af7a76ac6b51a8a1b1222f878d76405ed
https://github.com/llvm/llvm-project/commit/fda7a72af7a76ac6b51a8a1b1222f878d76405ed
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMGDPU] Add gfx1251 V_PK_MIN/MAX_NUM_F64 (#203596)
Also legalizes v2f64 fcanonicalize.
Commit: 2c1b71af78df9d7c22e225069971d3276d91d546
https://github.com/llvm/llvm-project/commit/2c1b71af78df9d7c22e225069971d3276d91d546
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
Log Message:
-----------
[VPlan] Compute URem via APInt in materializeVectorTripCount (#203604)
materializeVectorTripCount has a shortcut for scalable steps: if the
constant trip count is divisible by the maximum possible runtime step,
the vector trip count equals the trip count directly. This called
APInt::getZExtValue unconditionally, which asserts when the constant
value needs more than 64 bits.
Compute the URem in APInt to fix the crash.
Commit: 1060a6be0a471106fd65a3f16937ee1c588dabed
https://github.com/llvm/llvm-project/commit/1060a6be0a471106fd65a3f16937ee1c588dabed
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
Log Message:
-----------
[SimplifyCFG][DirectX] Honor target minimum lookup table element width (#203103)
fixes #202481
This change adds a `TTI::getMinimumLookupTableEntryBitWidth()` (default
`8`) and fold it
into SimplifyCFG's `NeededBitWidth` computation so targets can prevent
unsupported
narrow lookup tables. DirectX returns 32 (or 16 with native 16-bit
types) so tables
never narrow to the unsupported i8 type.
> Assisted by Claude Opus 4.8
Commit: 10508afd0b14ffcf6819665e31d64d77ccd45d3f
https://github.com/llvm/llvm-project/commit/10508afd0b14ffcf6819665e31d64d77ccd45d3f
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
Reland "[SSAF][Extractor] Make hard errors in PointerFlow and UnsafeBufferUsage Extractors quiet (#201953)" (#203602)
Reverted 7dcd1d2ad104c3f9748370a42dc775cd6e7e34dc and added '#ifndef
NDEBUG' guards for tests using 'llvm::setCurrentDebugType'.
Original message:
Hard errors were used in extractors during development to quickly
identify unsupported language constructs. This commit converts them to
DEBUG_WITH_TYPE so that these errors are silenced in release builds.
In addition, translating unsupported language constructs now silently
results in an empty EntityPointerLevelSet. The PointerFlowExtractor will
skip empty sets for either the source or the destination when building
edges to avoid an ill-formed edge set data structure.
rdar://178747892
Commit: 0b128394b9c796ebe4efd9e0dde38976fb291798
https://github.com/llvm/llvm-project/commit/0b128394b9c796ebe4efd9e0dde38976fb291798
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
Log Message:
-----------
[llvm-diff] Respect AllowAssumptions in diffCallSites (#203597)
diffCallSites always built an AssumptionContext, so call sites made
optimistic equivalence assumptions even when the caller disabled them.
This made matchForBlockDiff over-match, and the re-check in unify() then
hit the "structural differences second time around?" assertion.
Thread the caller's AssumptionContext into diffCallSites so call sites
honor the no-assumptions request like every other instruction kind.
Fixes #184133
Commit: 12d95c65fc99a3d5686f1d409572d1965fd653b1
https://github.com/llvm/llvm-project/commit/12d95c65fc99a3d5686f1d409572d1965fd653b1
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
R llvm/test/Transforms/LICM/vector-insert.ll
Log Message:
-----------
Revert "[LICM] Allow hoisting of InsertElementInst's past non-hoistable InsertElementInsts" (#203611)
Reverts llvm/llvm-project#200532
Commit: 0526807f89803b394fcebc87dfc234e57513986e
https://github.com/llvm/llvm-project/commit/0526807f89803b394fcebc87dfc234e57513986e
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A clang/test/AST/tyloctype_alignment.cpp
Log Message:
-----------
[clang][z/OS] Add test for TypeLoc tail padding alignment (#202710)
This adds a test for the TypeLoc tail padding fix that was merged in
commit 89305c3.
Commit: 5f51294647b3c4c08dfd0e455b1a997074864d26
https://github.com/llvm/llvm-project/commit/5f51294647b3c4c08dfd0e455b1a997074864d26
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
Log Message:
-----------
Fix contextual implicit conversions to int: with _Atomic (#203522)
PerformContextualImplicitConversion was performing
default-lvalue-conversions, then basing decisions on viable conversion
functions on this type However, when we then went to add the candidates
we were using the 'old' value (pre-conversion) of the type, resulting in
us regaining the lost 'atomic' from the default Lvalue conversion.
This patch updates the 'from' variable to be the converted value so all
conversions are done post-conversion.
Fixes: #201770
Commit: ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5
https://github.com/llvm/llvm-project/commit/ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
Log Message:
-----------
[ConstraintElim] Add test with negative offset and NUW only GEP (NFC) (#203614)
Add test currently mis-compiled with NUW only GEP.
https://alive2.llvm.org/ce/z/7G8uE3
Commit: 327ce1bb0cd56e74bfd79f51463e6c0a81905a25
https://github.com/llvm/llvm-project/commit/327ce1bb0cd56e74bfd79f51463e6c0a81905a25
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/lit.cfg.py
Log Message:
-----------
[Fuzzer] Use the internal shell by default (#203450)
The external shell is going away soon and the internal shell is superior
in most ways (platform compatibility, performance, debugging). This now
causes no test failures and is blocking deprecation of the external
shell, so switch over.
Commit: b312ae01043b75637f4fd4dbaf66a09907f63c22
https://github.com/llvm/llvm-project/commit/b312ae01043b75637f4fd4dbaf66a09907f63c22
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64 (#203607)
Commit: 87d29e3f438c9c02390a4260e9a1bc7712f882c2
https://github.com/llvm/llvm-project/commit/87d29e3f438c9c02390a4260e9a1bc7712f882c2
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
Log Message:
-----------
[AMDGPU] NFC: Drop constexpr from getFlavor*Name functions (#203603)
It seems specifying these as constexpr was causing some buildbot
failures due to llvm_unreachable --
```
[1/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h:20,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h:16,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp:14:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown AMDGPUSchedReason");
[2/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:17:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown AMDGPUSchedReason");
ninja: build stopped: subcommand failed.
```
See alo
(https://github.com/llvm/llvm-project/pull/192322#issuecomment-4672427400)
Commit: 3abb8d8a05a215f719cd5ebc962e5f07ffbaeaa1
https://github.com/llvm/llvm-project/commit/3abb8d8a05a215f719cd5ebc962e5f07ffbaeaa1
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
Log Message:
-----------
[MLIR][XeVM] Add xevm.extf op as the inverse of xevm.truncf (#203124)
Add a new xevm.extf operation that extends f8/bf8/f4 values to f16/bf16,
mirroring the existing xevm.truncf op, together with its lowering in
XeVMToLLVM.
Lowering details (XeVMToLLVM):
- bf8/f8 -> f16 via __builtin_IB_bf8tohf_16 / __builtin_IB_hf8tohf_16.
- bf8/f8 -> bf16 via f16 -> f32 (convert_float16) -> bf16
(__builtin_IB_ftobf_16).
- e2m1 (fp4) -> f16/bf16 via __builtin_IB_shfl_idx4_lut and
__builtin_IB_shfl_idx4_to_fp16_8_packed (LUT 7 for f16, 5 for bf16).
Adds the op definition and verifier, conversion/roundtrip/invalid unit
tests, and f8 and fp4 GPU round-trip integration tests.
Adds arith.extf to xevm.extf lowering and arith.truncf to xevm.truncf
lowering in XeGPU to XeVM conversion and unit tests.
Commit: c4c30cebec281eb52e9742cfb1f892fa3c1d9624
https://github.com/llvm/llvm-project/commit/c4c30cebec281eb52e9742cfb1f892fa3c1d9624
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
Log Message:
-----------
[SLP] Vectorize full insertvalue buildvector sequences
Treat a complete chain of insertvalue instructions building a homogeneous
literal struct from scalars as a buildvector, like insertelement sequences.
The scalars are vectorized into one vector; the aggregate is rebuilt from it
via a stack store + load, or stored directly when its only user is a store.
insertvalue is routed through the existing insertelement buildvector paths
(type/index helpers, reordering, tree build, cost model, min-bitwidth, and
codegen). Only single-index, non-vector inserts building from an undef
aggregate are handled.
Fixes #43353
Reviewers: hiraditya, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/200274
Commit: ae026a59dad1a0a59209418f7a39e16a889c8ac1
https://github.com/llvm/llvm-project/commit/ae026a59dad1a0a59209418f7a39e16a889c8ac1
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
Log Message:
-----------
[AMDGPU] Enable S_ADD_PC_I64 on gfx1251 (#203613)
Commit: 2f8a39d73394b9a50a32fed5430896afa32a06f5
https://github.com/llvm/llvm-project/commit/2f8a39d73394b9a50a32fed5430896afa32a06f5
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
Log Message:
-----------
[LoopInterchange] Fix crash when followLCSSA returns constant (#203515)
Similar as the case in ##201069, `followLCSSA` may return a constant
value, but it was cast to Instruction unconditionally. We need to
explicitly check whether the returned value is an Instruction or not.
Fix #203375.
Commit: d0cd530bf4e28732368244476c4f504a4920e6c4
https://github.com/llvm/llvm-project/commit/d0cd530bf4e28732368244476c4f504a4920e6c4
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
Log Message:
-----------
[LoopInterchange] Mark getAddRecCoefficient with static (#203624)
As this function is a file-scope non-member function, it's better to
mark it with static.
Commit: e882286f4bb9095558e9783aa79cc6ca90487bcf
https://github.com/llvm/llvm-project/commit/e882286f4bb9095558e9783aa79cc6ca90487bcf
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Fix perf data return identification (#203628)
If perf data doesn't have branch type recorded, missing value would
incorrectly be interpreted as not-a-return. Only populate Returns map if
the branch type is available.
Fixes bug introduced in #202813.
Commit: 8fb9963fd4da8bc5b3b7e186cd369102f42d3640
https://github.com/llvm/llvm-project/commit/8fb9963fd4da8bc5b3b7e186cd369102f42d3640
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_LSHL_ADD_U64 (#203612)
Commit: 181d8084770935e4e3cd1877d317e95b73fe8368
https://github.com/llvm/llvm-project/commit/181d8084770935e4e3cd1877d317e95b73fe8368
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
Log Message:
-----------
[AArch64][PAuth] Fix return-address auth for swifttailcc with FPDiff > 0 (#203340)
When a swifttailcc tail call has FPDiff > 0 (the caller received more
stack argument space than the callee pops), the epilogue contains an SP
adjustment to discard the leftover argument space. The existing code
treated both FPDiff < 0 and FPDiff > 0 uniformly in a single 'FPDiff !=
0' block, using AUTI[AB]1716 with a reconstructed entry-SP in x16 for
both cases.
For FPDiff < 0 (callee pops more) that reconstruction is necessary and
correct. For FPDiff > 0 it is wrong: by the time we enter the block the
post-index LDP has already adjusted SP back to the frame base, but the
'add sp, sp, #N' argument pop has not yet run. Entry SP equals the
current SP at that point, so AUTI[AB]SP would work directly, but instead
the combined block bumped SP via StackOffset::getFixed(-FPDiff) which
overshoots, and then emits AUTIA1716 with a wrong discriminator. Worse
yet, the SP restore had already been emitted *before* the auth, leaving
the live argument stack below SP and outside the red-zone during the
authentication window.
Fix by splitting the block on the sign of ArgumentStackToRestore:
* `< 0`: reconstruct entry SP in x16, save LR in x17, authenticate with
AUTI[AB]1716 (or AUTI[AB]171615 / PACM+AUTI[AB]1716 for PAuthLR).
* `> 0`: temporarily remove the 'add sp, sp, #N' SP-modifying
instructions from before the auth instruction (SPMods shuffle),
authenticate with AUTI[AB]SP (SP == entry SP at this point), then
re-insert the SP adjustment afterward.
Commit: 4c057feb7835680c39c78e826c033307bec74295
https://github.com/llvm/llvm-project/commit/4c057feb7835680c39c78e826c033307bec74295
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
Log Message:
-----------
[AMDGPU][true16] extract 16bit for scratch_load_ubyte_st when spilling (#203589)
In sramecc mode scratch_load_ubyte_st is selected for 16bit spilling.
Need a tmp vgpr32 and extract lo16 from it
Commit: 0a6e0210df5596f4aa35b6d01d0dcedc9414dab9
https://github.com/llvm/llvm-project/commit/0a6e0210df5596f4aa35b6d01d0dcedc9414dab9
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
Log Message:
-----------
[SPIR-V] Lower freeze instructions with aggregate operands (#203584)
An aggregate freeze takes its result type from its operand, like a PHI
or select, but was handled by neither the up-front value-id mutation nor
replaceMemInstrUses, so the pass aborted with "illegal aggregate
intrinsic user". Mutate aggregate freezes to the i32 value-id type and
replace their operands alongside PHIs and selects.
Commit: d2163f7c0c21390190e1ccb91e61958ad6ecc9f9
https://github.com/llvm/llvm-project/commit/d2163f7c0c21390190e1ccb91e61958ad6ecc9f9
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Error out if pause statement is used in device code (#203642)
Commit: 81a81d7fae4a16e0edfdb0273f5c376547e15841
https://github.com/llvm/llvm-project/commit/81a81d7fae4a16e0edfdb0273f5c376547e15841
Author: dpalermo <dan.palermo at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
Log Message:
-----------
Revert "[AMDGPU] In `LowerDYNAMIC_STACKALLOC`, hoist the `readfirstlane` up one instruction" (#203645)
Reverts llvm/llvm-project#201528
Reverting due to change causing "illegal VGPR to SGPR copy"
Commit: c9b25a6437fd97fdb1e55ab6661c0cccce98913e
https://github.com/llvm/llvm-project/commit/c9b25a6437fd97fdb1e55ab6661c0cccce98913e
Author: Hardik Chona <iamhardikchona at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/mkstemp_test.cpp
Log Message:
-----------
[libc] implement mkstemp (#199220)
Fixes #191266
Implements `mkstemp` as specified in POSIX
Currently Linux-only since it relies on the Linux syscall wrappers for
`getrandom` and `open`
Commit: 92d7a7fbbd7238222d8a0ef7b85b9300f832a4d5
https://github.com/llvm/llvm-project/commit/92d7a7fbbd7238222d8a0ef7b85b9300f832a4d5
Author: vsimion26 <vlad.simion at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/test/Dialect/Quant/Bytecode/types.mlir
Log Message:
-----------
QuantileType bytecode patch (#203495)
Since the merge of this
PR(https://github.com/llvm/llvm-project/pull/190321) there were some
issues identified, such as QuantileType not being added in the ByteCode
files. This PR focuses on fixing these missing pieces which should make
QuantileType a complete and functional type.
Commit: a8e3c083db160e2dc6f04b660b22b459e5167199
https://github.com/llvm/llvm-project/commit/a8e3c083db160e2dc6f04b660b22b459e5167199
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
Log Message:
-----------
[libc] fix EAGAIN being treated as timeout in mutex and rwlock (#203574)
fix #203411.
This PR addresses the problem that `EAGAIN` may be treated as timeout in
mutex and rwlock. Two changes are applied:
1. timeout sites always explicitly check for timeout now to make the
logic more robust;
2. the futex wait now discards the error of `EAGAIN/EWOULDBLOCK` and
returns 0;
We don't distinguish waking up from signal and waking up from mismatch
for the following 3 reasons:
- We have userspace guard to avoid futex syscall if we already know
value would match, it seems awkward to make that check returns error, as
we may wake up and loop back to the check, where signal is consumed but
we still return error....;
- futex syscall can spuriously wake up anyway, there is no way to tell
whether the signal is "indeed" consumed;
- other platforms like darwin does not distinguish these states either.
Assisted-by: Gemini powered automation tools (human-in-the-loop).
Commit: baf76a838f3da5fcbb5acbdc12f57b0ed79cc3ce
https://github.com/llvm/llvm-project/commit/baf76a838f3da5fcbb5acbdc12f57b0ed79cc3ce
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/perf2bolt/perf_test.test
Log Message:
-----------
[BOLT] Change DataAggregator error types (#203651)
1. In `filterBinaryMMapInfo`, replace `incovertibleErrorCode` with errc
code as `parseMainEvents` converts returned Error to std::error_code.
2. In `parsePerfData`, pass through Error returned by `prepareToParse`
for memory events.
Test Plan: updated perf_test.test
Commit: 6b82a0485dbd6a6a5006329f2fa5f4e8bc977488
https://github.com/llvm/llvm-project/commit/6b82a0485dbd6a6a5006329f2fa5f4e8bc977488
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-global-addr.mlir
Log Message:
-----------
[flang][cuda] Fix host loads from CUDA constant globals (#203064)
This fixes CUDA Fortran lowering for scalar module variables with the
constant attribute that are read from host code, such as launch
configuration expressions or CUF kernel loop bounds.
Previously, host-side declarations for these globals could be rewritten
to device constant-memory addresses, causing host loads to dereference
the result of _FortranACUFGetDeviceAddress. The fix preserves host reads
from the host-visible global while still using the device address for
host-to-device assignment updates.
A FIR regression test covers host reads and assignment updates for
scalar CUDA constant globals.
Commit: af60d56719aa770dda70d19f37b0451b222e89e4
https://github.com/llvm/llvm-project/commit/af60d56719aa770dda70d19f37b0451b222e89e4
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/cuf-generic-literal-host.cuf
A flang/test/Semantics/cuf28.cuf
Log Message:
-----------
[flang][CUDA] Keep host literals from using unified-memory generic distance (#201257)
Fix CUDA generic resolution under `-gpu=mem:unified` so unattributed
literals and expression temporaries are not treated as unified-memory
actuals.
Previously, a host scalar literal such as `1.0` could score as
compatible with a `DEVICE` dummy and incorrectly select the
device-scalar overload. This could pass a host stack address to a device
helper and fail at runtime. The fix applies the unified/managed memory
distance columns only to symbol-backed actuals.
Commit: 7670d88e7ea753095f753e6616b66f5e74da42ef
https://github.com/llvm/llvm-project/commit/7670d88e7ea753095f753e6616b66f5e74da42ef
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/test/Fir/CUDA/cuda-device-func-transform.mlir
Log Message:
-----------
[flang][cuda] Set kernel intent(in) as const __restrict__ (#203652)
Set attributes on `intent(in)` so `ld.global.nc` is generated by the
backend.
Commit: 0579490edf0599cc01e10885c2149d4cce8ec399
https://github.com/llvm/llvm-project/commit/0579490edf0599cc01e10885c2149d4cce8ec399
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/Intrinsics.cpp
A llvm/test/TableGen/intrinsic-overload-index-oor.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Log Message:
-----------
[NFC][LLVM] Refactor IIT_ANY payload for vector/element constraint (#203506)
Change `IIT_ANY` payload from a single packed OverloadIndex + AnyKind
byte to 2 bytes:
- An 8 bit OverloadIndex
- An 8 pit packed vector + element type constraint.
This will enable `IIT_ANY` to express constraints on the overload type
is a more general fashion compared to a flat `AnyKind` enum.
Also fixed a latent bug in fixed encodings generated by the intrinsic
emitter (exposed by this change). Existing `encodePacked` packs the
type-signature as 8 nibbles into a 32-bit word and then checks if the
MSB bit position (i.e., bit 15) is 0 (to allow it's use in fixed
encoding). This effectively drop any 0 valued bytes in the encoding in
the upper 4 nibbles. Fix this by changing `encodePacked` to use the
actual fixed encoding type and its size.
Commit: b8e34c5adc38b5406d175e7e94c95f6399da096a
https://github.com/llvm/llvm-project/commit/b8e34c5adc38b5406d175e7e94c95f6399da096a
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Improve diagnostic messages for invalidations (#203577)
Commit: 4e5fa3bbabdf304975abf9eea59bc44d72277169
https://github.com/llvm/llvm-project/commit/4e5fa3bbabdf304975abf9eea59bc44d72277169
Author: Sergey Stepanov <23sas32 at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
A llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
Log Message:
-----------
[RISCV] Mark HW shadow stack ops as frame setup/destroy (#203362)
This change follows up on PR #200182 and addresses the issue in the
[related
comment](https://github.com/llvm/llvm-project/pull/200182#discussion_r3329197379).
It sets `FrameSetup` on SSPUSH/C_SSPUSH and `FrameDestroy` on SSPOPCHK
instructions emitted by RISCVFrameLowering for the HW shadow stack path.
The test was written manually (instead of using
`utils/update_mir_test_checks.py`) to keep it simple and avoid
unnecessary fragility.
Commit: e3e2fd630f5969a6ee845a57e3be380331405e2e
https://github.com/llvm/llvm-project/commit/e3e2fd630f5969a6ee845a57e3be380331405e2e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
Log Message:
-----------
[RISCV] Add PseudoClearGPR to the special cases in RISCVInstrInfo::getInstSizeInBytes. (#203637)
This instruction is expanded to an ADDI with immediate of 0 and should
then be compressed to c.li with Zca. The compression code doesn't know
this due to the Pseudo so manually give a size of 2 for Zca.
Commit: 756ff7174c7e8e641d0c9270e9864f5ddefce5e6
https://github.com/llvm/llvm-project/commit/756ff7174c7e8e641d0c9270e9864f5ddefce5e6
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
Log Message:
-----------
[HLSL][NFC] Move HLSLBufferCopyEmitter class (#203595)
Move `HLSLBufferCopyEmitter` class to the anonymous namespace at the top
of `CGHLSLRuntime.cpp` and use it directly from
`CGHLSLRuntime::createBufferMatrixTempAddress` instead going though the
`CGHLSLRuntime::emitBufferCopy` call. No changes were done to the
`HLSLBufferCopyEmitter` code.
This is preparation for work related to resources in cbuffer structs
which will be changing the signature of `CGHLSLRuntime::emitBufferCopy`
and modifying the `HLSLBufferCopyEmitter`.
Commit: afeee229f5160fecf427571141165a4d97c93f00
https://github.com/llvm/llvm-project/commit/afeee229f5160fecf427571141165a4d97c93f00
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp-codesize.ll
Log Message:
-----------
[VectorCombine] Use TCK_CodeSize for size-optimized functions (#202207)
VectorCombine currently uses `TCK_RecipThroughput` for all functions,
including functions optimized for size.
Select `TCK_CodeSize` when `Function::hasOptSize()` is true, covering
both `-Os` (`optsize`) and `-Oz` (`minsize`), while retaining
`TCK_RecipThroughput` for the default optimization mode.
The X86 regression test demonstrates a sign-bit reduction where the
throughput cost model folds an `or` reduction into a `umax` reduction.
The code-size model preserves the smaller form for `optsize` and
`minsize` functions, while the default function retains the existing
throughput-oriented transformation.
Fixes #153375.
Commit: 08e6e1476b4d3273f95ef715391154be0a6881bc
https://github.com/llvm/llvm-project/commit/08e6e1476b4d3273f95ef715391154be0a6881bc
Author: Ilpo Ruotsalainen <lonewolf at iki.fi>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
Log Message:
-----------
[GlobalISel] Fix sign-extended byte mask in lowerBswap (#199387)
The per-byte mask in `LegalizerHelper::lowerBswap` was constructed via
```
APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
```
where `0xFF << (i * 8)` is evaluated as a signed `int`. For `i*8 >= 24`
(byte-3 mask of an s64 G_BSWAP) the value `0xFF000000` does not fit in a
positive 32-bit `int`; the conversion to signed `int` is
implementation-defined under C++17 (UB under C++11, fully defined under
C++20) and on two's-complement targets produces `-16777216`. The modular
conversion to `uint64_t` in the `APInt` constructor then materializes
that negative `int` as `0xFFFFFFFFFF000000` — the intended mask was
`0x00000000FF000000`. The over-wide mask preserved bytes 4-7 of the
source where only byte 3 was intended, and the spurious bytes propagated
through the subsequent shift/OR chain.
Use `APInt::getBitsSet` to construct the mask, matching the file's other
bit-range mask constructions.
Fixes #199386
Commit: 44cc7971ff6d87e924abaf1ff12599e91d077faf
https://github.com/llvm/llvm-project/commit/44cc7971ff6d87e924abaf1ff12599e91d077faf
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__memory/ranges_uninitialized_algorithms.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/version
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/ranges_uninitialized_default_construct.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/ranges_uninitialized_default_construct_n.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/uninitialized_default_construct.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/uninitialized_default_construct_n.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] P3369R0: constexpr for `uninitialized_default_construct` (#200163)
Remarks:
- Tests also verify that `uninitialized_default_construct(_n)`
algorithms do not initialize trivially default-constructible elements
(`int` in these tests) to determined values during constant evaluation.
Commit: 18a4c90c5191cb2bade557061ee4afa548468c1e
https://github.com/llvm/llvm-project/commit/18a4c90c5191cb2bade557061ee4afa548468c1e
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M libcxx/include/optional
M libcxx/test/std/utilities/optional/optional.monadic/and_then.pass.cpp
M libcxx/test/std/utilities/optional/optional.monadic/or_else.pass.cpp
M libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
Log Message:
-----------
[libc++] Fix bug where `optional<T&>` couldn't be constructed from `transform()` (#203462)
- Add the proper from monadic base constructor
- Fix the constraint so it allows references.
- Add tests
Commit: e63cd40ccce67f9472af9676185d7c87157043b4
https://github.com/llvm/llvm-project/commit/e63cd40ccce67f9472af9676185d7c87157043b4
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
Log Message:
-----------
[NVPTX] Rip out vestigial variadic support (NFC) (#202385)
Commit: 24faf90b03a16c248764fb7ab33d9e7cb1d39908
https://github.com/llvm/llvm-project/commit/24faf90b03a16c248764fb7ab33d9e7cb1d39908
Author: Justin Stitt <justinstitt at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/test/AST/undocumented-attrs.cpp
Log Message:
-----------
[Clang] Add AttrDocs entry for OverflowBehavior (#203392)
These docs were previously missing.
Fixes: #203322
Signed-off-by: Justin Stitt <justinstitt at google.com>
Commit: e602cd1acc04bd1a16a21d4d1d2d81037fa306f2
https://github.com/llvm/llvm-project/commit/e602cd1acc04bd1a16a21d4d1d2d81037fa306f2
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
Log Message:
-----------
[AMDGPU] Add a few wmma co-execution hazard checks, NFC (#203658)
This is to reflect the gfx1251 update regarding wmma*8f6f4 with
matrix format as F4.
Also fix a comment in GCNHazardRecognizer.cpp
Commit: caf98648e8767ba73facc14a0324045df597660c
https://github.com/llvm/llvm-project/commit/caf98648e8767ba73facc14a0324045df597660c
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrConstraints.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
A clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
A clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/NVPTX.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/SPIRV.cpp
M clang/test/CIR/IR/invalid-addrspace.cir
A clang/test/CIR/IR/invalid-opencl-kernel-arg-metadata.cir
A clang/test/CIR/IR/opencl-kernel-arg-metadata.cir
Log Message:
-----------
[CIR][OpenCL] Add kernel argument metadata attribute (#199530)
Add a CIR attribute that carries OpenCL kernel argument metadata in
source argument order. Verify that each metadata field has the expected
element type and that all present arrays describe the same number of
arguments.
Commit: e5afb8e0982c524ee79436a15fb7270d4b9436f3
https://github.com/llvm/llvm-project/commit/e5afb8e0982c524ee79436a15fb7270d4b9436f3
Author: agrieve <agrieve at chromium.org>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86Subtarget.cpp
M llvm/test/CodeGen/X86/call-imm.ll
Log Message:
-----------
[X86] Disallow immediate address calls when position independent (#202370)
Causes problems with mold linker, and was determined to be a compiler
bug. See:
See https://github.com/rui314/mold/pull/1601#issuecomment-4628653209
Commit: d0b899214d5ae364db6d24f4f3eafe9a5183b70e
https://github.com/llvm/llvm-project/commit/d0b899214d5ae364db6d24f4f3eafe9a5183b70e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt-c/Compiler.h
M orc-rt/include/orc-rt-c/CoreTypes.h
M orc-rt/include/orc-rt-c/Error.h
R orc-rt/include/orc-rt-c/ExternC.h
R orc-rt/include/orc-rt-c/Visibility.h
M orc-rt/include/orc-rt-c/WrapperFunction.h
Log Message:
-----------
[orc-rt] Merge ExternC.h and Visibility.h into Compiler.h. (#203673)
This mirrors the combined orc-rt/Compiler.h header on the C++ side, and
provides a natural home for future decoration macros when they're added.
Commit: 58c0dace6f0a230849910b92a97b00da4d04c2ec
https://github.com/llvm/llvm-project/commit/58c0dace6f0a230849910b92a97b00da4d04c2ec
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Compiler.h
M orc-rt/include/orc-rt-c/Error.h
M orc-rt/lib/executor/Error.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_C_NOTHROW and apply it to the Error C API. (#203674)
Adds an ORC_RT_C_NOTHROW macro that expands to `noexcept` in C++ mode,
and `__attribute__((nothrow))` where that attribute is supported.
Also applies the new ORC_RT_C_NOTHROW macro to orc-rt-c/Error.h (and
adds `noexcept` to the corresponding C++ implementation in
lib/executor/Error.cpp).
Commit: b76803b394ac4330dd7b14d1f866dd695f107fe9
https://github.com/llvm/llvm-project/commit/b76803b394ac4330dd7b14d1f866dd695f107fe9
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__locale
M libcxx/src/locale.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/codecvt_byname_char16_t_char8_t.depr_in_cxx20.verify.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/codecvt_byname_char32_t_char8_t.depr_in_cxx20.verify.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/ctor_char16_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/ctor_char32_t_char8_t.pass.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/codecvt_char16_t_char8_t.depr_in_cxx20.verify.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/codecvt_char32_t_char8_t.depr_in_cxx20.verify.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/ctor_char16_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/ctor_char32_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_always_noconv.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_encoding.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_in.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_max_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_out.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_unshift.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_always_noconv.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_encoding.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_in.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_max_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_out.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_unshift.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/types_char16_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/types_char32_t_char8_t.pass.cpp
Log Message:
-----------
[libc++] LWG3767: `codecvt<charN_t, char8_t, mbstate_t>` incorrectly added to locale (#201749)
Implement it as a DR against C++20, patching P0482R6.
Commit: 76e120e0bde5d1aa928ffd2e91e0276a24be365d
https://github.com/llvm/llvm-project/commit/76e120e0bde5d1aa928ffd2e91e0276a24be365d
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/www/cxx_status.html
Log Message:
-----------
[Clang][NFC] Add the list C++ papers approved in Brno by WG21 (#203685)
Commit: 9a3e91daa7798e8695a68b01a8ff9b76e54f8524
https://github.com/llvm/llvm-project/commit/9a3e91daa7798e8695a68b01a8ff9b76e54f8524
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-ptr-to-ptr-arg-alloca-store.ll
Log Message:
-----------
[SPIR-V] Preserve pointer-to-pointer element type for T*& parameters (#203113)
SPIR-V backend was collapsing T*& reference parameters down to T*,
dropping a level of indirection during element-type deduction. This
patch keeps the pointer-to-pointer level intact, fixing it both within a
function (a T** reloaded from its alloca) and across calls via
cross-function parameter propagation.
Fixes HeCBench/topk on HIP.
Commit: cbf3f87d6c950208ed95a5dcf4399b79e7e74baf
https://github.com/llvm/llvm-project/commit/cbf3f87d6c950208ed95a5dcf4399b79e7e74baf
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
M llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
M llvm/test/Analysis/CostModel/AMDGPU/fma.ll
M llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
M llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
A llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll
Log Message:
-----------
[AMDGPU] gfx1251 cost model (#203682)
Commit: 57109befac92811d2253109242ca6fa69c961fb2
https://github.com/llvm/llvm-project/commit/57109befac92811d2253109242ca6fa69c961fb2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/utils/lit/lit/formats/shtest.py
M llvm/utils/lit/tests/Inputs/per-test-coverage-by-lit-cfg/lit.cfg
M llvm/utils/lit/tests/Inputs/per-test-coverage/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-external-shell-kill/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-format/external_shell/lit.local.cfg
M llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/lit.local.cfg
M llvm/utils/lit/tests/Inputs/shtest-timeout/lit.cfg
Log Message:
-----------
Reapply "[lit] Deprecate execute_external=True in ShTest" (#203316) (#203689)
This reverts commit 6713634507b21efe6c895dd40e85ba72fe0ce269.
The fuzzer tests now use the internal shell by default, so we should be
good to go ahead and enable this.
Commit: 34802b90f3877abb71faf43ff80ffae985ab2672
https://github.com/llvm/llvm-project/commit/34802b90f3877abb71faf43ff80ffae985ab2672
Author: jofrn <jo7frn1 at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
Log Message:
-----------
[AtomicExpand][test] Add CHECK32 and CHECK64 via whole-file regen (#201303)
Add CHECK32 and CHECK64 via whole-file regen for the
`@load_v2i64_cmpxchg`, `@load_v4i32_cmpxchg`, `@load_v16i8_cmpxchg`
tests of https://github.com/llvm/llvm-project/pull/199310.
Stacked below https://github.com/llvm/llvm-project/pull/199520.
Commit: b48dd92d8e00b4a2940dd539722444bf0dd2ef65
https://github.com/llvm/llvm-project/commit/b48dd92d8e00b4a2940dd539722444bf0dd2ef65
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/lib/Parse/ParseOpenACC.cpp
A clang/test/ParserOpenACC/directive-scope-setup.cpp
R clang/test/ParserOpenACC/gh197858.cpp
Log Message:
-----------
[OpenACC] Fix scope setup for OpenACC directives without scope. (#203687)
When implementing these, I intended to have the 'empty' parse scopes for
most of the directives introduced for simplicity. However some
assertions show that this is not a valid use of this, as it doesn't
tolerate 'empty' parse scopes. This patch stops introducing one.
Fixes: #203679
Commit: e5cfc1ec130e9ef61fd64369353253f9da894887
https://github.com/llvm/llvm-project/commit/e5cfc1ec130e9ef61fd64369353253f9da894887
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/include/llvm/TargetParser/XtensaTargetParser.def
M llvm/include/llvm/TargetParser/XtensaTargetParser.h
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaProcessors.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/test/CodeGen/Xtensa/cpus.ll
A llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s
Log Message:
-----------
[Xtensa] Implement support of the ESP32S2 target. (#200130)
Commit: 76aed382055b0c07a9ce89d9273cc1f70daecf17
https://github.com/llvm/llvm-project/commit/76aed382055b0c07a9ce89d9273cc1f70daecf17
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/non-const-parameter.cpp
Log Message:
-----------
[clang-tidy] Avoid non-const-parameter fix-it conflicts with overloads (#202490)
`readability-non-const-parameter` can suggest changing `T *` to `const T
*` when that would conflict with an existing overload. Suppress the
diagnostic in that case by comparing the post-fix parameter list against
other declarations with the same name.
Closes https://github.com/llvm/llvm-project/issues/202478
Commit: 94b46a0ded3aebfa13c0fb63e5637df34a87efbd
https://github.com/llvm/llvm-project/commit/94b46a0ded3aebfa13c0fb63e5637df34a87efbd
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/include/llvm/Passes/MachinePassRegistry.def
Log Message:
-----------
[Passes] Remove redundant IR pass registries in MachinePassRegistry.def (#203659)
IR pass registries are redundant, remove them.
Commit: cf004c900376a60386d8cc7c643ea07cd61217e9
https://github.com/llvm/llvm-project/commit/cf004c900376a60386d8cc7c643ea07cd61217e9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.format.pass.cpp
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/parse.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.vformat.pass.cpp
Log Message:
-----------
[libcxx] Do not mark mkstemp tests xfail for libc (#203681)
mkstemp was recently implemented in
c9b25a6437fd97fdb1e55ab6661c0cccce98913e, so these tests now pass.
Commit: 5b3a9ac949aba6e062bcd9062cb8c0f2eaf7f776
https://github.com/llvm/llvm-project/commit/5b3a9ac949aba6e062bcd9062cb8c0f2eaf7f776
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.h
Log Message:
-----------
[clang][bytecode] Handle more types in `canClassify()` (#203669)
Avoid having to go through the normal `classify()` path.
Commit: eb23fddeb4e93b294f9c5db14dee577b14295c22
https://github.com/llvm/llvm-project/commit/eb23fddeb4e93b294f9c5db14dee577b14295c22
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Replace std::initializer_list SupportedOp with a C array
Fixes a static_assert constant-expression build failure on older clang
(temporary initializer_list backing array).
Fixes #203184
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/203707
Commit: a815e6f267c12417757743a95fdc89cc3cde4499
https://github.com/llvm/llvm-project/commit/a815e6f267c12417757743a95fdc89cc3cde4499
Author: Timur Golubovich <timur.golubovich at intel.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/test/Transforms/LoopStrengthReduce/X86/reuse-existing-phi.ll
M llvm/test/Transforms/LoopStrengthReduce/funclet.ll
Log Message:
-----------
[Test] Fix LSR tests to prevent trivial simplification of icmp (#203705)
Replace undef operands in funclet.ll with function parameters and adjust
the loop bound in reuse-existing-phi.ll so the new simplification pass
does not fold away the comparisons these tests are meant to exercise.
Commit: d0e87f95a6fd6b5aa9e46c5ef86f1e6080c04742
https://github.com/llvm/llvm-project/commit/d0e87f95a6fd6b5aa9e46c5ef86f1e6080c04742
Author: mike-goutokuji <gfunni234 at gmail.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
Log Message:
-----------
[X86] Fix Sandy Bridge's WriteLDMXCSR (#203585)
Using information from uops.info, I corrected some numbers.
Commit: e61071dda770c05e91319a46eef97e2bf9e9f007
https://github.com/llvm/llvm-project/commit/e61071dda770c05e91319a46eef97e2bf9e9f007
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
Log Message:
-----------
[VPlan] Run final removeBranchOnConst after late simplifyRecipes. (#193069)
simplifyRecipes may expose additional known branches. Move final
removeBranchOnConst after the late simplifyRecipes run.
Removing branches like the vector loop backedge leads to additional
simplifications, like removing trivial phis etc. Return true if any phis
have incoming values have been removed by removeBranchOnConst. If so, we
need another simplifyRecipes run.
Depends on https://github.com/llvm/llvm-project/pull/193067 for
functional changes.
PR: https://github.com/llvm/llvm-project/pull/193069
Commit: 8ba6fb1bf23748d58224db9df5b0ee7ddd257055
https://github.com/llvm/llvm-project/commit/8ba6fb1bf23748d58224db9df5b0ee7ddd257055
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/include/clang/AST/CXXRecordDeclDefinitionBits.def
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/Type.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/AST/HLSL/ConstantBuffers-AST-error.hlsl
A clang/test/AST/HLSL/StructPassing-AST.hlsl
M clang/test/AST/HLSL/cbuffer.hlsl
M clang/test/AST/HLSL/matrix-constructors.hlsl
M clang/test/AST/HLSL/semantic-output-struct-shadow.hlsl
M clang/test/AST/HLSL/semantic-output-struct.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/StructElementwiseCast.hlsl
A clang/test/CodeGenHLSL/BasicFeatures/StructPassing.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
M clang/test/CodeGenHLSL/builtins/hlsl_resource_t.hlsl
M clang/test/CodeGenHLSL/cbuffer_copy_layout.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-subscripts.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.hlsl
M clang/test/CodeGenHLSL/resources/resources-in-structs.hlsl
M clang/test/CodeGenHLSL/semantics/semantic-struct-2-output.hlsl
M clang/test/CodeGenHLSL/this-assignment-overload.hlsl
M clang/test/CodeGenHLSL/this-assignment.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveAllTrue-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveAnyTrue-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveBallot-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/dot4add_u8packed-errors.hlsl
M clang/test/SemaHLSL/Language/AggregateSplatCast-errors.hlsl
M clang/test/SemaHLSL/Language/ElementwiseCast-errors.hlsl
M clang/test/SemaHLSL/Language/ElementwiseCasts.hlsl
M clang/test/SemaHLSL/Language/InitListAST.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
M clang/test/SemaHLSL/prohibit_pointer.hlsl
Log Message:
-----------
[HLSL] Disable implicit constructors for user-defined structs/classes (#194989)
Disables implicit constructors and assignment operators on user-defined
structs/classes in HLSL.
When a struct is copied or passed as an argument to a function, instead
of using copy constructor the compiler inserts an implicit
_lvalue_-to-_rvalue_ cast where necessary to copy the value. In C++
these implicit casts are not allowed. Sema initialization and
overloading code has been adjusted to enable this code path for HLSL.
For struct in a constant buffer, the implicit cast changes the constant
address space to the default one. Codegen recognized this pattern and
instead of translating the copy as `memcpy`, it copies the struct
element-by-element (because the constant address space struct can have a
different layout).
To efficiently recognize whether a `CXXRecordDecl` is a user-defined
struct/class or if it is an HLSL built-in struct/class, a new bit
`IsHLSLBuiltinRecord` has been added to the `CXXRecordDecl` definition
data. This property is set for struct/classes created in
`HLSLExternalSemaSource`.
Part of #185466
Fixes #153055
Commit: f7b674930f468562b9e41481217ef4e1ed431e1b
https://github.com/llvm/llvm-project/commit/f7b674930f468562b9e41481217ef4e1ed431e1b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
Log Message:
-----------
[LV] Allow AddChainWithSubs in ExtNegatedMulAccReduction. (#203720)
For chained reductions identified as RecurKind::AddChainWithSubs, VPlan
construction rewrites each sub link as 0 - X so that the in-loop
reduction can treat the chain uniformly as a sum. The
ExtNegatedMulAccReduction VPExpressionRecipe matches that 0 - mul form,
but its constructor only allowed RecurKind::Add and asserted otherwise,
crashing with -prefer-inloop-reductions on the added tests.
AddChainWithSubs maps to Instruction::Add via
RecurrenceDescriptor::getOpcode, so the rest of the recipe (cost
computation, codegen) already handles it. Relax the constructor assert
to also accept AddChainWithSubs.
Commit: c6012943c60d0a106e03d4e38e12fd66d8e69ddf
https://github.com/llvm/llvm-project/commit/c6012943c60d0a106e03d4e38e12fd66d8e69ddf
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP][NFC]Add a test with the unsupported runtime checks
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/203728
Commit: 8796d370aed0153ce884319c2365530e92b9bf5e
https://github.com/llvm/llvm-project/commit/8796d370aed0153ce884319c2365530e92b9bf5e
Author: Govind Malasani <gmalasan at andrew.cmu.edu>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/IterationGraphSorter.cpp
A mlir/test/Dialect/SparseTensor/sparse_loop_ordering.mlir
Log Message:
-----------
[MLIR][SparseTensor] Added Sparse Outer Loop Ordering Strategy (#172198)
This PR builds upon the infrastructure set up for Sparse Tensor Loop
Ordering Heuristics (#154656) and the already existing Dense Outer loop
ordering strategy (#160168).
Commit: ae1c5074a0c6ec128fe824d456314e547b57165a
https://github.com/llvm/llvm-project/commit/ae1c5074a0c6ec128fe824d456314e547b57165a
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
Log Message:
-----------
[mlir][sparse_tensor] Fix out-of-bounds read in SparseAssembleOpConverter (#203289)
The assemble codegen loop iterates over the level rank but asserted on
`getDimShape()[lvl]`, which is sized by the dimension rank. Index the
level shape instead, matching the loop bound and the next line.
Fixes #203225.
Commit: a72232481fe7d87056dae9b89d8c2580323a9f39
https://github.com/llvm/llvm-project/commit/a72232481fe7d87056dae9b89d8c2580323a9f39
Author: dyung <douglas.yung at sony.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/test/Driver/hexagon-toolchain-picolibc.c
M clang/test/Driver/hip-include-path.hip
M clang/test/Preprocessor/iwithprefix.c
Log Message:
-----------
Update remaining tests for usage of CLANG_RESOURCE_DIR (#202475)
We would like to enable the clang CMake option CLANG_RESOURCE_DIR on our
build bots, but found that a few tests that need updating since they
make assumptions about compiler paths that are modified when using
CLANG_RESOURCE_DIR. This is the final change to update the remaining 3
test failures we found.
In the previous change (#197154), I added a definition for
`%clang-resource-dir` which contains the path printed by the compiler
when run with `-print-resource-dir`. We pass that value to the remaining
tests where needed through the RUN lines and use that to verify the
correct path rather than just trying to guess at it using a complex
regex.
One exception was a test which uses `-###` which escapes the backslashes
on Windows. For that test I just used tr+sed to escape the backslashes so
that the matching would work in that particular test only.
Commit: 3a46e59c2bf4db22cc22ef8a92d459c34c696731
https://github.com/llvm/llvm-project/commit/3a46e59c2bf4db22cc22ef8a92d459c34c696731
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
A clang/test/CodeGen/ubsan-aggregate-null-align-bounds.c
R clang/test/CodeGen/ubsan-aggregate-null-align.c
Log Message:
-----------
[NFC][tests] Rename test file and function names to reflect scope/content (#203731)
Rename test file to reflect scope (includes array bounds checking).
Rename test functions for internal convention consistency:
Consistently use "deref" and "subscript" to refer to `*p` and `arr[idx]`
expression forms.
Commit: e84e480bb5a53c794f303683df6460ddb44bb7ac
https://github.com/llvm/llvm-project/commit/e84e480bb5a53c794f303683df6460ddb44bb7ac
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/test/Fir/CUDA/cuda-device-func-transform.mlir
Log Message:
-----------
Revert "[flang][cuda] Set kernel intent(in) as const __restrict__" (#203734)
Reverts llvm/llvm-project#203652
breaking some downstream cudafor code
Commit: f7f904f96107dd59a06d8bc58f888befcfafd2b4
https://github.com/llvm/llvm-project/commit/f7f904f96107dd59a06d8bc58f888befcfafd2b4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll
Log Message:
-----------
[SLP][NFC]Add a test with miscompiled ordered reductions, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/203738
Commit: 5db7e5b483a32f37d1d77a6f18d2bc4c59fa460a
https://github.com/llvm/llvm-project/commit/5db7e5b483a32f37d1d77a6f18d2bc4c59fa460a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-replaced.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll
Log Message:
-----------
[SLP]Keep ordered fadd reductions sequential
tryToReduceOrdered vectorizes reductions that are not associative (e.g. an
fadd with reassoc but without nsz). The accumulation order must be
preserved, but the reduction was costed and emitted with reassoc, and the
whole tree was rotated to memory order by reorderTopToBottom, which can
change the result of the sequential reduction.
Drop reassoc from the flags used to cost and emit the reduction so the
generated llvm.vector.reduce.fadd stays ordered, and drop the top-to-bottom
reorder so the reduced values keep their original accumulation order.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/203741
Commit: 9d43f86e6f302604b109ffa9df7de793aeb801d8
https://github.com/llvm/llvm-project/commit/9d43f86e6f302604b109ffa9df7de793aeb801d8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/test/tools/llubi/alloca.ll
M llvm/test/tools/llubi/attributes.ll
M llvm/test/tools/llubi/gep.ll
M llvm/test/tools/llubi/inttoptr.ll
A llvm/test/tools/llubi/inttoptr_freed.ll
A llvm/test/tools/llubi/inttoptr_generation.ll
A llvm/test/tools/llubi/inttoptr_generation2.ll
A llvm/test/tools/llubi/inttoptr_gep.ll
A llvm/test/tools/llubi/inttoptr_multiobj.ll
A llvm/test/tools/llubi/inttoptr_multiobj2.ll
A llvm/test/tools/llubi/inttoptr_oob.ll
A llvm/test/tools/llubi/inttoptr_oob2.ll
M llvm/test/tools/llubi/lib_abort.ll
M llvm/test/tools/llubi/lib_exit.ll
M llvm/test/tools/llubi/lib_io.ll
M llvm/test/tools/llubi/lib_printf_format.ll
M llvm/test/tools/llubi/lib_terminate.ll
M llvm/test/tools/llubi/loadstore_be.ll
M llvm/test/tools/llubi/loadstore_le.ll
M llvm/test/tools/llubi/metadata.ll
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Context.h
M llvm/tools/llubi/lib/ExecutorBase.cpp
M llvm/tools/llubi/lib/ExecutorBase.h
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/lib/Library.cpp
M llvm/tools/llubi/lib/Value.cpp
M llvm/tools/llubi/lib/Value.h
Log Message:
-----------
[llubi] Add support for exposed provenance (#200596)
This patch implements the semantics of exposed provenance, as described
in [nikic's RFC draft](https://hackmd.io/@nikic/SJBt4mFCll) and
[Miri](https://doc.rust-lang.org/beta/nightly-rustc/miri/enum.Provenance.html).
The provenance of an inttoptr is marked as "wildcard", which picks one
from previously exposed provenances each time a memory access is
performed. For angelic non-determinism, a snapshot of the exposed
provenance set is recorded when inttoptr executes. When a memory access
is performed, all invalid provenances are masked out. If we fail to pick
one, it is UB.
Since all memory objects in llubi are non-overlapping (i.e., there is at
most one memory object satisfying `Obj->inBounds(Addr)` for each
address), we can determine a unique memory object for a wildcard
provenance when the first memory access is performed.
This matches Miri's behavior. Another variant is to resolve the memory
object when inttoptr executes, which gives a limited provenance set
(implemented in the second commit). See also the comments in nikic's RFC
(`For example, one could limit inttoptr to only recover the provenance
of an object that the address is part of.`).
Another thing to be noted is that `gep inbounds` cannot determine the
associated memory object of a wildcard provenance, because it doesn't
cause UB. Instead, I reuse the Obj field to represent something like
`this pointer has a wildcard provenance, but it is only allowed to use
exposed provenances associated with a specific memory object, when
performing load/store via the pointer`. This is an approximation: we
cannot update the wildcard provenance if the gep is used by an icmp and
a branch.
As we don't support `captures` for now, all checkers just return true.
I'll add more tests in the `captures` patch.
Commit: 4331c07e8a8d398daf2204b6c4085f992b343308
https://github.com/llvm/llvm-project/commit/4331c07e8a8d398daf2204b6c4085f992b343308
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M libcxx/include/optional
Log Message:
-----------
[libc++][NFC] Simplify `optional<T>` and `optional<T&>` a bit (#203665)
- Make `optional<T&>`'s iterator base directly from the storage base
instead of inheriting the empty bases, allowing us to remove the
`is_lvalue_reference_v` conditions in the empty bases
- Move the `__is_constructible_for_optional_{meow}` variables closer to
`make_optional` since that's the only place they're really useful for
now
- Change the SFINAE for the iterator availability to use concepts
instead
The above should make it easier to split up in an upcoming patch.
Commit: 0a2565d7c6dd196eceb8c93befde1150d78790b7
https://github.com/llvm/llvm-project/commit/0a2565d7c6dd196eceb8c93befde1150d78790b7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Use `isSignedType()` in `pushInteger` (#203670)
We need to classify here anyway, so use the information from the
primtype.
Commit: db210c5e33643a8154329a607b5b6dcd419271df
https://github.com/llvm/llvm-project/commit/db210c5e33643a8154329a607b5b6dcd419271df
Author: Shanzhi Chen <chenshanzhi at huawei.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/ProfileSummaryInfo.h
Log Message:
-----------
[NFC] Prefer compile-time branching in function template (#203698)
Commit: beadaec428a65a901be47964619121cc5b889635
https://github.com/llvm/llvm-project/commit/beadaec428a65a901be47964619121cc5b889635
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/test/tools/llubi/global_constexpr_initializer.ll
A llvm/test/tools/llubi/unsupported_constant.ll
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Context.h
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/lib/Value.h
Log Message:
-----------
[llubi] Add support for constant expressions (#203746)
This patch adds support for most kinds of constant expressions, except
for ptrtoint/inttoptr. Casting between pointers and integers is
stateful, so they cannot be cached. I plan to implement them in
subsequent patches. ptrtoaddr is also supported in this patch to block
constant folding.
The logic in `evaluateConstantExpression` duplicates the interpreter's
code in `visit*` methods. But I think it is acceptable. Only the GEP
computation is reused.
Commit: 86543b7a7c3c737f5680f9cb0e2277fe1c23f336
https://github.com/llvm/llvm-project/commit/86543b7a7c3c737f5680f9cb0e2277fe1c23f336
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll
Log Message:
-----------
[LV] Add additional tests for narrowing IGs with invariant ops (NFC). (#203726)
Add test where operands are different live-ins.
Commit: 6d25dcecf8bbc4f3e0246af8f3c6d6e9f70b85d4
https://github.com/llvm/llvm-project/commit/6d25dcecf8bbc4f3e0246af8f3c6d6e9f70b85d4
Author: Zhige Chen <zhigec_cpp at outlook.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
A llvm/test/tools/llubi/ptrtoaddr.ll
A llvm/test/tools/llubi/ptrtoaddr_after_ptrtoint.ll
A llvm/test/tools/llubi/ptrtoaddr_no_expose.ll
M llvm/tools/llubi/lib/Interpreter.cpp
Log Message:
-----------
[llubi] Implement ptrtoaddr (#203771)
This PR implements the `ptrtoaddr` instruction.
Commit: e19d1f51a2c80b63cd8ca95bcc757b7077112808
https://github.com/llvm/llvm-project/commit/e19d1f51a2c80b63cd8ca95bcc757b7077112808
Author: Walter <90877047+WalterKruger at users.noreply.github.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/gfni-xor-fold-avx512.ll
M llvm/test/CodeGen/X86/gfni-xor-fold.ll
Log Message:
-----------
[X86] Fold XOR of two VGF2P8AFFINEQB instructions with same matrix (#199146)
Adds an optimization to fold a XOR between two `vgf2p8affineqb`
instructions that share the same matrix by XORing their sources
beforehand. This patch:
- Can eliminate one `vgf2p8affineqb` instruction.
- Doesn't occur if either affine is multi use, preventing an increase in code size.
- Includes test coverage for both positive and negative cases.
Fixes #196879
Commit: a44231fd3f7a3d11d8a9fe666ed926e0efd891a5
https://github.com/llvm/llvm-project/commit/a44231fd3f7a3d11d8a9fe666ed926e0efd891a5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Lower the paadd/pasub intrinsics to existing ISD nodes. NFC (#203646)
This avoids having 2 different isel patterns for the same operation.
Commit: f58495a213b48f6fbd636eb8b41cfeb26da74b03
https://github.com/llvm/llvm-project/commit/f58495a213b48f6fbd636eb8b41cfeb26da74b03
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
Log Message:
-----------
[RISCV] Remove manual compression of SSPUSH in RISCVFrameLowering.cpp. NFC (#203635)
We used to emit a Zcmop instruction here, which required manual
compression. Since we now emit a Zicfiss instruction, we can rely on
CompressPat to do the right thing.
Commit: f683de4ee14074af6046c13f4db07c55450e3ef7
https://github.com/llvm/llvm-project/commit/f683de4ee14074af6046c13f4db07c55450e3ef7
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Add an LLVM ABI-breaking checks build setting (#203739)
Commit: eda662faf49d1a0cb81e724993d2fdc123b4b693
https://github.com/llvm/llvm-project/commit/eda662faf49d1a0cb81e724993d2fdc123b4b693
Author: Tuhil <63782260+Tuhil926 at users.noreply.github.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M flang/docs/Intrinsics.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/getarg.f90
A flang/test/Lower/Intrinsics/iargc.f90
A flang/test/Semantics/test-iargc-getarg.f90
Log Message:
-----------
[flang] Add support for the IARGC and GETARG legacy intrinsics (#196425)
Adds semantic checking and lowering, along with semantic and lowering
tests for the legacy GNU intrinsics 'IARGC()' and 'GETARG(POS, VALUE)'.
Although these could just be added as aliases to the standard
COMMAND_ARGUMENT_COUNT and GET_COMMAND_ARGUMENT intrinsics, they were
implemented as separate intrinsics because of some semantic differences
between them:
* IARGC always returns INTEGER(4), whereas COMMAND_ARGUMENT_COUNT
returns a default INTEGER, which could have a different kind.
* GETARG has only two arguments, both of which are required.
* GETARG's POS argument accepts any integer type of width less than or
equal to the default integer kind, while GET_COMMAND_ARGUMENT only
accepts default integers.
Fixes #158438
Commit: a53a62dace4adad245571cf989eeddca32108eb0
https://github.com/llvm/llvm-project/commit/a53a62dace4adad245571cf989eeddca32108eb0
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
Log Message:
-----------
[Github] Remove unnecessary packages from github-automation container (#203358)
This cuts the container size from 654 MB to 229 MB. This is mainly due
to removing the python3-pip package which was pulling in some big
depedencies like gcc.
A smaller container will be faster to download which will speed up the
workflow runs, but also, having less packages means smaller attack
surface for the container.
Commit: 3e11b3be3b86d4e72e73e610fb15fe431169f16e
https://github.com/llvm/llvm-project/commit/3e11b3be3b86d4e72e73e610fb15fe431169f16e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/fork.test
M compiler-rt/test/fuzzer/fork_corpus_groups.test
Log Message:
-----------
[Fuzzer] Bump max RSS in fork tests (#203688)
These became flaky on at least one buildbot after enabling the internal
shell by default:
1. https://lab.llvm.org/buildbot/#/builders/174/builds/36874
2. https://lab.llvm.org/buildbot/#/builders/174/builds/36876
Try bumping the max RSS to see if that helps.
Commit: 3df63e9edfc08d293f7b4232f3897c5d1cb16a2e
https://github.com/llvm/llvm-project/commit/3df63e9edfc08d293f7b4232f3897c5d1cb16a2e
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/use-old-text-zero-padding.c
Log Message:
-----------
[BOLT] Zero alignment padding when reusing old text section (#202375)
With --use-old-text, the output starts as a byte-for-byte copy of the
input. Alignment padding between sections could retain stale data from
the original binary. Zero the padding so the result matches writing
sections to new file offsets.
Commit: 80b1dddb5a24c5a09865357db0173260d8132ac0
https://github.com/llvm/llvm-project/commit/80b1dddb5a24c5a09865357db0173260d8132ac0
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
Log Message:
-----------
[LV] Drop the mask of a predicated store masked by the header mask. (#201676)
Drop the mask of a predicated store masked by the header mask (which is
guaranteed to be true at least for the first lane) and both the stored
value and the address are uniform across VF and UF.
An similar version for loads was included in
https://github.com/llvm/llvm-project/pull/196630, but restricted the
uniform-across-vfs-and-ufs did not have impact in practice.
For stores, this results in some improvements after
https://github.com/llvm/llvm-project/pull/196632.
PR: https://github.com/llvm/llvm-project/pull/201676
Commit: f7e53fc7fa5fc2cc9250b6a46b943c10380a112d
https://github.com/llvm/llvm-project/commit/f7e53fc7fa5fc2cc9250b6a46b943c10380a112d
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M offload/liboffload/src/OffloadImpl.cpp
Log Message:
-----------
[offload] Fix olMemcpy error message typo (#197273)
Commit: ad7119873fbb8814140f446ebaeaae4d47ad1a81
https://github.com/llvm/llvm-project/commit/ad7119873fbb8814140f446ebaeaae4d47ad1a81
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
Log Message:
-----------
[LV] Add outer-loop tests for continuous access analysis. (NFC) (#203789)
Add outer loop tests with different strided accesses.
Commit: 71f69c19ae1a2887cb642695e574eab9e23708cf
https://github.com/llvm/llvm-project/commit/71f69c19ae1a2887cb642695e574eab9e23708cf
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Use ResumeForEpilogue for header phi resume in epilogue plan (NFC) (#203786)
Pass the ResumeForEpilogue VPInstructions created by
preparePlanForMainVectorLoop into preparePlanForEpilogueVectorLoop and
get the resume IR from ResumeForEpilogue::getUnderlyingValue()
Commit: cc613052fd6afe2e3522c18234e382588069441d
https://github.com/llvm/llvm-project/commit/cc613052fd6afe2e3522c18234e382588069441d
Author: jofrn <jo7frn1 at gmail.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
Log Message:
-----------
[X86] Remove shouldCastAtomicLoadInIR; use DAG combine instead (#199520)
Remove X86's shouldCastAtomicLoadInIR override that cast FP atomic loads
to integer at the IR level. Instead, handle this in a pre-legalize DAG
combine (combineAtomicLoad) that rewrites FP/FP-vector atomic loads to
integer atomic loads plus a bitcast.
This and #199310, which adds the necessary cmpxchg support for
non-integer atomic loads in AtomicExpand, are a response to
https://github.com/llvm/llvm-project/pull/148899 for `atomic_vec4_float`
of `atomic-load-store.ll`.
Stacked above #201303.
Commit: 86d7405f428e0cf4cdeba55babbcd111ab499370
https://github.com/llvm/llvm-project/commit/86d7405f428e0cf4cdeba55babbcd111ab499370
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M lldb/source/Symbol/Symbol.cpp
M lldb/source/Symbol/Symtab.cpp
Log Message:
-----------
[lldb] Add static asserts on Symbol size to DataFileCache (#203735)
DataFileCache is a serialization to disk of a Symtab - the symbol names
and array of Symbol objects - so if the contents of the Symbol object
change, the serialization may need to change as well, and we need to
bump the DataFileCache version number to avoid misparsing an older
format.
It's also a little too easy to change Symbol and not notice that
Symbol::Encode/Decode and Symtab::Encode/Decode need to be updated.
static_asserting the size of Symbol isn't perfect, but as long as we're
doing it in Symbol.h already to warn anyone increasing the size of this
object, I want to use the same technique to make sure people look at
these other sites that are tied to the contents.
Commit: 6966cf3f7120f5068d811b439ac431f7af6c6e6d
https://github.com/llvm/llvm-project/commit/6966cf3f7120f5068d811b439ac431f7af6c6e6d
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Clarify the `nsz` semantic for `{u,s}itofp` (#201557)
`nsz` has special semantic in `{u,s}itofp`, which falls into the "unless
otherwise mentioned" in `nsz` doc, this PR clarifies it in LangRef.
Commit: 19d343debcbc47b1d9b2e2117a599130c33c547c
https://github.com/llvm/llvm-project/commit/19d343debcbc47b1d9b2e2117a599130c33c547c
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/add.ll
M llvm/test/CodeGen/X86/apx/and.ll
M llvm/test/CodeGen/X86/apx/cmov.ll
M llvm/test/CodeGen/X86/apx/dec.ll
M llvm/test/CodeGen/X86/apx/imul.ll
M llvm/test/CodeGen/X86/apx/inc.ll
M llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/neg.ll
M llvm/test/CodeGen/X86/apx/not.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/apx/rol.ll
M llvm/test/CodeGen/X86/apx/ror.ll
M llvm/test/CodeGen/X86/apx/sar.ll
M llvm/test/CodeGen/X86/apx/sbb.ll
M llvm/test/CodeGen/X86/apx/shl.ll
M llvm/test/CodeGen/X86/apx/shld.ll
M llvm/test/CodeGen/X86/apx/shr.ll
M llvm/test/CodeGen/X86/apx/shrd.ll
M llvm/test/CodeGen/X86/apx/sub.ll
M llvm/test/CodeGen/X86/apx/xor.ll
M llvm/test/CodeGen/X86/cmp.ll
Log Message:
-----------
[X86][APX] Remove prefer-ndd-imm tuning (#203758)
It turns out NDD's immediate variants perform as good as non-NDD's on
real hardware. Verified both on CPU2017 and CPU2026, the geomean is
around 0 w/ and w/o this change. A few items get up and down due to the
side effect of register live range change caused by the NDD form. No
evidence shows this tuning has improvements or degradations even on
single items.
Assisted-by: Claude Sonnet 4.6
Commit: 375b70bafedafa71fabfb0e8b1e759daeef0f703
https://github.com/llvm/llvm-project/commit/375b70bafedafa71fabfb0e8b1e759daeef0f703
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M libclc/clc/lib/amdgpu/CMakeLists.txt
A libclc/clc/lib/amdgpu/math/clc_recip_fast.cl
A libclc/clc/lib/amdgpu/math/clc_recip_fast.inc
M libclc/clc/lib/generic/CMakeLists.txt
Log Message:
-----------
[libclc] Improve performance and precision of reciprocal functions (#203805)
Summary:
Small change to improve the performance and output of functions using
the reciprocol. This makes these functions *byte-for-byte* identical
with their OCML counterparts in ROCm.
Additionally ensure tanpi is correctly rounded to match ROCm.
Commit: bf0ccb40170c8cbf0e0510ca344b79ddc338b64b
https://github.com/llvm/llvm-project/commit/bf0ccb40170c8cbf0e0510ca344b79ddc338b64b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-lto-defaults.ll
Log Message:
-----------
[Passes] Invoke CGSCCOptimizerLateEP callbacks in LTO pipeline (#203262)
The CGSCCOptimizerLateEP extension point was not being invoked in the
LTO pipeline. Right now only AMDGPU registers any passes during this
callback, but it was a real source of delta between the LTO and default
pipelines when targeting AMDGPU. This doesn't seem to be an intentional
omission given that it is instantiated in thinLTO as well. Just add it.
Commit: 8b6551e49395be0dc878e7acff1edd31f4204143
https://github.com/llvm/llvm-project/commit/8b6551e49395be0dc878e7acff1edd31f4204143
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_acos.inc
M libclc/clc/lib/generic/math/clc_atan.inc
Log Message:
-----------
[libclc] Use FMA for the pi reconstruction in acos / atan (#203804)
Summary:
This should recombine the split constant for this case. The performance
should be negligible for such large math functions, we get an extra add,
but in exchange the results should improve 1 ULP.
This was primarily done to match what AMD's math libraries do, with this
change we are byte-for-byte identical in output.
Commit: 303400f0809a808d0f478c05eeaf0073d6fa149a
https://github.com/llvm/llvm-project/commit/303400f0809a808d0f478c05eeaf0073d6fa149a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_sincos_helpers_fp64.inc
Log Message:
-----------
[libclc] Use __CLC_SCALAR instead of nonexistant __CLC_SCALAR1 for sin (#203807)
Summary:
This seems to be a typo? Every other case is guarded by `__CLC_SCALAR`
but this case had a `1` after it. Removing this improved performance on
sin/cos/tan to match the ROCm version.
Commit: e79e056ee982450ee75477d1b315b2f747d7790c
https://github.com/llvm/llvm-project/commit/e79e056ee982450ee75477d1b315b2f747d7790c
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M mlir/lib/Transforms/Utils/CSE.cpp
Log Message:
-----------
[mlir][CSE] Remove the opsToErase container and immediately delete dead ops. (#203702)
This PR removes the `opsToErase` container and immediately erases dead
operations. Since dead ops are deleted on the fly, the value in the
`MemEffectsCache` map now correctly tracks the previous operation of
`toOp`. This change improves the storage efficiency of CSE. Furthermore,
it is part of https://github.com/llvm/llvm-project/pull/180556 and
substantially simplifies the implementation.
Commit: 31f998d6a25ce5dea6999c533f265f8a89074b48
https://github.com/llvm/llvm-project/commit/31f998d6a25ce5dea6999c533f265f8a89074b48
Author: hev <wangrui at loongson.cn>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
A llvm/test/CodeGen/LoongArch/crc.ll
Log Message:
-----------
[LoongArch][NFC] Add demanded bits tests for CRC[C].W.{B,H}.W (#203200)
Commit: 9f2035d27cb534ab7be6fe3e41603eba74e66df5
https://github.com/llvm/llvm-project/commit/9f2035d27cb534ab7be6fe3e41603eba74e66df5
Author: Luke Lau <luke at igalia.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
Log Message:
-----------
[VPlan] Move tail folding logic out of addMiddleCheck. NFC (#203475)
We simplify the TripCount == VectorTrip count condition with tail
folding, but we can just do that in foldTailByMasking and keep the
logic in one place instead.
Commit: 569c21a4a5fd24b14a05bf9e8ea08a3694fbb0d3
https://github.com/llvm/llvm-project/commit/569c21a4a5fd24b14a05bf9e8ea08a3694fbb0d3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp
M mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Fix empty optional deref in spirv.Switch verifier (#203561)
Commit: e413f6e780a932606b0ba48d7bf61ba5724c48b8
https://github.com/llvm/llvm-project/commit/e413f6e780a932606b0ba48d7bf61ba5724c48b8
Author: hev <wangrui at loongson.cn>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/crc.ll
Log Message:
-----------
[LoongArch] Propagate demanded bits for CRC[C].W.{B,H}.W (#203201)
CRC byte and halfword instructions only use the low 8 or 16 bits of
their data operand. Propagate these demanded-bit requirements through
SimplifyDemandedBitsForTargetNode() so redundant masking operations can
be removed during DAG combining.
Commit: 838f7f71ca3db152551b3f385438ff266d886c62
https://github.com/llvm/llvm-project/commit/838f7f71ca3db152551b3f385438ff266d886c62
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpUtils.h
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/test/Dialect/SPIRV/IR/structure-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Enforce physical storage buffer pointer decorations on GlobalVariable (#203600)
Enable the rule that was already enforced by spirv.Variable (in case of
SPV_KHR_physical_storage_buffer ext) requiring exactly one of
AliasedPointer/RestrictPointer
Commit: ee5856d8a8353f7bcb2c62f75711e30b0f8c9c45
https://github.com/llvm/llvm-project/commit/ee5856d8a8353f7bcb2c62f75711e30b0f8c9c45
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M mlir/lib/Conversion/IndexToSPIRV/IndexToSPIRV.cpp
M mlir/test/Conversion/IndexToSPIRV/index-to-spirv.mlir
Log Message:
-----------
[mlir][SPIR-V] Add OpenCL lowering path for index.min/max (#203493)
GLSL min/max ops were emitted even for Kernel targets where these ops
are illegal
Commit: 625facd4375f6bfa5de501d0559bd262062e2dc3
https://github.com/llvm/llvm-project/commit/625facd4375f6bfa5de501d0559bd262062e2dc3
Author: Thirumalai Shaktivel <74826228+Thirumalai-Shaktivel at users.noreply.github.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M flang/test/Driver/compiler-options.f90
M flang/tools/flang-driver/driver.cpp
Log Message:
-----------
[Flang] Store only options in FLANG_COMPILER_OPTIONS_STRING (#201278)
Previously, FLANG_COMPILER_OPTIONS_STRING stored every argument passed
to the flang driver, including input file names. The GNU extension
compiler_options() is documented to return only the options, not the
input files. Including the input files also caused the string to exceed
ARG_MAX on large builds, producing:
posix_spawn failed: Argument list too long
Use the driver's parsed InputArgList to filter out OPT_INPUT arguments,
preserving all options and their values (e.g. `-I /path`, `-o file`).
Fixes: https://github.com/llvm/llvm-project/issues/170651
Commit: 8106136012b933c4674c4f72f0b2a61a8b7eaa71
https://github.com/llvm/llvm-project/commit/8106136012b933c4674c4f72f0b2a61a8b7eaa71
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Support/Z3Solver.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
M llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
M llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp
M llvm/tools/llvm-exegesis/lib/SubprocessMemory.h
M llvm/tools/llvm-objdump/SourcePrinter.h
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.h
M llvm/unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp
M llvm/unittests/tools/llvm-exegesis/X86/SubprocessMemoryTest.cpp
M llvm/utils/TableGen/DFAPacketizerEmitter.cpp
Log Message:
-----------
[llvm] Replace unordered_map<std::string, T> with StringMap (#203815)
Prefer StringMap to the slow unordered_map per ProgrammersManual.
Commit: f211ea13e59b589fad35ee93a752c7ec19c284ba
https://github.com/llvm/llvm-project/commit/f211ea13e59b589fad35ee93a752c7ec19c284ba
Author: Luke Lau <luke at igalia.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Don't calculate VPDT in non-side-effect early exit loops. NFC (#203476)
Follow up from
https://github.com/llvm/llvm-project/pull/203233/changes/BASE..6c916678df65787d524558919cee233bf2329aa8#r3398107262
Commit: 8714a0179e83808916520c64c5e9d0c4f17baa04
https://github.com/llvm/llvm-project/commit/8714a0179e83808916520c64c5e9d0c4f17baa04
Author: Yashwant Singh <yashwants at nvidia.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
R llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
Log Message:
-----------
[AArch64] Use sve for 64 wide masked load/store (#203480)
Commit: 05c8f9b1ead844024f414f45ab9ba11757bef2ea
https://github.com/llvm/llvm-project/commit/05c8f9b1ead844024f414f45ab9ba11757bef2ea
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
A clang/test/AST/ByteCode/codegen-cxx2a.cpp
Log Message:
-----------
[clang][bytecode] Overide constant context state in CallVar (#203747)
We do this for regular calls, so do it for variable calls as well. Also
remove two comments that don't have any meaning today anymore.
Commit: b113f5b4e27dd726515a8e22bf02a6d911dd6691
https://github.com/llvm/llvm-project/commit/b113f5b4e27dd726515a8e22bf02a6d911dd6691
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-14 (Sun, 14 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/tools/flang-driver/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 625facd (#203814)
This fixes 625facd4375f6bfa5de501d0559bd262062e2dc3.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: c775d6e52b3340fa4669cfae8d1a83d968db7747
https://github.com/llvm/llvm-project/commit/c775d6e52b3340fa4669cfae8d1a83d968db7747
Author: Braden Ganetsky <10316270+k3DW at users.noreply.github.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M libcxx/include/print
Log Message:
-----------
[libc++] Make the body of println(FILE*) dependent on the template parameter to avoid template instantiation (#200996)
Make the function parameter of the `std::print` call inside the
`std::println` overload taking `FILE*` dependent on the template
parameter to avoid eager instantiation.
Commit: 6f916feb8ba799f78c252907b6d659dae64039c6
https://github.com/llvm/llvm-project/commit/6f916feb8ba799f78c252907b6d659dae64039c6
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M clang/docs/tools/dump_ast_matchers.py
Log Message:
-----------
[ASTMatchers][Docs] print ignoring message only when class was not documented before (#203783)
Commit: 08940b5399e4a8e475085b270b92f05867e77202
https://github.com/llvm/llvm-project/commit/08940b5399e4a8e475085b270b92f05867e77202
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/ClangTidyCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/MacroParenthesesCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/MoveForwardingReferenceCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/NotNullTerminatedResultCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ParentVirtualCallCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/UseAfterMoveCheck.cpp
M clang-tools-extra/clang-tidy/llvmlibc/InlineFunctionDeclCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/misc/MisplacedConstCheck.cpp
M clang-tools-extra/clang-tidy/misc/NoRecursionCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertUtils.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertUtils.h
M clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
M clang-tools-extra/clang-tidy/performance/MoveConstArgCheck.cpp
M clang-tools-extra/clang-tidy/performance/UnnecessaryCopyInitializationCheck.cpp
M clang-tools-extra/clang-tidy/readability/ConvertMemberFunctionsToStaticCheck.cpp
M clang-tools-extra/clang-tidy/readability/ElseAfterReturnCheck.cpp
M clang-tools-extra/clang-tidy/readability/EnumInitialValueCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/utils/FileExtensionsUtils.cpp
M clang-tools-extra/clang-tidy/utils/FileExtensionsUtils.h
M clang-tools-extra/clang-tidy/utils/FormatStringConverter.cpp
M clang-tools-extra/clang-tidy/utils/UseRangesCheck.cpp
Log Message:
-----------
[clang-tidy][NFC] Apply const-correctness to code (#203823)
Commit: 568122adff14a16b2ee9dd4e196b69cd438c3cfd
https://github.com/llvm/llvm-project/commit/568122adff14a16b2ee9dd4e196b69cd438c3cfd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain.c
A clang/test/Driver/amdgpu-xnack-sramecc-flags.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-features.hip
M clang/test/Driver/target-id.cl
Log Message:
-----------
clang/AMDGPU: Split out target ID flags in TranslateArgs. (#203750)
Change how xnack and sramecc are processed. Introduce
-mxnack/-mno-xnack and -msramecc/-mno-sramecc flags.
When the target is first parsed in TranslateArgs, synthesize
the appropriate flag for the toolchain. This avoids
special case feature string fixups in getAMDGPUTargetFeatures,
and also avoids an extra parse of the target ID.
In the future this will also simplify tracking these ABI
modifiers in a module flag.
As a side-effect, you can use these flags to override the
no specifier case with the flags. These do not fully replace
the target ID syntax, as there's no way to represent compiling
both modes for the same subtarget.
I didn't bother trying to forward these flags on the main command
line without being specified to the offload device, but I suppose
that would be possible.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
Commit: ad611b62095e55a1fa534ccbac99603ba02634a9
https://github.com/llvm/llvm-project/commit/ad611b62095e55a1fa534ccbac99603ba02634a9
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/test/CodeGen/X86/abi-isel.ll
Log Message:
-----------
[X86] Do not hold GOT base for indirect call or absolute address (#203192)
Fixes:
https://github.com/llvm/llvm-project/pull/202370#discussion_r3384983368
Assisted-by: Claude Sonnet 4.6
Commit: c236ef51d8dcf9b4c2f060d6c92a1f4d97143a57
https://github.com/llvm/llvm-project/commit/c236ef51d8dcf9b4c2f060d6c92a1f4d97143a57
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/CFIFixup.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CFIFixup.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
M llvm/test/CodeGen/AArch64/cfi-fixup.mir
Log Message:
-----------
[CodeGen][NewPM] Port cfi-fixup to new pass manager (#203692)
Standard work for `cfi-fixup`.
Commit: 774f486e44ab198e689e226e75d6de908559a066
https://github.com/llvm/llvm-project/commit/774f486e44ab198e689e226e75d6de908559a066
Author: Rana Pratap Reddy <RanaPratapReddy.Nimmakayala at amd.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-extended-image.hip
Log Message:
-----------
[CIR][AMDGPU] Adds lowering for amdgcn extended image sample/gather4 builtins (#201761)
Support for lowering of` __builtin_amdgcn_image_sample/gather4` for
AMDGPU builtins to clangIR.
Followed similar lowering from clang->llvmir:
`clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp`.
Upstreaming clangIR PR:
[llvm/clangir#2083](https://github.com/llvm/clangir/pull/2083)
Commit: 57a5646bf7750f18576f719fd7227c9bd2006fa2
https://github.com/llvm/llvm-project/commit/57a5646bf7750f18576f719fd7227c9bd2006fa2
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/Heatmap.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/use-old-text-zero-padding.c
M bolt/test/X86/heatmap-preagg.test
M bolt/test/perf2bolt/perf_test.test
M clang-tools-extra/clang-tidy/ClangTidyCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/MacroParenthesesCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/MoveForwardingReferenceCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/NotNullTerminatedResultCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ParentVirtualCallCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/UseAfterMoveCheck.cpp
M clang-tools-extra/clang-tidy/llvmlibc/InlineFunctionDeclCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/misc/MisplacedConstCheck.cpp
M clang-tools-extra/clang-tidy/misc/NoRecursionCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertUtils.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertUtils.h
M clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
M clang-tools-extra/clang-tidy/performance/MoveConstArgCheck.cpp
M clang-tools-extra/clang-tidy/performance/UnnecessaryCopyInitializationCheck.cpp
M clang-tools-extra/clang-tidy/readability/ConvertMemberFunctionsToStaticCheck.cpp
M clang-tools-extra/clang-tidy/readability/ElseAfterReturnCheck.cpp
M clang-tools-extra/clang-tidy/readability/EnumInitialValueCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
M clang-tools-extra/clang-tidy/utils/FileExtensionsUtils.cpp
M clang-tools-extra/clang-tidy/utils/FileExtensionsUtils.h
M clang-tools-extra/clang-tidy/utils/FormatStringConverter.cpp
M clang-tools-extra/clang-tidy/utils/UseRangesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/non-const-parameter.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/tools/dump_ast_matchers.py
M clang/include/clang/AST/CXXRecordDeclDefinitionBits.def
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrConstraints.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
A clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/NVPTX.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/SPIRV.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/Targets/SystemZ.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
A clang/test/AST/ByteCode/codegen-cxx2a.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/HLSL/ConstantBuffers-AST-error.hlsl
A clang/test/AST/HLSL/StructPassing-AST.hlsl
M clang/test/AST/HLSL/cbuffer.hlsl
M clang/test/AST/HLSL/matrix-constructors.hlsl
M clang/test/AST/HLSL/semantic-output-struct-shadow.hlsl
M clang/test/AST/HLSL/semantic-output-struct.hlsl
A clang/test/AST/tyloctype_alignment.cpp
M clang/test/AST/undocumented-attrs.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-extended-image.hip
M clang/test/CIR/IR/invalid-addrspace.cir
A clang/test/CIR/IR/invalid-opencl-kernel-arg-metadata.cir
A clang/test/CIR/IR/opencl-kernel-arg-metadata.cir
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
R clang/test/CodeGen/AArch64/poly-add.c
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
M clang/test/CodeGen/X86/avx512f-builtins-constrained-cmp.c
A clang/test/CodeGen/ubsan-aggregate-null-align-bounds.c
R clang/test/CodeGen/ubsan-aggregate-null-align.c
M clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/StructElementwiseCast.hlsl
A clang/test/CodeGenHLSL/BasicFeatures/StructPassing.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
M clang/test/CodeGenHLSL/builtins/hlsl_resource_t.hlsl
M clang/test/CodeGenHLSL/cbuffer_copy_layout.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-subscripts.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.hlsl
M clang/test/CodeGenHLSL/resources/resources-in-structs.hlsl
M clang/test/CodeGenHLSL/semantics/semantic-struct-2-output.hlsl
M clang/test/CodeGenHLSL/this-assignment-overload.hlsl
M clang/test/CodeGenHLSL/this-assignment.hlsl
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain.c
A clang/test/Driver/amdgpu-xnack-sramecc-flags.c
M clang/test/Driver/hexagon-toolchain-picolibc.c
M clang/test/Driver/hip-include-path.hip
M clang/test/Driver/hip-profile-rocm-runtime.hip
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-features.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/target-id.cl
M clang/test/Format/lit.local.cfg
A clang/test/ParserOpenACC/directive-scope-setup.cpp
R clang/test/ParserOpenACC/gh197858.cpp
M clang/test/Preprocessor/iwithprefix.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
A clang/test/Sema/LifetimeSafety/inapplicable-lifetimebound.cpp
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/lifetime-facts.cpp
M clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-cross-tu.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-macro.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/noescape-violation.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
M clang/test/SemaHLSL/BuiltIns/WaveActiveAllTrue-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveAnyTrue-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveBallot-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/dot4add_u8packed-errors.hlsl
M clang/test/SemaHLSL/Language/AggregateSplatCast-errors.hlsl
M clang/test/SemaHLSL/Language/ElementwiseCast-errors.hlsl
M clang/test/SemaHLSL/Language/ElementwiseCasts.hlsl
M clang/test/SemaHLSL/Language/InitListAST.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
M clang/test/SemaHLSL/prohibit_pointer.hlsl
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
M clang/www/cxx_status.html
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/fork.test
M compiler-rt/test/fuzzer/fork_corpus_groups.test
M compiler-rt/test/fuzzer/lit.cfg.py
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
M flang/docs/Intrinsics.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Driver/compiler-options.f90
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/mem2reg.mlir
A flang/test/Lower/Intrinsics/getarg.f90
A flang/test/Lower/Intrinsics/iargc.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Semantics/OpenMP/linear-clause01.f90
A flang/test/Semantics/cuf-generic-literal-host.cuf
M flang/test/Semantics/cuf09.cuf
A flang/test/Semantics/cuf28.cuf
A flang/test/Semantics/test-iargc-getarg.f90
M flang/tools/flang-driver/driver.cpp
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/mkstemp_test.cpp
M libclc/clc/lib/amdgpu/CMakeLists.txt
A libclc/clc/lib/amdgpu/math/clc_recip_fast.cl
A libclc/clc/lib/amdgpu/math/clc_recip_fast.inc
M libclc/clc/lib/generic/CMakeLists.txt
M libclc/clc/lib/generic/math/clc_acos.inc
M libclc/clc/lib/generic/math/clc_atan.inc
M libclc/clc/lib/generic/math/clc_sincos_helpers_fp64.inc
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__locale
M libcxx/include/__memory/ranges_uninitialized_algorithms.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/optional
M libcxx/include/print
M libcxx/include/version
M libcxx/src/locale.cpp
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.format.pass.cpp
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.vformat.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/codecvt_byname_char16_t_char8_t.depr_in_cxx20.verify.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/codecvt_byname_char32_t_char8_t.depr_in_cxx20.verify.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/ctor_char16_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/ctor_char32_t_char8_t.pass.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/codecvt_char16_t_char8_t.depr_in_cxx20.verify.cpp
A libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/codecvt_char32_t_char8_t.depr_in_cxx20.verify.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/ctor_char16_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/ctor_char32_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_always_noconv.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_encoding.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_in.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_max_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_out.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_unshift.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_always_noconv.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_encoding.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_in.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_max_length.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_out.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_unshift.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/types_char16_t_char8_t.pass.cpp
M libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/types_char32_t_char8_t.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtstr/parse.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.format.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.vformat.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/ranges_uninitialized_default_construct.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/ranges_uninitialized_default_construct_n.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/uninitialized_default_construct.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/uninitialized_default_construct_n.pass.cpp
M libcxx/test/std/utilities/optional/optional.monadic/and_then.pass.cpp
M libcxx/test/std/utilities/optional/optional.monadic/or_else.pass.cpp
M libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M lldb/source/Symbol/Symbol.cpp
M lldb/source/Symbol/Symtab.cpp
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/ADT/StringExtras.h
M llvm/include/llvm/Analysis/ProfileSummaryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/CFIFixup.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/TargetParser/XtensaTargetParser.def
M llvm/include/llvm/TargetParser/XtensaTargetParser.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/CFIFixup.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/lib/Support/Z3Solver.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/lib/Target/X86/X86Subtarget.cpp
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaProcessors.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
M llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
M llvm/test/Analysis/CostModel/AMDGPU/fma.ll
M llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
M llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
A llvm/test/Analysis/ValueTracking/known-non-zero-shr-add.ll
A llvm/test/Bitcode/byte-constants.ll
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
M llvm/test/CodeGen/AArch64/cfi-fixup.mir
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-assign.ll
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-value-arglist.ll
A llvm/test/CodeGen/DirectX/DebugInfo/di-commonblock.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
A llvm/test/CodeGen/LoongArch/crc.ll
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
A llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-ptr-to-ptr-arg-alloca-store.ll
M llvm/test/CodeGen/X86/abi-isel.ll
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/add.ll
M llvm/test/CodeGen/X86/apx/and.ll
M llvm/test/CodeGen/X86/apx/cmov.ll
M llvm/test/CodeGen/X86/apx/dec.ll
M llvm/test/CodeGen/X86/apx/imul.ll
M llvm/test/CodeGen/X86/apx/inc.ll
M llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/neg.ll
M llvm/test/CodeGen/X86/apx/not.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/apx/rol.ll
M llvm/test/CodeGen/X86/apx/ror.ll
M llvm/test/CodeGen/X86/apx/sar.ll
M llvm/test/CodeGen/X86/apx/sbb.ll
M llvm/test/CodeGen/X86/apx/shl.ll
M llvm/test/CodeGen/X86/apx/shld.ll
M llvm/test/CodeGen/X86/apx/shr.ll
M llvm/test/CodeGen/X86/apx/shrd.ll
M llvm/test/CodeGen/X86/apx/sub.ll
M llvm/test/CodeGen/X86/apx/xor.ll
M llvm/test/CodeGen/X86/call-imm.ll
M llvm/test/CodeGen/X86/cmp.ll
M llvm/test/CodeGen/X86/gfni-xor-fold-avx512.ll
M llvm/test/CodeGen/X86/gfni-xor-fold.ll
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/Xtensa/cpus.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/COFF/seh-unwindv3-error.s
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
A llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s
M llvm/test/Other/new-pm-lto-defaults.ll
A llvm/test/TableGen/intrinsic-overload-index-oor.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
R llvm/test/Transforms/LICM/vector-insert.ll
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/reuse-existing-phi.ll
M llvm/test/Transforms/LoopStrengthReduce/funclet.ll
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
A llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
A llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
M llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/MergeICmps/X86/no-gep-other-work.ll
M llvm/test/Transforms/MergeICmps/X86/opaque-ptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-replaced.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
A llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp-codesize.ll
A llvm/test/tools/dxil-dis/dbg-assign.ll
A llvm/test/tools/dxil-dis/dbg-value-arglist.ll
A llvm/test/tools/dxil-dis/di-commonblock.ll
M llvm/test/tools/llubi/alloca.ll
M llvm/test/tools/llubi/attributes.ll
M llvm/test/tools/llubi/gep.ll
M llvm/test/tools/llubi/global_constexpr_initializer.ll
M llvm/test/tools/llubi/inttoptr.ll
A llvm/test/tools/llubi/inttoptr_freed.ll
A llvm/test/tools/llubi/inttoptr_generation.ll
A llvm/test/tools/llubi/inttoptr_generation2.ll
A llvm/test/tools/llubi/inttoptr_gep.ll
A llvm/test/tools/llubi/inttoptr_multiobj.ll
A llvm/test/tools/llubi/inttoptr_multiobj2.ll
A llvm/test/tools/llubi/inttoptr_oob.ll
A llvm/test/tools/llubi/inttoptr_oob2.ll
M llvm/test/tools/llubi/lib_abort.ll
M llvm/test/tools/llubi/lib_exit.ll
M llvm/test/tools/llubi/lib_io.ll
M llvm/test/tools/llubi/lib_printf_format.ll
M llvm/test/tools/llubi/lib_terminate.ll
M llvm/test/tools/llubi/loadstore_be.ll
M llvm/test/tools/llubi/loadstore_le.ll
M llvm/test/tools/llubi/metadata.ll
A llvm/test/tools/llubi/ptrtoaddr.ll
A llvm/test/tools/llubi/ptrtoaddr_after_ptrtoint.ll
A llvm/test/tools/llubi/ptrtoaddr_no_expose.ll
A llvm/test/tools/llubi/unsupported_constant.ll
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Context.h
M llvm/tools/llubi/lib/ExecutorBase.cpp
M llvm/tools/llubi/lib/ExecutorBase.h
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/lib/Library.cpp
M llvm/tools/llubi/lib/Value.cpp
M llvm/tools/llubi/lib/Value.h
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
M llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
M llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp
M llvm/tools/llvm-exegesis/lib/SubprocessMemory.h
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-objdump/SourcePrinter.h
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.h
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
M llvm/unittests/ADT/BitsetTest.cpp
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
M llvm/unittests/Support/GlobPatternTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
M llvm/unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp
M llvm/unittests/tools/llvm-exegesis/X86/SubprocessMemoryTest.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/TableGen/DFAPacketizerEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/MC/BUILD.gn
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/lit/formats/shtest.py
M llvm/utils/lit/tests/Inputs/per-test-coverage-by-lit-cfg/lit.cfg
M llvm/utils/lit/tests/Inputs/per-test-coverage/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-external-shell-kill/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-format/external_shell/lit.local.cfg
M llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/lit.local.cfg
M llvm/utils/lit/tests/Inputs/shtest-timeout/lit.cfg
M llvm/utils/lit/tests/substitutions.py
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/IndexToSPIRV/IndexToSPIRV.cpp
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpUtils.h
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/IterationGraphSorter.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/CSE.cpp
M mlir/test/Conversion/IndexToSPIRV/index-to-spirv.mlir
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
M mlir/test/Dialect/Quant/Bytecode/types.mlir
M mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
M mlir/test/Dialect/SPIRV/IR/structure-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
A mlir/test/Dialect/SparseTensor/sparse_loop_ordering.mlir
M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
A mlir/test/IR/test-func-erase-arg-error.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/IR/TestFunc.cpp
M offload/liboffload/src/OffloadImpl.cpp
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt-c/Compiler.h
M orc-rt/include/orc-rt-c/CoreTypes.h
M orc-rt/include/orc-rt-c/Error.h
R orc-rt/include/orc-rt-c/ExternC.h
R orc-rt/include/orc-rt-c/Visibility.h
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/lib/executor/Error.cpp
M utils/bazel/llvm-project-overlay/flang/tools/flang-driver/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kasuga-fj/da-add-test-addrec-wrap-gcdmiv
Compare: https://github.com/llvm/llvm-project/compare/e170fb1c8f53...57a5646bf775
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