[all-commits] [llvm/llvm-project] dbe91f: [CIR][AArch64] Lower NEON vslid intrinsics (#199415)

[Jiahao Guo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbe91f4a4b55a17197c52335db4b7a0aa9c69f6b
      https://github.com/llvm/llvm-project/commit/dbe91f4a4b55a17197c52335db4b7a0aa9c69f6b
  Author: Jiahao Guo <eoonguo at gmail.com>
  Date:   2026-06-05 (Fri, 05 Jun 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
    M clang/test/CodeGen/AArch64/neon-intrinsics.c
    M clang/test/CodeGen/AArch64/neon/intrinsics.c

  Log Message:
  -----------
  [CIR][AArch64] Lower NEON vslid intrinsics (#199415)

### summary

part of: https://github.com/llvm/llvm-project/issues/185382

this is a follow up of :
https://github.com/llvm/llvm-project/pull/198309

This adds CIR lowering for the scalar AArch64 NEON shift-left-and-insert
intrinsics `vslid_n_s64` and `vslid_n_u64`.

These ACLE builtins expose scalar `i64` interfaces, but the
corresponding LLVM intrinsic is vector-shaped:

  ```llvm
  llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) -> <1 x i64>
  ```
  
The new lowering wraps the scalar 64-bit operands in one-lane CIR vector
types, emits the aarch64.neon.vsli LLVM
intrinsic call, and bitcasts the result back to the scalar return type.



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