[all-commits] [llvm/llvm-project] a7a53b: [lldb][RISCV] Handle subsets of CSRs in RV32 core ...

[Ayush Sahay via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a7a53bfbcff401dbc9df5544b7662a7f96ce7336
      https://github.com/llvm/llvm-project/commit/a7a53bfbcff401dbc9df5544b7662a7f96ce7336
  Author: Ayush Sahay <asahay at qti.qualcomm.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M lldb/include/lldb/Target/DynamicRegisterInfo.h
    M lldb/source/Plugins/Process/Utility/CMakeLists.txt
    A lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
    A lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
    M lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
    M lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
    M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
    M lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
    M lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
    M lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
    M lldb/source/Utility/RISCV_DWARF_Registers.h
    M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
    A lldb/test/API/functionalities/postmortem/elf-core/riscv32-imcxqcixqccmp.gpr_csr.core
    A lldb/test/API/functionalities/postmortem/elf-core/riscv32-imcxqcixqccmp.gpr_csr.out

  Log Message:
  -----------
  [lldb][RISCV] Handle subsets of CSRs in RV32 core dump images (#142932)

The standard RISC-V ISA sets aside a 12-bit encoding space for up to
4,096 CSRs. However, many of these may remain unutilized and needn't be
saved in core dump images. To address this, we've come up with a new
note, _NT_CSREGMAP_, that saves subsets of CSRs as key-value pairs. This
change provisions support for handling the subsets of CSRs saved in
32-bit RISC-V core dump images by building the register information for
GPRs, FPRs, and CSRs dynamically.

Kindly refer to the corresponding topic ([Add RISC-V CSRs to core
dumps](https://discourse.llvm.org/t/add-risc-v-csrs-to-core-dumps/84348))
for additional details.



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