[all-commits] [llvm/llvm-project] 14299e: [AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to ...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/restrict_luti6_z0_z7
  Home:   https://github.com/llvm/llvm-project
  Commit: 14299e148cd450fc254a02532b164b6ae6fca4f6
      https://github.com/llvm/llvm-project/commit/14299e148cd450fc254a02532b164b6ae6fca4f6
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-06-03 (Wed, 03 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s

  Log Message:
  -----------
  [AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7

The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.


  Commit: 932aff7105ca33e8181ad52507f5ebd8c408c3df
      https://github.com/llvm/llvm-project/commit/932aff7105ca33e8181ad52507f5ebd8c408c3df
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-06-03 (Wed, 03 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td

  Log Message:
  -----------
  fixup! Address CR comments


  Commit: d3b5f2e57d649e0d3a40648d2e545abe240d0fcd
      https://github.com/llvm/llvm-project/commit/d3b5f2e57d649e0d3a40648d2e545abe240d0fcd
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-06-03 (Wed, 03 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  fixup! Address more CR comments


Compare: https://github.com/llvm/llvm-project/compare/f78d2a600ac9...d3b5f2e57d64

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