[all-commits] [llvm/llvm-project] e6d46f: [VPlan] Expand DerivedIV into executable recipes (...

[Ramkumar Ramachandra via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e6d46f16ab54e9994c5616adb9e62cbd44a01458
      https://github.com/llvm/llvm-project/commit/e6d46f16ab54e9994c5616adb9e62cbd44a01458
  Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
  Date:   2026-04-29 (Wed, 29 Apr 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
    M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/CodeGen/AArch64/aggressive-interleaving.ll
    M llvm/test/Transforms/LoopLoadElim/versioning-scev-invalidation.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-runtime-checks.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
    M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
    M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
    M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/cast-costs.ll
    M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
    M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
    M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-hoist-load-across-store.ll
    M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
    M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
    M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr39160.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
    M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
    M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
    M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
    M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
    M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
    M llvm/test/Transforms/LoopVectorize/consec_no_gep.ll
    M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
    M llvm/test/Transforms/LoopVectorize/debugloc.ll
    M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
    M llvm/test/Transforms/LoopVectorize/find-last-iv-interleave.ll
    M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-interleave-only.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/float-induction.ll
    M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
    M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
    M llvm/test/Transforms/LoopVectorize/induction.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-gep-nowrap-flags.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-requiring-scev-predicates.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
    M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
    M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
    M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
    M llvm/test/Transforms/LoopVectorize/metadata.ll
    M llvm/test/Transforms/LoopVectorize/narrow-interleave-groups-scalable-vf.ll
    M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
    M llvm/test/Transforms/LoopVectorize/pr128062-interleaved-accesses-narrow-group.ll
    M llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
    M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
    M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
    M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
    M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
    M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
    M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
    M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
    M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
    M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
    M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
    M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
    M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
    M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
    M llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll

  Log Message:
  -----------
  [VPlan] Expand DerivedIV into executable recipes (#187589)

This allows us to strip DerivedIVRecipe::execute, and remove the
dependency on emitTransformedIndex. It allows us to benefit from
existing simplifications in VPlan.



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