[all-commits] [llvm/llvm-project] a68f6a: [AArch64][GlobalISel] Selet SQDMLSLv1i64_indexed w...

[Joshua Rodriguez via All-commits]

  Branch: refs/heads/users/JoshdRod/add-sqdmlal-patterns
  Home:   https://github.com/llvm/llvm-project
  Commit: a68f6a881d8d8ed18f0790c24119e91f5e42b4d2
      https://github.com/llvm/llvm-project/commit/a68f6a881d8d8ed18f0790c24119e91f5e42b4d2
  Author: Josh Rodriguez <josh.rodriguez at arm.com>
  Date:   2026-03-24 (Tue, 24 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vmul.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Selet SQDMLSLv1i64_indexed when vector_extract present

Like SQDMLALv1i64_indexed, selecting this intrinsic reduces the number of instructions generated by 1, as it performs both the vector extract and the sqdmlal in one instruction.

This only works when the vector to extract from is v4i32, not v2i32. This is due to some issues GlobalISel has selecting intrinsics using v2i32.



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