[all-commits] [llvm/llvm-project] 6b6efc: [RISCV] Add sp register as implicit/implicit-def r...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b6efcd743ee692cd86e1885f7ba2e621c2eaf45
      https://github.com/llvm/llvm-project/commit/6b6efcd743ee692cd86e1885f7ba2e621c2eaf45
  Author: Jim Lin <jim at andestech.com>
  Date:   2026-02-11 (Wed, 11 Feb 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir

  Log Message:
  -----------
  [RISCV] Add sp register as implicit/implicit-def register to save/restore call (#180667)

This is a follow-up PR for
https://github.com/llvm/llvm-project/pull/180133.



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