[all-commits] [llvm/llvm-project] c3b6f1: [RISCV] Remove explicitly adding spilled registers...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c3b6f14a89f518288dfdafbf711827c9ffb4adc5
      https://github.com/llvm/llvm-project/commit/c3b6f14a89f518288dfdafbf711827c9ffb4adc5
  Author: Jim Lin <jim at andestech.com>
  Date:   2026-02-11 (Wed, 11 Feb 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

  Log Message:
  -----------
  [RISCV] Remove explicitly adding spilled registers as liveins. (#180483)

We didn't explicitly add spilled registers as liveins for CM_PUSH as
well. The liveins of the basic block will be updated by updateLiveness
in PrologEpilogInserter.



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