[all-commits] [llvm/llvm-project] f134b8: [RISCV] Refactor the MC layer SiFive VCIX classes....

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f134b802ee5ec127f178dd0c93de40f7e83a1c27
      https://github.com/llvm/llvm-project/commit/f134b802ee5ec127f178dd0c93de40f7e83a1c27
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-02-10 (Tue, 10 Feb 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

  Log Message:
  -----------
  [RISCV] Refactor the MC layer SiFive VCIX classes. (#180433)

My initial goal was to name bits {19-15} as either rs1, vs1, or imm as
appropriate.

The VCIX instructions effectively have 3 properties that are combined:
the type of bits 19-15 (determined by funct3), how many vector registers
are sources (determined by funct6), and whether vd is a written or not
(determined by vm).

I found the VCIXInfo class very hard to read and understand. This patch
breaks it up into simpler steps and moves some properties to flags in
the existing VCIXType classs. A new VCIXRs1Info class is added to
contain the properties for bits 19-15. The VCIXInfo now combines the
properties from these 2 classes and the HaveOutputDst flag to create the
various things needed to build the final instruction. To reduce the
number of template arguments, the VCIXInfo is passed all the way down to
the base class.

Much of the refactoring in this patch was accomplished with AI. I have
looked at the diffs in the output tablegen files to verify it works as
expected. RISCVGenInstrInfo.inc only changes line number comments.
RISCVGenDisassembler.inc doesn't change at all as expected.
RISCVGenMCCodeEmitter.inc changes due to the different field names and
orders in the record.



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