[all-commits] [llvm/llvm-project] b9107b: [RISCV] Support zilsd-4byte-align for i64 load/sto...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9107bfc1faa8aa74e736169626e0cf7eb0925ba
      https://github.com/llvm/llvm-project/commit/b9107bfc1faa8aa74e736169626e0cf7eb0925ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-11-22 (Sat, 22 Nov 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
    M llvm/test/CodeGen/RISCV/zilsd.ll

  Log Message:
  -----------
  [RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182)

I think we need to keep the SelectionDAG code for volatile load/store so
we should support 4 byte alignment when possible.



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