[all-commits] [llvm/llvm-project] bd1561: [RISCV][GISel] Add manual isel for s8/s16/s32 load...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd1561d5f160a949c0bbf9bfbda3558eb62f98d7
      https://github.com/llvm/llvm-project/commit/bd1561d5f160a949c0bbf9bfbda3558eb62f98d7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td

  Log Message:
  -----------
  [RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)

GISel doesn't distinquish integer and FP loads and stores. We only
know which it is after register bank selection. This results in
s16/s32 loads/stores on the GPR register bank that need to be
selected. This required extra isel patterns not needed for SDAG
and adding i16 and i32 to the GPR register class. Having i16/i32
on the GPR register class makes type interfence in tablegen less
effective, requiring explicit casts to be added to patterns. It also
increases the size of RISCVGenDAGISel.inc by 2K.

This patch removes the extra isel patterns and replaces it with custom
instruction selection similar to what is done on AArch64. A future
patch will remove i16 and i32 from the GPR register class.



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