[all-commits] [llvm/llvm-project] 30b9ef: [RISCV] Factor out the core part of LMULWriteResMX...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb
      https://github.com/llvm/llvm-project/commit/30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Factor out the core part of LMULWriteResMXVariant. NFC (#162347)

LMULWriteResMXVariant is a helper class that makes creating LMUL-aware
`SchedVar` easier. In preparation for later patches that require
  - LMUL- _and_ SEW-aware `SchedVar`
- Assign different processor resources for predicated and non-predicated
variants

I factor out the core logics of LMULWriteResMXVariant into another impl
class, such that it'll be easier to add _"LMULSEWWriteResMXSEWVariant"_
easier later. I also extend this class so that users can customize
processor resources for the non-predicated variant.

Despite these, this patch is still a NFC. I thought it'll be cleaner not
to mix the changes here into later patches.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications