[all-commits] [llvm/llvm-project] 5c613f: [ARM] Add mayRaiseFPException to appropriate instr...

[Erik Enikeev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c613f287df7fc94e159621f870f1bb1fe3baaee
      https://github.com/llvm/llvm-project/commit/5c613f287df7fc94e159621f870f1bb1fe3baaee
  Author: Erik Enikeev <47039011+Varnike at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/ARM/ARMRegisterInfo.td
    M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
    M llvm/test/CodeGen/ARM/bf16_fast_math.ll
    M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
    M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
    M llvm/test/CodeGen/ARM/fp16_fast_math.ll
    M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
    M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
    M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
    M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
    M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
    M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
    M llvm/test/CodeGen/Thumb2/swp-regpressure.mir

  Log Message:
  -----------
  [ARM] Add mayRaiseFPException to appropriate instructions and mark all instructions that read/write fpscr rounding bits as doing so (#160698)

Added new register FPSCR_RM to correctly model interactions with
rounding mode control bits of fpscr and to avoid performance regressions
in normal non-strictfp case

This PR is part of the work on adding strict FP support in ARM, which
was previously discussed in #137101.



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