[all-commits] [llvm/llvm-project] 4d2e1e: Reland "[lit] Refactor available `ptxas` features"...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Wed Sep 3 09:12:56 PDT 2025
Branch: refs/heads/users/boomanaiden154/main.lld-update-tests-redirecting-multiple-commands-to-filecheck
Home: https://github.com/llvm/llvm-project
Commit: 4d2e1e1c74c1e437b23fccd4ea545d2f7d43d1d2
https://github.com/llvm/llvm-project/commit/4d2e1e1c74c1e437b23fccd4ea545d2f7d43d1d2
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/applypriority.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/b52037.ll
M llvm/test/CodeGen/NVPTX/barrier.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bmsk.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/byval-arg-vectorize.ll
M llvm/test/CodeGen/NVPTX/byval-const-global.ll
M llvm/test/CodeGen/NVPTX/calling-conv.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/combine-min-max.ll
M llvm/test/CodeGen/NVPTX/common-linkage.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/convert-call-to-indirect.ll
M llvm/test/CodeGen/NVPTX/convert-fp.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm89.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/NVPTX/discard.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16-ex2.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
M llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fold-movs.ll
M llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/griddepcontrol.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/prefetch-inferas-test.ll
M llvm/test/CodeGen/NVPTX/prefetch.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/st_bulk.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/surf-tex.py
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/szext.ll
M llvm/test/CodeGen/NVPTX/tanhf.ll
M llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
M llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
M llvm/test/CodeGen/NVPTX/tcgen05-fence.ll
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M llvm/test/CodeGen/NVPTX/trunc-setcc.ll
M llvm/test/CodeGen/NVPTX/trunc-tofp.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/vaargs.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vector-compare.ll
M llvm/test/CodeGen/NVPTX/vector-select.ll
M llvm/test/CodeGen/NVPTX/vote.ll
M llvm/test/CodeGen/NVPTX/weak-global.ll
M llvm/test/CodeGen/NVPTX/wgmma-sm90a-fence.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx60-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx61-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm72.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx64-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx65-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx71-sm80.py
M llvm/test/CodeGen/NVPTX/wmma-ptx78-sm90.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm100a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm101a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py
M llvm/test/DebugInfo/NVPTX/dbg-value-const-byref.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Reland "[lit] Refactor available `ptxas` features" (#155923)
Reland #154439. Reverted with #155914.
Account for:
- Windows `ptxas` outputting error messages to `stdout` instead of
`stderr`
- Tests in `llvm/test/DebugInfo/NVPTX`
Commit: 2e96cd6562f64e11b4b3359f867bab8d45a79672
https://github.com/llvm/llvm-project/commit/2e96cd6562f64e11b4b3359f867bab8d45a79672
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp
A clang/test/Analysis/model-file-missing.cpp
Log Message:
-----------
[clang][analyzer] Delay checking the model-path (#150133)
This PR is part of an effort to remove file system usage from the
command line parsing code. The reason for that is that it's impossible
to do file system access correctly without a configured VFS, and the VFS
can only be configured after the command line is parsed. I don't want to
intertwine command line parsing and VFS configuration, so I decided to
perform the file system access after the command line is parsed and the
VFS is configured - ideally right before the file system entity is used
for the first time.
This patch delays checking that `model-path` is an existing directory.
Commit: 3ab1e0f888d46708c0c2308b072d84d8ceb43f93
https://github.com/llvm/llvm-project/commit/3ab1e0f888d46708c0c2308b072d84d8ceb43f93
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
R clang/test/AST/ast-dump-labeled-break-continue-json.c
Log Message:
-----------
[Clang] Remove broken AST dump test for now (#156498)
The name mangling on Mac OS is causing one of the AST dump tests added
by #152870 to fail, and it seems that there are some other issues with it; remove
it entirely so it stops breaking CI; I’ll add it back in a separate pr after I’ve managed
to fix it.
Commit: 2364736d6b55a4c92a53e33ee2be2679d36d26b5
https://github.com/llvm/llvm-project/commit/2364736d6b55a4c92a53e33ee2be2679d36d26b5
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang/lib/Semantics/check-call.cpp
M flang/test/Semantics/reduce01.f90
Log Message:
-----------
[flang] Fixed a crash in CheckReduce() (#156382)
Added extra checks to fix the crash.
Fixes #156167
Commit: 08001cf340185877665ee381513bf22a0fca3533
https://github.com/llvm/llvm-project/commit/08001cf340185877665ee381513bf22a0fca3533
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
Log Message:
-----------
[LAA,Loads] Use loop guards and max BTC if needed when checking deref. (#155672)
Remove the fall-back to constant max BTC if the backedge-taken-count
cannot be computed.
The constant max backedge-taken count is computed considering loop
guards, so to avoid regressions we need to apply loop guards as needed.
Also remove the special handling for Mul in willNotOverflow, as this
should not longer be needed after 914374624f
(https://github.com/llvm/llvm-project/pull/155300).
PR: https://github.com/llvm/llvm-project/pull/155672
Commit: 95d3ecee828528d4b019aae71c4f5581224ddbe2
https://github.com/llvm/llvm-project/commit/95d3ecee828528d4b019aae71c4f5581224ddbe2
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/volatile.cpp
Log Message:
-----------
[CIR] Add handling for volatile loads and stores (#156124)
This fills in the missing pieces to handle volatile loads and stores in
CIR.
This addresses https://github.com/llvm/llvm-project/issues/153280
Commit: 1fc090f7f1dba97bf0c53d3b158ef4934804d3d9
https://github.com/llvm/llvm-project/commit/1fc090f7f1dba97bf0c53d3b158ef4934804d3d9
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[clang][analyzer] Delay checking the ctu-dir (#150139)
This PR is part of an effort to remove file system usage from the
command line parsing code. The reason for that is that it's impossible
to do file system access correctly without a configured VFS, and the VFS
can only be configured after the command line is parsed. I don't want to
intertwine command line parsing and VFS configuration, so I decided to
perform the file system access after the command line is parsed and the
VFS is configured - ideally right before the file system entity is used
for the first time.
This patch delays checking that `ctu-dir` is an existing directory.
Commit: 7e1e13398f6907bf66fcf26dbf1f4ab67ece0182
https://github.com/llvm/llvm-project/commit/7e1e13398f6907bf66fcf26dbf1f4ab67ece0182
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang/test/Driver/atomic-control-options.f90
Log Message:
-----------
Exclude some run options on AIX. (#156376)
Those excluded run options failed on AIX.
Commit: ef72c2325ba995da84f9de62606e9a607f0d3c9a
https://github.com/llvm/llvm-project/commit/ef72c2325ba995da84f9de62606e9a607f0d3c9a
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Implement vector unpack instructions (#151004)
Implement the set of vector uncompress instructions:
* vupkhsntob
* vupklsntob
* vupkint4tobf16
* vupkint8tobf16
* vupkint4tofp32
* vupkint8tofp32
Commit: 0c0c55a6e794779917132e48322a7222c76d11b6
https://github.com/llvm/llvm-project/commit/0c0c55a6e794779917132e48322a7222c76d11b6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A bolt/test/runtime/copy_file.py
M bolt/test/runtime/instrumentation-indirect-2.c
Log Message:
-----------
[BOLT] Port additional test to internal shell (#156487)
This test was broken by #156083 because it was never ported to the
internal shell. It requires fuser which is not installed by default on
premerge and none of the BOLT buildbots have been online in a while.
This was actually causing a timeout because of #156484, worked around
using a manual bash invocation with a wait call to ensure all of the
subprocesses have exited.
Commit: cf3a8876f4129f76884a67f6db9214adb7adedc6
https://github.com/llvm/llvm-project/commit/cf3a8876f4129f76884a67f6db9214adb7adedc6
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
A mlir/lib/Dialect/SPIRV/IR/ArmGraphOps.cpp
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
M mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Dialect/SPIRV/IR/availability.mlir
A mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
Log Message:
-----------
[mlir][spirv] Add support for SPV_ARM_graph extension - part 1 (#151934)
This is the first patch to add support for the SPV_ARM_graph SPIR-V
extension to MLIR’s SPIR-V dialect. The extension introduces a new Graph
abstraction for expressing dataflow computations over full resources.
The part 1 implementation includes:
- A new `GraphType`, modeled similarly to `FunctionType`, for typed
graph signatures.
- New operations in the `spirv.arm` namespace:
- `spirv.arm.Graph`
- `spirv.arm.GraphEntryPoint`
- `spirv.arm.GraphConstant`
- `spirv.arm.GraphOutput`
- Verifier and VCE updates to properly gate usage under SPV_ARM_graph.
- Tests covering parsing and verification.
Graphs currently support only SPV_ARM_tensors, but are designed to
generalize to other resource types, such as images.
Spec: KhronosGroup/SPIRV-Registry#346
RFC:
https://discourse.llvm.org/t/rfc-add-support-for-spv-arm-graph-extension-in-mlir-spir-v-dialect/86947
---------
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: c62284c43d519317979e3028f7c37f42eed6ac8e
https://github.com/llvm/llvm-project/commit/c62284c43d519317979e3028f7c37f42eed6ac8e
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[clang] Followup for constexpr-unknown potential constant expressions. (#151053)
6a60f18997d62b0e2842a921fcb6beb3e52ed823 fixed the primary issue of
dereferences, but there are some expressions that depend on the identity
of the pointed-to object without actually accessing it. Handle those
cases.
Also, while I'm here, fix a crash in interpreter mode comparing typeid
to nullptr.
Commit: e2a8b9862c09acb5ae065718bbd73485da21172b
https://github.com/llvm/llvm-project/commit/e2a8b9862c09acb5ae065718bbd73485da21172b
Author: Thurston Dang <thurston at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/zero_alloc.cpp
Log Message:
-----------
[asan] Change zero_alloc.cpp testcase to use stdlib.h, re-enable on Mac (#156490)
Avoid build breakage on Mac (reported at
https://github.com/llvm/llvm-project/pull/155943#issuecomment-3244593484)
Commit: 51163c5dbdea72139ee4b93f5de7e652d30dea9f
https://github.com/llvm/llvm-project/commit/51163c5dbdea72139ee4b93f5de7e652d30dea9f
Author: Thurston Dang <thurston at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M compiler-rt/test/msan/zero_alloc.cpp
Log Message:
-----------
[msan] Change zero_alloc.cpp testcase to use stdlib.h (#156491)
Avoid build breakage on Mac
Commit: c1d1e0e32fcd8f457a1644a5859d23155ca666ac
https://github.com/llvm/llvm-project/commit/c1d1e0e32fcd8f457a1644a5859d23155ca666ac
Author: Mohamed Emad <hulxxv at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/include/math.yaml
M libc/src/math/CMakeLists.txt
A libc/src/math/atanpif16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/atanpif16.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/atanpif16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/atanpif16_test.cpp
M libc/utils/MPFRWrapper/MPCommon.cpp
M libc/utils/MPFRWrapper/MPCommon.h
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
Log Message:
-----------
[libc][math][c23] Implement C23 math function atanpif16 (#150400)
This PR implements `atanpif16(x)` which computes
$\frac{\arctan(x)}{\pi}$ for half-precision floating-point numbers using
polynomial approximation with domain reduction.
## Mathematical Implementation
The implementation uses a 15th-degree Taylor polynomial expansion of
$\frac{\arctan(x)}{\pi}$ that's computed using
[`python-sympy`](https://www.sympy.org/en/index.html) and it's accurate
in $|x| \in [0, 0.5)$:
$$
g(x) = \frac{\arctan(x)}{\pi} \approx
\begin{aligned}[t]
& 0.318309886183791x \\
& - 0.106103295394597x^3 \\
& + 0.0636619772367581x^5 \\
& - 0.0454728408833987x^7 \\
& + 0.0353677651315323x^9 \\
& - 0.0289372623803446x^{11} \\
& + 0.0244853758602916x^{13} \\
& - 0.0212206590789194x^{15} + O(x^{17})
\end{aligned}
$$
---
To ensure accuracy across all real inputs, the domain is divided into
three cases with appropriate transformations:
**Case 1: $|x| \leq 0.5$**
Direct polynomial evaluation:
$$\text{atanpi}(x) = \text{sign}(x) \cdot g(|x|)$$
**Case 2: $0.5 < |x| \leq 1$**
Double-angle reduction using:
$$\arctan(x) = 2\arctan\left(\frac{x}{1 + \sqrt{1 + x^2}}\right)$$
$$\text{atanpi}(x) = \text{sign}(x) \cdot 2g\left(\frac{|x|}{1 + \sqrt{1
+ x^2}}\right)$$
**Case 3: $|x| > 1$**
Reciprocal transformation using
$$\arctan(x) = \frac{\pi}{2} - \arctan\left(\frac{1}{x}\right) \
\text{for} \ x \gt 0$$
$$\text{atanpi}(x) = \text{sign}(x) \cdot \left(\frac{1}{2} -
g\left(\frac{1}{|x|}\right)\right)$$
Closes #132212
Commit: 1a4d0c6dfe9d717215890650a42a53d4ec9bfd8f
https://github.com/llvm/llvm-project/commit/1a4d0c6dfe9d717215890650a42a53d4ec9bfd8f
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/MC/AMDGPU/vop3-literal.s
Log Message:
-----------
[AMDGPU] Add VOP3 literal testing for GFX1250. NFC. (#156496)
Tweak some tests to avoid uninteresting errors about VGPR alignment and
some unsupported instructions.
Commit: a24e11fd951d3396ccbb469b2c5dc707dc4196a6
https://github.com/llvm/llvm-project/commit/a24e11fd951d3396ccbb469b2c5dc707dc4196a6
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[clang] Delay checking of `-fopenmp-host-ir-file-path` (#150124)
This PR is part of an effort to remove file system usage from the
command line parsing code. The reason for that is that it's impossible
to do file system access correctly without a configured VFS, and the VFS
can only be configured after the command line is parsed. I don't want to
intertwine command line parsing and VFS configuration, so I decided to
perform the file system access after the command line is parsed and the
VFS is configured - ideally right before the file system entity is used
for the first time.
This patch delays opening the OpenMP host IR file until codegen.
Commit: cea2c8625e801bdabca5e73d050300dc4060df00
https://github.com/llvm/llvm-project/commit/cea2c8625e801bdabca5e73d050300dc4060df00
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder][Debug] Remove unnecessary code. (#156468)
In the code that fix ups the debug information, we handles both the
debug intrinsics and debug records. The debug intrinsics are being
phased out and I recently changed mlir translation to not generate them.
This means that we should not get debug intrinsics anymore and code can
be simplified by removing their handling.
Commit: 005f0fa40ed3fe4657322f95916577c2f855719b
https://github.com/llvm/llvm-project/commit/005f0fa40ed3fe4657322f95916577c2f855719b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/AArch64/many-uses-fma-candidate.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
[SLP]Improved/fixed FMAD support in reductions
In the initial patch for FMAD, potential FMAD nodes were completely
excluded from the reduction analysis for the smaller patch. But it may
cause regressions.
This patch adds better detection of scalar FMAD reduction operations and
tries to correctly calculate the costs of the FMAD reduction operations
(also, excluding the costs of the scalar fmuls) and split reduction
operations, combined with regular FMADs.
Fixed the handling for reduced values with many uses.
Reviewers: RKSimon, gregbedwell, hiraditya
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/152787
Commit: 70a291f3225628d3479452829dc8b72d5d04e034
https://github.com/llvm/llvm-project/commit/70a291f3225628d3479452829dc8b72d5d04e034
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[MLIR][Python] fix operation hashing (#156514)
https://github.com/llvm/llvm-project/pull/155114 broke op hashing
(because the python objects ceased to be reference equivalent). This PR
fixes by binding `OperationEquivalence::computeHash`.
Commit: 4efde3c8fddc30b853430fc154cac85cfecc5224
https://github.com/llvm/llvm-project/commit/4efde3c8fddc30b853430fc154cac85cfecc5224
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size-needs-loop-guards.ll
Log Message:
-----------
[Loads] Apply loop guards to IRArgValue from assumption.
Applying loop guards to IRArgValue can improve results in some cases.
Commit: b0f85beeefbfdf3eb3f66fed6c5aed13ac423bb4
https://github.com/llvm/llvm-project/commit/b0f85beeefbfdf3eb3f66fed6c5aed13ac423bb4
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[flang] Fix build after #150124
Commit: 9f8988aaf4cc28ff534edd8c6bd7ec0300afd328
https://github.com/llvm/llvm-project/commit/9f8988aaf4cc28ff534edd8c6bd7ec0300afd328
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DependenceAnalysis] Improve debug messages (#156367)
This patch prints the reason why delinearization of array subscripts failed in dependence analysis.
Commit: 2429a8f71ff2080116b8a0e46541d1fb80351219
https://github.com/llvm/llvm-project/commit/2429a8f71ff2080116b8a0e46541d1fb80351219
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/include/math.yaml
Log Message:
-----------
[libc] Add missing and correct some existing C23 functions to math.h (#156512)
This change fixes and closes some gaps in the YAML template for
producing the math.h header.
It adds some missing declarations (dadd/dsub function variants), correct
arguments and/or return type for other functions from this family (dsqrt
and ddiv), and add a missing fminimum_numl variant.
Commit: f0df1e3dd4ec064821f673ced7d83e5a2cf6afa1
https://github.com/llvm/llvm-project/commit/f0df1e3dd4ec064821f673ced7d83e5a2cf6afa1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
Log Message:
-----------
Revert "[LAA,Loads] Use loop guards and max BTC if needed when checking deref. (#155672)"
This reverts commit 08001cf340185877665ee381513bf22a0fca3533.
This triggers an assertion in some build configs, e.g.
https://lab.llvm.org/buildbot/#/builders/24/builds/12211
Commit: 3c7bf3b3c3a4871d13f7b7d5d60bbf190eaf8f3a
https://github.com/llvm/llvm-project/commit/3c7bf3b3c3a4871d13f7b7d5d60bbf190eaf8f3a
Author: nerix <nerixdev at outlook.de>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
M lldb/test/Shell/SymbolFile/NativePDB/Inputs/incomplete-tag-type.cpp
R lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.cpp
A lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.test
Log Message:
-----------
[LLDB][NativePDB] Complete array member types in AST builder (#156370)
Commit: 665e875f1a86be650e044bb20744bb272d03e11d
https://github.com/llvm/llvm-project/commit/665e875f1a86be650e044bb20744bb272d03e11d
Author: David Blaikie <dblaikie at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCall.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/DebugInfo/CXX/structured-binding.cpp
Log Message:
-----------
[DebugInfo] When referencing structured bindings use the reference's location, not the binding's declaration's location (#153637)
For structured bindings that use custom `get` specializations, the
resulting LLVM IR ascribes the load of the result of `get` to the
binding's declaration, rather than the place where the binding is
referenced - this caused awkward sequencing in the debug info where,
when stepping through the code you'd step back to the binding
declaration every time there was a reference to the binding.
To fix that - when we cross into IRGening a binding - suppress the debug
info location of that subexpression.
I don't represent this as a great bit of API design - certainly open to
ideas, but putting it out here as a place to start.
It's /possible/ this is an incomplete fix, even - if the binding decl
had other subexpressions, those would still get their location applied &
it'd likely be wrong.
So maybe that's a direction to go with to productionize this - add a new
location scoped device that suppresses any overriding - this might be
more robust. How do people feel about that?
Commit: 3e0b91b77c0e4a056b4d8be61a8b82a077d36644
https://github.com/llvm/llvm-project/commit/3e0b91b77c0e4a056b4d8be61a8b82a077d36644
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/error_message.cpp
Log Message:
-----------
[OpenMP][clang] Fix CaptureRegion for message clause (#156525)
Fixes https://github.com/llvm/llvm-project/issues/156232
Commit: fbb0f2dba040bbdd5de5e59201c1a6fb9be3e06d
https://github.com/llvm/llvm-project/commit/fbb0f2dba040bbdd5de5e59201c1a6fb9be3e06d
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Implement vector uncompress instructions (#150702)
Implement the set of vector uncompress instructions:
* vucmprhh
* vucmprlh
* vucmprhn
* vucmprln
* vucmprhb
* vucmprlb
Commit: 3ce0ea38c2328c373227f5f1237b8ed88f7ecf06
https://github.com/llvm/llvm-project/commit/3ce0ea38c2328c373227f5f1237b8ed88f7ecf06
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
Log Message:
-----------
[AMDGPU] Definitions of new gfx1250 HW_REG_MODE fields. NFC. (#156527)
Commit: 49fcfaa15aeeed147280e6e39d802ac712ed3d74
https://github.com/llvm/llvm-project/commit/49fcfaa15aeeed147280e6e39d802ac712ed3d74
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
A llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
Log Message:
-----------
[GVN] Turn off ScalarPRE for TokenLike Types (#156513)
fixes #154407
In HLSL the GVNPass was adding a phi node on
a target extention type.
https://hlsl.godbolt.org/z/sc14YenEe
This is something we cleaned up in a past PR
(https://github.com/llvm/llvm-project/pull/154620) by introducing
`isTokenLikeTy`. In the case of the GVN pass the target extention type
was still making its way through. This change makes it so if we see this
type we don't do PRE.
Commit: 81131f37455e9960ed22fa48d95e69f8a0149347
https://github.com/llvm/llvm-project/commit/81131f37455e9960ed22fa48d95e69f8a0149347
Author: Haowei <haowei at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Debuginfod/Debuginfod.h
M llvm/include/llvm/Debuginfod/HTTPServer.h
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/Debuginfod/HTTPServer.cpp
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
Log Message:
-----------
Reverts recent debuginfod patches (#156532)
This patch reverts 44e791c6ff1a982de9651aad7d1c83d1ad96da8a,
3cc1031a827d319c6cb48df1c3aafc9ba7e96d72 and
adbd43250ade1d5357542d8bd7c3dfed212ddec0. Which breaks debuginfod build
and tests when httplib is used.
Commit: cc9acb9df7f7e598a6c93eaa1f2b1405a6b73bad
https://github.com/llvm/llvm-project/commit/cc9acb9df7f7e598a6c93eaa1f2b1405a6b73bad
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] Add s_set_vgpr_msb gfx1250 instruction (#156524)
Commit: 023a98c2ae8a260632f5fa71aaede95c4a981399
https://github.com/llvm/llvm-project/commit/023a98c2ae8a260632f5fa71aaede95c4a981399
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/bindings/interface/SBStructuredDataExtensions.i
M lldb/test/API/python_api/sbstructureddata/TestStructuredDataAPI.py
Log Message:
-----------
[lldb] Add Pythonic API to SBStructuredData extension (#155061)
* Adds `dynamic` property to automatically convert `SBStructuredData`
instances to the associated Python type (`str`, `int`, `float`, `bool`,
`NoneType`, etc)
* Implements `__getitem__` for Pythonic array and dictionary
subscripting
* Subscripting return the result of the `dynamic` property
* Updates `__iter__` to support dictionary instances (supporting `for`
loops)
* Adds conversion to `str`, `int`, and `float`
* Adds Pythonic `bool` conversion
With these changes, these two expressions are equal:
```py
data["name"] == data.GetValueForKey("name").GetStringValue(1024)
```
Additionally did some cleanup in TestStructuredDataAPI.py.
Commit: 2fc0e2c888521489f4a286b0902a6896506f8d8e
https://github.com/llvm/llvm-project/commit/2fc0e2c888521489f4a286b0902a6896506f8d8e
Author: Zequan Wu <zequanwu at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
Log Message:
-----------
[lldb][NativePDB] Sort function name and type basename maps deterministically. (#156530)
https://github.com/llvm/llvm-project/pull/153160 created those function
maps and uses default sort comparator which is not deterministic when
there are multiple entries with same name because llvm::sort is unstable
sort.
This fixes it by comparing the id value when tie happens and sort
`m_type_base_names` deterministically as well.
Commit: 5b4819e337c662fad7176a1d8e7b95a94f199290
https://github.com/llvm/llvm-project/commit/5b4819e337c662fad7176a1d8e7b95a94f199290
Author: David Blaikie <dblaikie at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/test/DebugInfo/CXX/structured-binding.cpp
Log Message:
-----------
Generalize test over 32 and 64bit targets
Commit: 2bc019d8d02afee096f1c0c19cb2828b526aef94
https://github.com/llvm/llvm-project/commit/2bc019d8d02afee096f1c0c19cb2828b526aef94
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Log Message:
-----------
[RISCV] Simplify interface of RISCVAsmPrinter::lowerToMCInst [nfc] (#156482)
The only case which returns true is just pypassing this routine for
custom logic. Given the caller *already* has to special case this to
even fall into this routine, let's just put the logic in one place.
Note that the code had a guard for a malformed attribute which is
unreachable, and was converted into an assert. The verifier enforces
that the function attribute is well formed if present.
Commit: e57cb26d171bebe78df0a3d008e7f4c14b319067
https://github.com/llvm/llvm-project/commit/e57cb26d171bebe78df0a3d008e7f4c14b319067
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang-rt/lib/runtime/CMakeLists.txt
Log Message:
-----------
[flang][rt] Remove findloc.cpp from supported_sources fro CUDA build (#156542)
findloc.cpp is causing memory exhaustion with higher compute
capabilities. Also it is a very expensive file to build. Remove it from
the supported_sources for CUDA build until we can lower its memory
footprint.
Commit: 7fa3e6d17941cfdd982f5e159a52dde671e24685
https://github.com/llvm/llvm-project/commit/7fa3e6d17941cfdd982f5e159a52dde671e24685
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Commands/Options.td
Log Message:
-----------
[lldb] Format source/Commands/Options.td (#156517)
Format the command options tablegen file, which was created before
clang-format added support for tablegen. Small changes lead to lots of
reformatting changes which makes the diffs hard to review.
Commit: 03f836eff85e115c4dc57b64eeb3d8643f9f53a3
https://github.com/llvm/llvm-project/commit/03f836eff85e115c4dc57b64eeb3d8643f9f53a3
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
Log Message:
-----------
[NVPTX] Fix `fence-nocluster.ll` `ptxas` invocation (NFC) (#156531)
Commit: 7a0dfb1fec20bcb8565b39507e282b12e436ba1f
https://github.com/llvm/llvm-project/commit/7a0dfb1fec20bcb8565b39507e282b12e436ba1f
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/SemaOpenACC/combined-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/compute-construct-reduction-clause.c
M clang/test/SemaOpenACC/compute-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
Log Message:
-----------
[OpenACC] Make 'reduction' on a complex ill-formed
The standard provides for scalar variables, though is silent as to
whether complex is a scalar variable. However, during review, we found
that it is completely nonsensical to do any of the reduction operations on
complex (or to initialize some), so this patch makes it ill-formed.
Commit: 22ba2ac3ea4e57d9e501c6c82e6f2f9e2a71f970
https://github.com/llvm/llvm-project/commit/22ba2ac3ea4e57d9e501c6c82e6f2f9e2a71f970
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for modernize-use-emplace in TosaReduceTransposes.cpp (NFC)
Commit: 2b70ad24e8c4db8fa681ea8a1086cda81e89fde2
https://github.com/llvm/llvm-project/commit/2b70ad24e8c4db8fa681ea8a1086cda81e89fde2
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in ReshapeOpsUtils.cpp (NFC)
Commit: e2901f161087840c36890e61055aded5df90399b
https://github.com/llvm/llvm-project/commit/e2901f161087840c36890e61055aded5df90399b
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
Log Message:
-----------
[AMDGPU] Adjust VGPR allocation encoding on gfx1250 (#156546)
Commit: 1cee0e7b6281e5f82154a101eed09a7197a295a6
https://github.com/llvm/llvm-project/commit/1cee0e7b6281e5f82154a101eed09a7197a295a6
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/include/lldb/Host/File.h
M lldb/source/Host/common/File.cpp
Log Message:
-----------
[lldb][windows] use Windows APIs to print to the console (#156469)
This is a relanding of https://github.com/llvm/llvm-project/pull/149493.
The tests were failing because we were interpreting a proper file
descriptor as a console file descriptor.
This patch uses the Windows APIs to print to the Windows Console,
through `llvm::raw_fd_ostream`.
This fixes a rendering issue where the characters defined in
`DiagnosticsRendering.cpp` ("╰" for instance) are not rendered properly
on Windows out of the box, because the default codepage is not `utf-8`.
This solution is based on [this patch
downstream](https://github.com/swiftlang/swift/pull/40632/files#diff-e948e4bd7a601e3ca82d596058ccb39326459a4751470eec4d393adeaf516977R37-R38).
rdar://156064500
Commit: a3c41ddcafb93dcb226bdef12b91a192b647e8c4
https://github.com/llvm/llvm-project/commit/a3c41ddcafb93dcb226bdef12b91a192b647e8c4
Author: Derek Schuff <dschuff at chromium.org>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/test/CodeGen/WebAssembly/global-set.ll
Log Message:
-----------
[WebAssembly] Guard use of getSymbolName with isSymbol (#156105)
WebAssemblyRegStackfy checks for writes to the stack pointer to avoid
stackifying across them, but it wasn't prepared for other global_set
instructions (such as writes in addrspace 1).
Fixes #156055
Thanks to @QuantumSegfault for reporting and identifying the offending
code.
Commit: e95355c3f7e18829b587bc2d589b24a65f596543
https://github.com/llvm/llvm-project/commit/e95355c3f7e18829b587bc2d589b24a65f596543
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
Log Message:
-----------
[libc] Add CMake Target for Dl_info.h Header (#156195)
Otherwise when installing the dlfcn.h header, there is a missing
reference to Dl_info.h, which causes compilation failures in some cases,
notably libunwind.
Commit: 0dc1b168a660969f6f99f3238b908c1e3be5ed2d
https://github.com/llvm/llvm-project/commit/0dc1b168a660969f6f99f3238b908c1e3be5ed2d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/dl_info.h
M libc/src/dlfcn/CMakeLists.txt
M libc/src/dlfcn/dladdr.cpp
M libc/src/dlfcn/dladdr.h
Log Message:
-----------
[libc] Install dladdr on X86 (#156500)
This patch adds dladdr to the X86 entrypoints and also does the
necessary plumbing so that dladdr.cpp will actually compile.
This depends on #156195.
Commit: d3d1d8ff213868262194676dfd90172ddc447907
https://github.com/llvm/llvm-project/commit/d3d1d8ff213868262194676dfd90172ddc447907
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-cluster-load.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] Support cluster load instructions for gfx1250 (#156548)
Commit: c7b26bdf0b495fb1e835f7fe4136d3583628dd60
https://github.com/llvm/llvm-project/commit/c7b26bdf0b495fb1e835f7fe4136d3583628dd60
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
Log Message:
-----------
[AMDGPU] Update builtins-amdgcn-error-gfx1250-param.cl (#156551)
Should check both load_async_to_lds and store_async_from_lds instead
just check store_async_from_lds twice.
Commit: 442b14d1720824064ac2d194d151c6421f6d4570
https://github.com/llvm/llvm-project/commit/442b14d1720824064ac2d194d151c6421f6d4570
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Fix adding m0 uses to gfx94/gfx12 ds atomics (#156402)
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid trying
to match the nonexistent m0-having form.
Commit: 1e786fbe5bbec669c745ea1bb67c1e15092a0073
https://github.com/llvm/llvm-project/commit/1e786fbe5bbec669c745ea1bb67c1e15092a0073
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Reorder arguments of DS_Real_gfx12 (NFC) (#156405)
This helps shrink the diff in a future change.
Commit: 3a7d14accef790e38fa38bdc2ef7fec4cfb90c2d
https://github.com/llvm/llvm-project/commit/3a7d14accef790e38fa38bdc2ef7fec4cfb90c2d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
Log Message:
-----------
AMDGPU: Avoid using exact class check in reg_sequence AGPR fold (#156135)
This does better in cases which mix align2 and non-align2 classes.
Commit: d7484684e5c81e567e6d31942b7047ba579daae1
https://github.com/llvm/llvm-project/commit/d7484684e5c81e567e6d31942b7047ba579daae1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Refactor isImmOperandLegal (#155607)
The goal is to expose more variants that can operate without
preconstructed MachineInstrs or MachineOperands.
Commit: d50f2ef437aeb1784f7556fd63639487f245ffaa
https://github.com/llvm/llvm-project/commit/d50f2ef437aeb1784f7556fd63639487f245ffaa
Author: Wenju He <wenju.he at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libclc/clc/include/clc/clc_convert.h
R libclc/clc/include/clc/clcmacro.h
M libclc/clc/lib/amdgcn/math/clc_ldexp_override.cl
M libclc/clc/lib/amdgpu/math/clc_native_exp2.cl
M libclc/clc/lib/amdgpu/math/clc_sqrt_fp64.cl
M libclc/clc/lib/clspv/math/clc_sw_fma.cl
M libclc/clc/lib/generic/common/clc_degrees.cl
M libclc/clc/lib/generic/common/clc_radians.cl
M libclc/clc/lib/generic/common/clc_smoothstep.cl
M libclc/clc/lib/generic/common/clc_step.cl
M libclc/clc/lib/generic/integer/clc_clz.cl
M libclc/clc/lib/generic/integer/clc_ctz.cl
M libclc/clc/lib/generic/integer/clc_mad_sat.cl
M libclc/clc/lib/generic/math/clc_cbrt.cl
M libclc/clc/lib/generic/math/clc_cos.cl
M libclc/clc/lib/generic/math/clc_exp10.cl
M libclc/clc/lib/generic/math/clc_fmod.cl
M libclc/clc/lib/generic/math/clc_fract.cl
M libclc/clc/lib/generic/math/clc_frexp.inc
M libclc/clc/lib/generic/math/clc_hypot.cl
M libclc/clc/lib/generic/math/clc_ilogb.cl
M libclc/clc/lib/generic/math/clc_ldexp.cl
M libclc/clc/lib/generic/math/clc_lgamma_r.cl
M libclc/clc/lib/generic/math/clc_log.cl
M libclc/clc/lib/generic/math/clc_log10.cl
M libclc/clc/lib/generic/math/clc_log2.cl
M libclc/clc/lib/generic/math/clc_logb.cl
M libclc/clc/lib/generic/math/clc_nextafter.cl
M libclc/clc/lib/generic/math/clc_pow.cl
M libclc/clc/lib/generic/math/clc_pown.cl
M libclc/clc/lib/generic/math/clc_powr.cl
M libclc/clc/lib/generic/math/clc_remainder.cl
M libclc/clc/lib/generic/math/clc_remquo.cl
M libclc/clc/lib/generic/math/clc_sin.cl
M libclc/clc/lib/generic/math/clc_sw_fma.cl
M libclc/clc/lib/generic/relational/clc_bitselect.cl
M libclc/clc/lib/r600/math/clc_native_rsqrt.cl
M libclc/clc/lib/r600/math/clc_rsqrt_override.cl
M libclc/clc/lib/spirv/math/clc_fmax.cl
M libclc/clc/lib/spirv/math/clc_fmin.cl
M libclc/opencl/lib/generic/common/sign.cl
M libclc/opencl/lib/generic/common/smoothstep.cl
M libclc/opencl/lib/generic/math/atan2.cl
M libclc/opencl/lib/generic/math/atan2pi.cl
M libclc/opencl/lib/generic/math/log.cl
M libclc/opencl/lib/generic/math/log10.cl
M libclc/opencl/lib/generic/math/log2.cl
M libclc/opencl/lib/generic/math/nan.cl
Log Message:
-----------
[NFC][libclc] Move _CLC_V_V_VP_VECTORIZE macro into clc_lgamma_r.cl and delete clcmacro.h (#156280)
clcmacro.h only defines _CLC_V_V_VP_VECTORIZE which is only used in
clc/lib/generic/math/clc_lgamma_r.cl.
Commit: dd5eb46690be62cc2c7b925de1b2dfde514337f0
https://github.com/llvm/llvm-project/commit/dd5eb46690be62cc2c7b925de1b2dfde514337f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
Log Message:
-----------
AMDGPU: Fold 64-bit immediate into copy to AV class (#155615)
This is in preparation for patches which will intoduce more
copies to av registers.
Commit: b159631bc63c9a591500a9dcde759b358229f179
https://github.com/llvm/llvm-project/commit/b159631bc63c9a591500a9dcde759b358229f179
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Replace constexpr with inline
One bot doesn't like this constexpr after d7484684
Commit: 9b5502292d8e4fa00ec1ab204df3999b7424dbb8
https://github.com/llvm/llvm-project/commit/9b5502292d8e4fa00ec1ab204df3999b7424dbb8
Author: Adam Nemet <anemet at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Log Message:
-----------
[CG] Add VTs for v[567]i1 and v[567]f16 (#156523)
[recommit https://github.com/llvm/llvm-project/pull/151763 after fixing
https://github.com/llvm/llvm-project/issues/152150]
We already had corresponding f32 and i32 vector types for these sizes.
Also add VTs v[567]i8 and v[567]i16: these are needed by the Hexagon
backend which for each i1 vector types want to query information about
the corresponding i8 and i16 types in
HexagonTargetLowering::getPreferredHvxVectorAction.
Commit: 681046e3a5d9892711846ff1eb01b112357fdacc
https://github.com/llvm/llvm-project/commit/681046e3a5d9892711846ff1eb01b112357fdacc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Fix true16 d16 entry table for DS pseudos (#156419)
This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.
Commit: 4ec890857da327adf547d3fece986e125ff2e2cb
https://github.com/llvm/llvm-project/commit/4ec890857da327adf547d3fece986e125ff2e2cb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
A llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
Log Message:
-----------
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
In future changes we will have more AV_ virtual registers, which
currently
block the formation of write2. Most of the time these registers can
simply
be constrained to VGPR, so do that.
Also relaxes the constraint in flat merging case. We already have the
necessary
code to insert copies to the original result registers, so there's no
point
in avoiding it.
Addresses the easy half of #155769
Commit: 410764cff5d657e66a64a8250958db99fb721385
https://github.com/llvm/llvm-project/commit/410764cff5d657e66a64a8250958db99fb721385
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
Log Message:
-----------
[RISCV] Commute True in foldVMergeToMask (#156499)
In order to fold a vmerge into a pseudo, the pseudo's passthru needs to
be the same as vmerge's false operand.
If they don't match we can try and commute the instruction if possible,
e.g. here we can commute v9 and v8 to fold the vmerge:
vsetvli zero, a0, e32, m1, ta, ma
vfmadd.vv v9, v10, v8
vsetvli zero, zero, e32, m1, tu, ma
vmerge.vvm v8, v8, v9, v0
vsetvli zero, a0, e32, m1, tu, mu
vfmacc.vv v8, v9, v10, v0.t
Previously this wasn't possible because we did the peephole in
SelectionDAG, but now that it's been migrated to MachineInstr in #144076
we can reuse the commuting infrastructure in TargetInstrInfo.
This fixes the extra vmv.v.v in the "mul" example here:
https://github.com/llvm/llvm-project/issues/123069#issuecomment-3137997141
It should also allow us to remove the isel patterns described in #141885
later.
Commit: c33ccfa52b2db90bae72ac11ee50639231e93310
https://github.com/llvm/llvm-project/commit/c33ccfa52b2db90bae72ac11ee50639231e93310
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
Log Message:
-----------
[VPlan] Reassociate (x & y) & z -> x & (y & z) (#155383)
This PR reassociates logical ands in order to enable more
simplifications.
The driving motivation for this is that with tail folding all blocks
inside the loop body will end up using the header mask. However this can
end up nestled deep within a chain of logical ands from other edges.
Typically the header mask will be a leaf nested in the LHS, e.g.
(headermask & y) & z. So pulling it out allows it to be simplified
further, e.g. allows it to be optimised away to VP intrinsics with EVL
tail folding.
Commit: cb89ffdd34aa6b7e6d1417ef68e1d837c8e651a1
https://github.com/llvm/llvm-project/commit/cb89ffdd34aa6b7e6d1417ef68e1d837c8e651a1
Author: Mitch <mitchbriles at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
Log Message:
-----------
[RISCV] Fix incorrect folding of select on ctlz/cttz (#155231)
This patch tries to fix
[#155014](https://github.com/llvm/llvm-project/issues/155014). The
pattern of `ctlz`/`cttz` -> `icmp` -> `select` can occur when accounting
for targets which don't support `cttz(0)` or `ctlz(0)`. We can replace
this with a mask, but **only on power-of-2 bitwidths**.
Commit: bfe150cdfc58feb0499f129b4be653340f98e1fe
https://github.com/llvm/llvm-project/commit/bfe150cdfc58feb0499f129b4be653340f98e1fe
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
Log Message:
-----------
[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence (#154952)
update zext pattern with reg_sequence. This is a follow up from
https://github.com/llvm/llvm-project/pull/154211#discussion_r2288538817
Commit: c5d766236d2b550c093fe9d963f8d036b0fcfb0b
https://github.com/llvm/llvm-project/commit/c5d766236d2b550c093fe9d963f8d036b0fcfb0b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
Log Message:
-----------
AMDGPU: Add tests for ds_write2 formation with agprs (#155765)
The current handling for write2 formation is overly conservative
and cannot form write2s with AGPR inputs.
Commit: 74275a11038c0c354a31b5da4657e5ddfad58d9a
https://github.com/llvm/llvm-project/commit/74275a11038c0c354a31b5da4657e5ddfad58d9a
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[RISCV] Simplify code gen for riscv_vector_builtin_cg.inc [NFC] (#156397)
For each intrinsic with ManualCodegen block will generate something like
below:
```cpp
SegInstSEW = 0;
...
if (SegInstSEW == (unsigned)-1) {
auto PointeeType = E->getArg(4294967295)->getType()->getPointeeType();
SegInstSEW = llvm::Log2_64(getContext().getTypeSize(PointeeType));
}
```
But actually SegInstSEW is table-gen-time constant, so can remove that
if-check and directly use the constant.
This change reduce riscv_vector_builtin_cg.inc around 6600 lines (30913
to 24305) which is around 20% reduction, however seems this isn't impact
the build time much since the redundant dead branch is almost will
optimized away by compiler in early stage.
Commit: 4aeb2900837ce750af821e1f0dba6d53ccd4870a
https://github.com/llvm/llvm-project/commit/4aeb2900837ce750af821e1f0dba6d53ccd4870a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/src/__support/CPP/simd.h
M libc/src/string/memory_utils/generic/inline_strlen.h
Log Message:
-----------
[libc] Add more elementwise wrapper functions (#156515)
Summary:
Fills out some of the missing fundamental floating point operations.
These just wrap the elementwise builtin of the same name.
Commit: 9c3961f4f60d7d6de189addfb81d43e05300600e
https://github.com/llvm/llvm-project/commit/9c3961f4f60d7d6de189addfb81d43e05300600e
Author: Chaitanya Koparkar <ckoparkar at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Headers/fmaintrin.h
Log Message:
-----------
[X86] Clear EVEX512 feature for 128-bit and 256-bit FMA intrinsics (#156472)
This matches the corresponding features defined in avx512vlintrin.h.
Commit: ba7d4792e1edabac593b8292420d355495081e08
https://github.com/llvm/llvm-project/commit/ba7d4792e1edabac593b8292420d355495081e08
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-cp.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-shift.mlir
Log Message:
-----------
[MLIR][NVVM] [NFC] Rename Tcgen05GroupKind to CTAGroupKind (#156448)
...as the cta_group::1/2 are used in non-tcgen05 Ops like TMA Loads
also.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 8f50921cef04a11b97be0fb333c1df6921df649f
https://github.com/llvm/llvm-project/commit/8f50921cef04a11b97be0fb333c1df6921df649f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
Log Message:
-----------
[RISCV] Add Zfh RUN lines to calling-conv-half.ll. NFC (#156562)
We had these RUN lines in our downstream and I couldn't tell for sure
that we had another Zfh calling convention test upstream.
Note we should fix the stack test to also exhaust the GPRs to make it
test the stack for ilp32f/lp64f. This was an existing issue in the
testing when F was enabled.
Commit: a9532191b82b02e6690e13fb72f513ab16119652
https://github.com/llvm/llvm-project/commit/a9532191b82b02e6690e13fb72f513ab16119652
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
Log Message:
-----------
[HLSL][NFC] Add assert to verify implicit binding resource attribute exists (#156094)
Adds assert as requested in
https://github.com/llvm/llvm-project/pull/152454#discussion_r2304509802.
Commit: 10dbb45e5c278dbbae4c0c3744482e0ebb557a9a
https://github.com/llvm/llvm-project/commit/10dbb45e5c278dbbae4c0c3744482e0ebb557a9a
Author: Jim Lin <jim at andestech.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
Log Message:
-----------
[RISCV] Remove unused `IntrinsicTypes` from help functions in RISCV.cpp. NFC.
Commit: 085471d777a2056903dca12b10139a9036b0125b
https://github.com/llvm/llvm-project/commit/085471d777a2056903dca12b10139a9036b0125b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
Log Message:
-----------
AMDGPU: Handle rewriting VGPR MFMA fed from AGPR copy (#153022)
Previously we handled the inverse situation only.
Commit: d373ec7f16872f838ce5ea9355b76b5924628393
https://github.com/llvm/llvm-project/commit/d373ec7f16872f838ce5ea9355b76b5924628393
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
Log Message:
-----------
AMDGPU: Add baseline test for unspilling VGPRs after MFMA rewrite (#154322)
Test for #154260
Commit: fdede21ddf05d72ce752bf03920d533e0800354b
https://github.com/llvm/llvm-project/commit/fdede21ddf05d72ce752bf03920d533e0800354b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
AMDGPU: Add statistic for number of MFMAs moved to AGPR form (#153024)
Commit: 3294cddb9878347cf273f427184190321e062028
https://github.com/llvm/llvm-project/commit/3294cddb9878347cf273f427184190321e062028
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
Log Message:
-----------
AMDGPU: Add test for mfma rewrite pass respecting optnone (#153025)
Commit: 7624c6141974f66f24ea90a18a55a111e98baa40
https://github.com/llvm/llvm-project/commit/7624c6141974f66f24ea90a18a55a111e98baa40
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/__tree
M libcxx/include/map
M libcxx/include/set
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/set/insert_iter_iter.pass.cpp
Log Message:
-----------
[libc++] Optimize {map,set}::insert(InputIterator, InputIterator) (#154703)
```
----------------------------------------------------------------------------------------------------------------------------
Benchmark old new
----------------------------------------------------------------------------------------------------------------------------
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/0 14.2 ns 14.8 ns
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/32 519 ns 404 ns
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/1024 52460 ns 36242 ns
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/8192 724222 ns 706496 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/0 14.2 ns 14.7 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/32 429 ns 349 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/1024 23601 ns 14734 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/8192 267753 ns 112155 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/0 434 ns 448 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/32 950 ns 963 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/1024 27205 ns 25344 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/8192 294248 ns 280713 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/0 435 ns 449 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/32 771 ns 706 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/1024 30841 ns 17495 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/8192 468807 ns 285847 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/0 449 ns 453 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/32 1021 ns 932 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/1024 29796 ns 19518 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/8192 345688 ns 153966 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/0 449 ns 450 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/32 1026 ns 807 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/1024 31632 ns 15573 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/8192 303024 ns 128946 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/0 447 ns 452 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/32 687 ns 710 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/1024 8604 ns 8581 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/8192 65693 ns 67406 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/0 15.0 ns 15.0 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/32 2781 ns 1845 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/1024 187999 ns 182103 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/8192 2937242 ns 2934912 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/0 15.0 ns 15.2 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/32 1326 ns 2462 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/1024 81778 ns 72193 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/8192 1177292 ns 669152 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/0 439 ns 454 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/32 2483 ns 2465 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/1024 187614 ns 188072 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/8192 1654675 ns 1706603 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/0 437 ns 452 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/32 1836 ns 1820 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/1024 114885 ns 121865 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/8192 1151960 ns 1197318 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/0 438 ns 455 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/32 1599 ns 1614 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/1024 95935 ns 82159 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/8192 776480 ns 941043 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/0 435 ns 462 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/32 1723 ns 1550 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/1024 107096 ns 92850 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/8192 893976 ns 775046 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/0 436 ns 453 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/32 775 ns 824 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/1024 20241 ns 20454 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/8192 139038 ns 138032 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/0 14.8 ns 14.7 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/32 468 ns 426 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/1024 54289 ns 39028 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/8192 738438 ns 695720 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/0 14.7 ns 14.6 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/32 478 ns 391 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/1024 24017 ns 13905 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/8192 267862 ns 111378 ns
std::set<int>::insert(iterator, iterator) (all new keys)/0 458 ns 450 ns
std::set<int>::insert(iterator, iterator) (all new keys)/32 1066 ns 956 ns
std::set<int>::insert(iterator, iterator) (all new keys)/1024 29190 ns 25212 ns
std::set<int>::insert(iterator, iterator) (all new keys)/8192 320441 ns 279602 ns
std::set<int>::insert(iterator, iterator) (half new keys)/0 454 ns 453 ns
std::set<int>::insert(iterator, iterator) (half new keys)/32 816 ns 709 ns
std::set<int>::insert(iterator, iterator) (half new keys)/1024 32072 ns 17074 ns
std::set<int>::insert(iterator, iterator) (half new keys)/8192 403386 ns 286202 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/0 451 ns 452 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/32 710 ns 703 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/1024 8261 ns 8499 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/8192 64466 ns 67343 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/0 15.2 ns 15.0 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/32 3069 ns 3005 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/1024 189552 ns 180933 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/8192 2887579 ns 2691678 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/0 15.1 ns 14.9 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/32 2611 ns 2514 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/1024 91581 ns 78727 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/8192 1192640 ns 1158959 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/0 452 ns 457 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/32 2530 ns 2544 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/1024 195352 ns 179614 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/8192 1737890 ns 1749615 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/0 451 ns 454 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/32 1949 ns 1766 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/1024 128853 ns 109467 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/8192 1233077 ns 1177289 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/0 450 ns 451 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/32 809 ns 812 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/1024 21736 ns 21922 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/8192 135884 ns 133228 ns
```
Fixes #154650
Commit: 4a2dd31f16d60b65a46696a909efad5c11b18c19
https://github.com/llvm/llvm-project/commit/4a2dd31f16d60b65a46696a909efad5c11b18c19
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__tree
M libcxx/include/map
Log Message:
-----------
[libc++] Refactor __tree::__find_equal to not have an out parameter (#147345)
Commit: a5b5248b7f2a9c0a25fc41ea87c01510558e3ecf
https://github.com/llvm/llvm-project/commit/a5b5248b7f2a9c0a25fc41ea87c01510558e3ecf
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__functional/function.h
M libcxx/include/__type_traits/invoke.h
Log Message:
-----------
[libc++] Simplify std::function implementation further (#145153)
We can use `if constexpr` and `__is_invocable_r` to simplify the
`function` implementation a bit.
Commit: 0a2eb850d0dbd9caa1b22ee94f3b2b9903f679cb
https://github.com/llvm/llvm-project/commit/0a2eb850d0dbd9caa1b22ee94f3b2b9903f679cb
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__config
M libcxx/include/mutex
A libcxx/test/extensions/clang/thread/thread.mutex/lock.verify.cpp
Log Message:
-----------
[libc++] Add thread safety annotations for std::lock (#154078)
Fixes #151733
Commit: 7ac3e52e29b17e22e973c15c2715602ffd19e8a9
https://github.com/llvm/llvm-project/commit/7ac3e52e29b17e22e973c15c2715602ffd19e8a9
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__cxx03/bitset
M libcxx/include/__cxx03/forward_list
M libcxx/include/__cxx03/list
M libcxx/test/std/containers/sequences/forwardlist/types.pass.cpp
M libcxx/test/std/containers/sequences/list/types.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/index_const.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/nonstdmem.uglified.compile.pass.cpp
Log Message:
-----------
[libc++][C++03] Backport #111127, #112843 and #121620 (#155571)
Commit: 90865906dd2d42311901ce8a567bb992a169860d
https://github.com/llvm/llvm-project/commit/90865906dd2d42311901ce8a567bb992a169860d
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
R clang/lib/StaticAnalyzer/Checkers/CastSizeChecker.cpp
R clang/test/Analysis/castsize.c
M clang/test/Analysis/malloc-annotations.c
M clang/test/Analysis/malloc-annotations.cpp
M clang/test/Analysis/malloc.c
M clang/test/Analysis/malloc.cpp
M clang/test/Analysis/misc-ps.m
M clang/test/Analysis/qt_malloc.cpp
Log Message:
-----------
[clang][analyzer] Remove checker 'alpha.core.CastSize' (#156350)
Commit: 655cdf2e45a108177f013a59f108d17a8a267783
https://github.com/llvm/llvm-project/commit/655cdf2e45a108177f013a59f108d17a8a267783
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
Log Message:
-----------
llvm-tli-checker: Remove TLINameList helper struct (#142535)
This avoids subclassing std::vector and a static constructor.
This started as a refactor to make TargetLibraryInfo available during
printing so a custom name could be reported. It turns out this struct
wasn't doing anything, other than providing a hacky way of printing the
standard name instead of the target's custom name. Just remove this and
stop hacking on the TargetLibraryInfo to falsely report the function
is available later.
Commit: d0363815dd4acde08168e930cb529ee10f86b838
https://github.com/llvm/llvm-project/commit/d0363815dd4acde08168e930cb529ee10f86b838
Author: quic_hchandel <hchandel at qti.qualcomm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/xqcibm-insbi.ll
Log Message:
-----------
[RISCV] Add changes to have better coverage for qc.insb and qc.insbi (#154135)
Before this patch, the selection for `QC_INSB` and `QC_INSBI` entirely
happens in C++, and does not support more than one non-constant input.
This patch seeks to rectify this shortcoming, by moving the C++ into a
target-specific DAGCombine, and adding `RISCV::QC_INSB`. One advantage
is this simplifies the code for handling `QC_INSBI`, as the C++ no
longer needs to choose between the two instructions based on the
inserted value (this is still done, but via ISel Patterns).
Another advantage of the DAGCombine is that this introduction can also
shift the inserted value to the `QC_INSB`, which our patterns need (and
were previously doing to the constant), and this shift can be
CSE'd/optimised with any prior shifts, if they exist. This allows the
inserted value to be variable, rather than a constant.
Commit: 22e7c36b7e3bc8755ae4b856eb0da1249beb0d6c
https://github.com/llvm/llvm-project/commit/22e7c36b7e3bc8755ae4b856eb0da1249beb0d6c
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Log Message:
-----------
[RISCV] Remove remaining vmerge_vl mask patterns. NFC (#156566)
Now that RISCVVectorPeephole can commute operands to fold vmerge into a
pseudo to make it masked in #156499, we can remove the remaining
VPatMultiplyAccVL_VV_VX/VPatFPMulAccVL_VV_VF_RM patterns.
It also looks like we can remove the vmerge_vl patterns for _TIED
psuedos too. I suspect they're handled by convertAllOnesVMergeToVMv and
foldVMV_V_V
Tested on SPEC CPU 2017 and llvm-test-suite to confirm there's no
codegen change.
Fixes #141885
Commit: f1dcdaac09b9271e00aeb095735ef984ae69752b
https://github.com/llvm/llvm-project/commit/f1dcdaac09b9271e00aeb095735ef984ae69752b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__tree
Log Message:
-----------
[libc++] Refactor remaining __find_equal calls (#156594)
#147345 refactored `__find_equal`. Unfortunately there was a merge
conflict with another patch. This fixes up the problematic places.
Commit: fba17cdee1830951867ecfc7d40f7b6caa78310a
https://github.com/llvm/llvm-project/commit/fba17cdee1830951867ecfc7d40f7b6caa78310a
Author: David Green <david.green at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
Log Message:
-----------
[AArch64] Guard fptosi+sitofp patterns with one use checks. (#156407)
Otherwise we can end up with more instructions, needing to emit both
`fcvtzu w0, s0` and `fcvtzu s0, s0`.
Commit: da8f692e3e6ecc7f91e4d0ff945613cabc103c28
https://github.com/llvm/llvm-project/commit/da8f692e3e6ecc7f91e4d0ff945613cabc103c28
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
Log Message:
-----------
AMDGPU: Handle V->A MFMA copy from case with immediate src2 (#153023)
Handle a special case for copies from AGPR VGPR on the MFMA inputs.
If the "input" is really a subregister def, we will not see the
usual copy to VGPR for src2, only the read of the subregister def.
Not sure if this pattern appears in practice.
Commit: 852f40f63bab4d85919cef1a28a3ee50239c303f
https://github.com/llvm/llvm-project/commit/852f40f63bab4d85919cef1a28a3ee50239c303f
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Follow up for #154865
Commit: 0909f04dcec436a7956a86300eaaaac6fbfd681c
https://github.com/llvm/llvm-project/commit/0909f04dcec436a7956a86300eaaaac6fbfd681c
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/unittests/Analysis/IR2VecTest.cpp
Log Message:
-----------
IR2VecTest.cpp: Suppress a warning. [-Wunused-const-variable]
Commit: 5256924acca8530c311abe64b525ba5dffa02074
https://github.com/llvm/llvm-project/commit/5256924acca8530c311abe64b525ba5dffa02074
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Clarify semantics of objectsize min parameter (#156309)
LangRef currently only says that this determines the return value if the
object size if unknown. What it actually does is determine whether the
minimum or maximum size is reported, which degenerates to 0 or -1 if
unknown.
Fixes https://github.com/llvm/llvm-project/issues/156192.
Commit: e915d9addeae5431f869d9a10021382871c11169
https://github.com/llvm/llvm-project/commit/e915d9addeae5431f869d9a10021382871c11169
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
[flang] Do not create omp_lib.f18.mod files (#156311)
The build system used to create `.f18.mod` variants for all `.mod`
files, but this was removed in #85249. However, there is a leftover that
still creates these when building `openmp` in the project configuration.
It does not happen in the runtimes configuration.
Commit: 0f3ede911a2c54ae6c4cac9801edc28d83e4c6a0
https://github.com/llvm/llvm-project/commit/0f3ede911a2c54ae6c4cac9801edc28d83e4c6a0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512fintrin.h
M clang/test/CodeGen/X86/avx512f-builtins.c
Log Message:
-----------
[X86] Allow AVX512 512-bit variants of AVX2 per-element i32 shift intrinsics to be used in constexpr (#156480)
Followup to #154780
Commit: 653c40365b9adf43ef766aeb7b6ef341598cceb5
https://github.com/llvm/llvm-project/commit/653c40365b9adf43ef766aeb7b6ef341598cceb5
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/X86/bswap-inline-asm.ll
Log Message:
-----------
[X86] Generate test checks (NFC)
Commit: d0d79fd1ac70602b3286bedbb75e42d3766c8019
https://github.com/llvm/llvm-project/commit/d0d79fd1ac70602b3286bedbb75e42d3766c8019
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
Log Message:
-----------
[AMDGPU] si-peephole-sdwa: reuse getOne{NonDBGUse,Def} (NFC) (#156455)
This patch changes the findSingleRegDef function from si-peephole-sdwa
to reuse MachineRegisterInfo::getOneDef and findSingleRefUse to use a
new MachineRegisterInfo::getOneNonDBGUse function.
Commit: 349523e26b80155b200e52e628006855371b6a93
https://github.com/llvm/llvm-project/commit/349523e26b80155b200e52e628006855371b6a93
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/IR/GEPNoWrapFlags.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/gep-canonicalize-constant-indices.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
Log Message:
-----------
[InstCombine] Merge constant offset geps across variable geps (#156326)
Fold:
%gep1 = ptradd %p, C1
%gep2 = ptradd %gep1, %x
%res = ptradd %gep2, C2
To:
%gep = ptradd %gep, %x
%res = ptradd %gep, C1+C2
An alternative to this would be to generally canonicalize constant
offset GEPs to the right. I found the results of doing that somewhat
mixed, so I'm going for this more obviously beneficial change for now.
Proof for flag preservation on reassociation:
https://alive2.llvm.org/ce/z/gmpAMg
Commit: 73bed64433072338d11ebf770d6db99c2ce810aa
https://github.com/llvm/llvm-project/commit/73bed64433072338d11ebf770d6db99c2ce810aa
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
A llvm/test/CodeGen/AArch64/scalable_masked_deinterleaved_loads.ll
Log Message:
-----------
[AArch64] Improve lowering for scalable masked deinterleaving loads (#154338)
For IR like this:
%mask = ... @llvm.vector.interleave2(<vscale x 16 x i1> %a, <vscale x 16
x i1> %a)
%vec = ... @llvm.masked.load(..., <vscale x 32 x i1> %mask, ...)
%dvec = ... @llvm.vector.deinterleave2(<vscale x 32 x i8> %vec)
where we're deinterleaving a wide masked load of the supported type
and with an interleaved mask we can lower this directly to a ld2b
instruction. Similarly we can also support other variants of ld2
and ld4.
This PR adds a DAG combine to spot such patterns and lower to ld2X
or ld4X variants accordingly, whilst being careful to ensure the
masked load is only used by the deinterleave intrinsic.
Commit: cd7f7cf5cca6fa425523a5af9fd42f82c6566ebf
https://github.com/llvm/llvm-project/commit/cd7f7cf5cca6fa425523a5af9fd42f82c6566ebf
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DebugOptions.h
M llvm/lib/Support/TypeSize.cpp
M llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Log Message:
-----------
Reapply [IR] Remove options to make scalable TypeSize access a warning (#156336)
Reapplying now that buildbot has picked up the new configuration
that does not use -treat-scalable-fixed-error-as-warning.
-----
This removes the `LLVM_ENABLE_STRICT_FIXED_SIZE_VECTORS` cmake option
and the `-treat-scalable-fixed-error-as-warning` opt flag.
We stopped treating these as warnings by default a long time ago
(62f09d788f9fc540db12f3cfa2f98760071fca96), so I don't think it makes
sense to retain these options at this point. Accessing a scalable
TypeSize as fixed should always result in an error.
Commit: 759a2ac5b0ee09be9dbb51ad50143d7db990a94a
https://github.com/llvm/llvm-project/commit/759a2ac5b0ee09be9dbb51ad50143d7db990a94a
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__ranges/as_rvalue_view.h
M libcxx/test/std/ranges/range.adaptors/range.as.rvalue/adaptor.pass.cpp
Log Message:
-----------
[libc++][ranges] LWG4083: `views::as_rvalue` should reject non-input ranges (#155156)
Fixes #105351
# References:
- https://wg21.link/LWG4083
- https://wg21.link/range.as.rvalue.overview
Commit: be1e50f56af8e270a0396eef8f62626fbbb84996
https://github.com/llvm/llvm-project/commit/be1e50f56af8e270a0396eef8f62626fbbb84996
Author: Miguel Saldivar <miguel.saldivar at hpe.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Lower/ConvertConstant.cpp
Log Message:
-----------
[flang] Avoid unnecessary looping for constants (#156403)
Going through and doing `convertToAttribute` for all elements, if they
are the same can be costly. If the elements are the same, we can just
call `convertToAttribute` once.
This does give us a significant speed-up:
```console
$ hyperfine --warmup 1 --runs 5 ./slow.sh ./fast.sh
Benchmark 1: ./slow.sh
Time (mean ± σ): 1.606 s ± 0.014 s [User: 1.393 s, System: 0.087 s]
Range (min … max): 1.591 s … 1.628 s 5 runs
Benchmark 2: ./fast.sh
Time (mean ± σ): 452.9 ms ± 7.6 ms [User: 249.9 ms, System: 83.3 ms]
Range (min … max): 443.9 ms … 461.7 ms 5 runs
Summary
./fast.sh ran
3.55 ± 0.07 times faster than ./slow.sh
```
Fixes #125444
Commit: b16930204b230240d834f667c8f32b12ca4ad198
https://github.com/llvm/llvm-project/commit/b16930204b230240d834f667c8f32b12ca4ad198
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
Log Message:
-----------
[LV] Add additional tests for reasoning about dereferenceable loads.
Includes a test for the crash exposed by 08001cf340185877.
Commit: 7da91fa801d8bd490c8dcd9a29faba209feb2954
https://github.com/llvm/llvm-project/commit/7da91fa801d8bd490c8dcd9a29faba209feb2954
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
Log Message:
-----------
[CodeGen] Fix failing assert in interleaved access pass (#156457)
In the InterleavedAccessPass the function getMask assumes that
shufflevector operations are always fixed width, which isn't true
because we use them for splats of scalable vectors. This patch fixes the
code by bailing out for scalable vectors.
Commit: 49ffe31defafd0cd87b2c194e57a02ad428fdae4
https://github.com/llvm/llvm-project/commit/49ffe31defafd0cd87b2c194e57a02ad428fdae4
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
Log Message:
-----------
[AMDGPU][LIT][NFC] Adding -mtriple for AMDGPUAnnotateUniformValues Pass tests (#156437)
It specifies the target machine as AMDGPU for
AMDGPUAnnotateUniformValues pass-related test (that uses UA). Before in
its absense, the UA would consider everything Uniform resulting in
setting metadata incorrectly for AMDGPU. Now, after specifying the
AMDGPU, the UA would be rightful sets the right metadata as the test
gets commpiled for AMDGPU.
Commit: 47de90e285aeec1acc8595c4b327cd823c069c90
https://github.com/llvm/llvm-project/commit/47de90e285aeec1acc8595c4b327cd823c069c90
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
A clang/test/Analysis/ctu-import-type-decl-definition.c
Log Message:
-----------
[clang] Fix crash 'Cannot get layout of forward declarations' during CTU static analysis (#156056)
When a type is imported with `ASTImporter`, the "original declaration"
of the type is imported. In some cases this is not the definition
(of the class). Before the fix the definition was only imported if
there was an other reference to it in the AST to import. This is not
always the case (like in the added test case), if not the definition
was missing in the "To" AST which can cause the assertion later.
Commit: 2f5500e4cf603ae080363f4f24df78d543972667
https://github.com/llvm/llvm-project/commit/2f5500e4cf603ae080363f4f24df78d543972667
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[LV] Improve the test coverage for strided access. nfc (#155981)
Add tests for strided access with UF > 1, and introduce a new test case
@constant_stride_reinterpret.
Commit: 3576f05db125006ffbe22bfc199a269bf2a4a06f
https://github.com/llvm/llvm-project/commit/3576f05db125006ffbe22bfc199a269bf2a4a06f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
Log Message:
-----------
llvm-tli-checker: Avoid a temporary string while printing (#156605)
Directly write to the output instead of building a string to
print.
Closes #142538
Commit: a1bfa2f6a69b9bff45529809af932f0484795b90
https://github.com/llvm/llvm-project/commit/a1bfa2f6a69b9bff45529809af932f0484795b90
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Log Message:
-----------
AMDGPU: Avoid directly using MCOperandInfo RegClass field (#156641)
This value should not be directly interpreted. Also avoids
a function only used for an assert.
Commit: d4de7809697842e99e4935974d54d3a1f829e59d
https://github.com/llvm/llvm-project/commit/d4de7809697842e99e4935974d54d3a1f829e59d
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
Log Message:
-----------
[AMDGPU] Use "v_bfi_b32 x, 0, z" to implement (z & ~x) (#156636)
Commit: 3bb6e60c1681300c44098a772f0a277dd12a9648
https://github.com/llvm/llvm-project/commit/3bb6e60c1681300c44098a772f0a277dd12a9648
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-extract.ll
A llvm/test/Analysis/CostModel/AArch64/sve-vls-shuffle-extract.ll
Log Message:
-----------
[AArch64] Update cost model for extracting halves from 128+ bit vectors (#155601)
Previously, only 128-bit "NEON" vectors were given sensible costs.
Cores with vscale>1 can use SVE's EXT instruction to perform a
fixed-length subvector extract.
This is a follow-up from the codegen patches at #152554. They show that
with the help of MOVPRFX, we can do subvector extracts with roughly one
instruction. We now at least give sensible costs for extracting 128-bit
halves from a 256-bit vector.
Commit: 8989ec5439dc2df2aeb7e5ea3e6c255ce8e9634d
https://github.com/llvm/llvm-project/commit/8989ec5439dc2df2aeb7e5ea3e6c255ce8e9634d
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
[AArch64] Combine SEXT_INREG(CSET) to CSETM. (#156429)
Add the following patterns to performSignExtendInRegCombine:
* SIGN_EXTEND_INREG (CSEL 0, 1, cc), i1 --> CSEL 0, -1, cc
* SIGN_EXTEND_INREG (CSEL 1, 0, cc), i1 --> CSEL -1, 0, cc
The combined forms can be matched to a CSETM.
Commit: a434a7a4f12faf3e0231fc145f7fb2e02c623a97
https://github.com/llvm/llvm-project/commit/a434a7a4f12faf3e0231fc145f7fb2e02c623a97
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
Log Message:
-----------
Reapply "[LAA,Loads] Use loop guards and max BTC if needed when checking deref. (#155672)"
This reverts commit f0df1e3dd4ec064821f673ced7d83e5a2cf6afa1.
Recommit with extra check for SCEVCouldNotCompute. Test has been added in
b16930204b.
Original message:
Remove the fall-back to constant max BTC if the backedge-taken-count
cannot be computed.
The constant max backedge-taken count is computed considering loop
guards, so to avoid regressions we need to apply loop guards as needed.
Also remove the special handling for Mul in willNotOverflow, as this
should not longer be needed after 914374624f
(https://github.com/llvm/llvm-project/pull/155300).
PR: https://github.com/llvm/llvm-project/pull/155672
Commit: 2ee567110c4cb9d562d03b690799c4f040b2a06c
https://github.com/llvm/llvm-project/commit/2ee567110c4cb9d562d03b690799c4f040b2a06c
Author: Mario Camillo <mario.camillo at imgtec.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] handle unranked tensors in tosa::table::verify (#156321)
Seen when running TOSA PRO-INT conformance tests in our SUT. This leads
to verify being called with unranked tensors causing exception/error
when trying to call getShape on them.
Made some variables const for consistency with other verify functions in
same file.
Commit: 27e541645c2a99cba6ae8705f2969f523410ef4c
https://github.com/llvm/llvm-project/commit/27e541645c2a99cba6ae8705f2969f523410ef4c
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M offload/test/offloading/mandatory_but_no_devices.c
M offload/test/offloading/memory_manager.cpp
Log Message:
-----------
[Offload][OpenMP] Enable more tests on AMDGPU (#156626)
(Re)enables a couple of tests that were disabled on AMDGPU for some
reason. Pass for me locally.
Commit: 38b376f1927df5c1dea1065041779b28b13b9dd9
https://github.com/llvm/llvm-project/commit/38b376f1927df5c1dea1065041779b28b13b9dd9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/IR/DataLayout.cpp
Log Message:
-----------
[DataLayout] Use linear scan to determine integer alignment (NFC)
The number of alignment entries is usually very small (5-7), so
it is more efficient to use a linear scan than a binary search.
Commit: 298764a250150752b556b3212af955e1e2a01877
https://github.com/llvm/llvm-project/commit/298764a250150752b556b3212af955e1e2a01877
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
A mlir/test/Conversion/FuncToLLVM/func-to-llvm-datalayout.mlir
Log Message:
-----------
[mlir][ToLLVM] Fix the index bitwidth handling for the dynamic case of `convert-to-llvm` (#156557)
This patch changes the behavior of `convert-to-llvm{dynamic=true}` so
that the nearest `DataLayout` is used to configure LowerToLLVMOptions
and LLVMTypeConverter.
Example:
```mlir
module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 16>>} {
func.func private @test_16bit_index(%arg0: index) -> index
}
// mlir-opt --convert-to-llvm="dynamic=true"
module attributes {dlti.dl_spec = #dlti.dl_spec<index = 16 : i64>} {
llvm.func @test_16bit_index(i16) -> i16 attributes {sym_visibility = "private"}
}
```
Commit: dc05c5dd12a952df82a7c843b1b3d05ea1ef21c0
https://github.com/llvm/llvm-project/commit/dc05c5dd12a952df82a7c843b1b3d05ea1ef21c0
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/lldb/LLDB.py
Log Message:
-----------
[Dexter] Use continue when resuming lldb execution to reach breakpoint (#156481)
Currently, Dexter's interface for lldb and lldb-dap has a post-step hook
that checks to see whether lldb reports that we stopped because we
completed a step, and if so checks to see whether the current $pc
address also matches a known breakpoint whose conditions (if any) are
met, and if so it requests to "step in", so that we "resume" execution,
stopping again at the current address, such that lldb now reports that
we have hit a breakpoint and provides the list of breakpoints that were
hit.
This logic has a flaw however: the call to "step in" sets an implicit
breakpoint on the next line. In Dexter's default stepping mode this is
not an issue, as we intend to step there eventually. When we use
DexContinue, however, we set a breakpoint from which we wish to continue
to the next user-specified breakpoint, rather than stepping. Currently,
there is a bug where Dexter sets a DexContinue breakpoint, arrives at
that bp from a step, requests "step in" so that LLDB gives us the hit
breakpoint ID, requests "continue" to hit the next user breakpoint, and
then arrives at the next line after the continue due to the earlier
"step in" request. This effectively negates the DexContinue command.
This patch fixes this behaviour by using "continue" instead of "step in"
in the post-step hook, ensuring that no implicit breakpoint is set so
that we do not incorrectly stop at the next line.
Commit: d29dc18992c85c5ef20f5958f55ed1713c1e215c
https://github.com/llvm/llvm-project/commit/d29dc18992c85c5ef20f5958f55ed1713c1e215c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Log Message:
-----------
AMDGPU: Remove dead code for printing DFP immediates (#156644)
Nothing in the backend uses these, so there's no reason
to support printing them.
Commit: 3f4d116978044e2acc5e9a36196cf2a7d790319e
https://github.com/llvm/llvm-project/commit/3f4d116978044e2acc5e9a36196cf2a7d790319e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M bolt/runtime/instr.cpp
Log Message:
-----------
[BOLT] close map_files FD (#156489)
The BOLT runtime currently does not close the FD pointing to
/proc/self/map_files. This does not actually hurt anything but was at
least a bit of a red herring for me when looking through strace on a
BOLT instrumented binary.
Commit: 71641049a91253f7547f792ec2fcb6609794ea4f
https://github.com/llvm/llvm-project/commit/71641049a91253f7547f792ec2fcb6609794ea4f
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libc/src/__support/threads/thread.cpp
M libc/src/__support/threads/thread.h
M libc/src/stdlib/exit.cpp
M libc/test/integration/src/__support/threads/CMakeLists.txt
A libc/test/integration/src/__support/threads/double_exit_test.cpp
A libc/test/integration/src/__support/threads/main_exit_test.cpp
Log Message:
-----------
[libc] ensure tls dtors are called in main thread (#133641)
This is a part of allocator patch since I want to make sure the TLS for
allocators are correctly handled.
TLS dtors are not invoked on exit previously. This departures from major
libc implementations.
This PR fixes the issue by aligning the behavior with bionic.
https://android.googlesource.com/platform/bionic/+/refs/heads/main/libc/bionic/exit.cpp
I believe the finalization order is also consistent with glibc now:
On main thread exiting:
- pthread_key dtors are not called (unless exiting with `pthread_exit`)
- `__cxa` based tls dtors are called
- `::__cxa_atexit` and `::atexit` dtors are called
- `.fini` dtors are called
Commit: ee71af4fc7e62981da3d73a917ef1919e6d4c2d8
https://github.com/llvm/llvm-project/commit/ee71af4fc7e62981da3d73a917ef1919e6d4c2d8
Author: Lakshay Kumar <lakshayk at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
A llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
M llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
Log Message:
-----------
[llvm-exegesis] [AArch64] Reland Resolving "not all operands are initialized by snippet generator" (#156423)
### Reland #142529 (Resolving "not all operands are initialized by
snippet generator")
Introduced changes in implementation of `randomizeTargetMCOperand()` for
AArch64 that omitting `OPERAND_SHIFT_MSL`, `OPERAND_PCREL` to an
immediate value of 264 and 8 respectively.
PS: Omitting
`MCOI::OPERAND_FIRST_TARGET/llvm:AArch64:OPERAND_IMPLICIT_IMM_0`
similarly, to value 0. It was low hanging change thus added in this PR
only.
For any future operand type of AArch64 if not initialised will exit with
error "`Unimplemented operand type: MCOI::OperandType:<#Number>`".
#### [Reland Updates]
Updated `tools/llvm-exegesis/AArch64/error-resolution.s` which caused
problem.
Test case was failing when there is uninitialised operands error coming
from secondary/consumer instruction used by exegesis in latency mode
required to chain up the assembly to ensure serial execution.
i.e. We get error message like `UMOVvi16_idx0: Not all operands were
initialized by the snippet generator for <<<any opcode other than
UMOVvi16_idx0>>> opcode.` but test case want to check like
`# UMOVvi16_idx0_latency: ---`. Thus the testcase fails.
```+ /llvm-project/build/bin/FileCheck /llvm-project/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s --check-prefix=UMOVvi16_idx0_latency
/llvm-project/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s:65:26: error: UMOVvi16_idx0_latency: expected string not found in input
# UMOVvi16_idx0_latency: ---
^
<stdin>:1:1: note: scanning from here
UMOVvi16_idx0: Not all operands were initialized by the snippet generator for LD1W_D_IMM opcode.
^
Input file: <stdin>
Check file: /llvm-project/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
-dump-input=help explains the following input dump.
Input was:
<<<<<<
1: UMOVvi16_idx0: Not all operands were initialized by the snippet generator for LD1W_D_IMM opcode.
check:65 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
>>>>>>
--
********************
********************
Failed Tests (1):
LLVM :: tools/llvm-exegesis/AArch64/error-resolution.s
```
#### [Why it fails (only sometimes)]
Exegesis in latency mode require the generated assembly to be chained to
ensure serial execution,
For this exegesis add an additional consumer instruction for some
instruction, which is chosen via a random seed.
Thus, it randomly fails whenever there is secondary consumer instruction
(which is unsupported/throws error) added in generated assembly.
Commit: 9f9b480dea3bd26b133e30d56e37f8ab0007f26d
https://github.com/llvm/llvm-project/commit/9f9b480dea3bd26b133e30d56e37f8ab0007f26d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[AArch64] Add computeKnownBits unit test coverage for AArch64ISD::VASHR/VLSHR/VSHL (#156631)
Base tests so we can add additional FREEZE tests on top in #156445
Commit: 5e924fa7640041f7081deed9787dc10d8007e7f9
https://github.com/llvm/llvm-project/commit/5e924fa7640041f7081deed9787dc10d8007e7f9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
A clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-unsigned-int.c
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
Log Message:
-----------
[OpenACC] Reduction 'init' lowering for all-ones/least/largest (#156535)
As a follow on to the last patches of this form, this patch does the
init section for all of the reduction operators that weren't previously
covered, which is '&' as all-ones, 'max' as 'least', and 'min' as
'largest'.
Commit: 913d44da833674be59b1713dfdb1cde8fea2a842
https://github.com/llvm/llvm-project/commit/913d44da833674be59b1713dfdb1cde8fea2a842
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/IR/EnumAttr.td
M mlir/test/IR/array-of-attr.mlir
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/test/mlir-tblgen/attr-or-type-format.td
Log Message:
-----------
[mlir][IR] Fix enum attribute handling by using parseKeywordOrString instead of parseKeyword (#156662)
Change enum attribute parsing to handle special characters and
multi-word
identifiers. This allows enum attrs to use symbols like "+" and strings
with separators like "dash-separated-sentence" instead of being limited
to
valid identifiers.
This also aligns enum attribute parsing with how enums are already
handled
by the `FieldParser`:
https://github.com/llvm/llvm-project/blob/main/mlir/tools/mlir-tblgen/EnumsGen.cpp#L108
Signed-off-by: Fabian Mora <fabian.mora-cordero at amd.com>
Commit: 44b779526036a62aa2f7c5285a51f5c043805c33
https://github.com/llvm/llvm-project/commit/44b779526036a62aa2f7c5285a51f5c043805c33
Author: Shamshura Egor <164661612+egorshamshura at users.noreply.github.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags-std.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags.cpp
Log Message:
-----------
[Clang] Add detailed notes explaining why is_aggregate evaluates to false (#152488)
This PR is part of
[#141911](https://github.com/llvm/llvm-project/issues/141911)
---------
Co-authored-by: Erich Keane <ekeane at nvidia.com>
Commit: 48d445a9713577576f03c6ddb11a4fa782838a4f
https://github.com/llvm/llvm-project/commit/48d445a9713577576f03c6ddb11a4fa782838a4f
Author: Lucas <github.snugness349 at passinbox.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/www/features.html
Log Message:
-----------
[clang][www] Documentation revision and proof read for features.html (#156620)
This is mostly just a small proof read for the
https://clang.llvm.org/features.html documentation page.
The changes include some typo fixes and suggestions I've found would be
useful.
---------
Co-authored-by: Lucas Mellone <lucasmellone at MAC-MINI.station>
Co-authored-by: lknknm <sxswt at protonmail.com>
Commit: fdace1ca454316d35d7fcbf4e0a0aa747aac57f2
https://github.com/llvm/llvm-project/commit/fdace1ca454316d35d7fcbf4e0a0aa747aac57f2
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Extract SCEVExpander from `calculateRtStride`, NFC
Make `calculateRtStride` return the SCEV of rt stride value and let the
caller expand it where needed.
Commit: b5f6ce6a1f5a8f42f9506f3a1b17b80b30e3e717
https://github.com/llvm/llvm-project/commit/b5f6ce6a1f5a8f42f9506f3a1b17b80b30e3e717
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
Log Message:
-----------
[mlir][vector] Propagate alignment from vector to llvm dialects. (#153482)
Allows alignment to be propagated correctly from vector to LLVM dialect
operations.
Commit: 6bbf0c30ca4449e325beb2d28db00d258d3a1a10
https://github.com/llvm/llvm-project/commit/6bbf0c30ca4449e325beb2d28db00d258d3a1a10
Author: Fei Peng <airpfei at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Log Message:
-----------
[sanitizer] Fix prctl interceptor causing PAC authentication failure (#153081)
The root cause of this crash is that prctl(PR_PAC_RESET_KEYS) generates
a new PAC key. As a result, paciasp and autiasp use different keys,
leading to the crash.
The solution is: if prctl's option is PR_PAC_RESET_KEYS, call real_prctl
directly. This is implemented in assembly, so there are no PAC
instructions involved.
Related issue: https://github.com/android/ndk/issues/1848
```
0000000000095468 <__interceptor_prctl>:
95468: d503233f paciasp
9546c: d10183ff sub sp, sp, #0x60
95470: a90267fe stp x30, x25, [sp, #0x20]
95474: a9035ff8 stp x24, x23, [sp, #0x30]
95478: a90457f6 stp x22, x21, [sp, #0x40]
9547c: a9054ff4 stp x20, x19, [sp, #0x50]
95480: aa1e03f4 mov x20, x30
95484: aa0403f3 mov x19, x4
95488: aa0303f6 mov x22, x3
9548c: aa0203f7 mov x23, x2
95490: aa0103f5 mov x21, x1
95494: 2a0003f8 mov w24, w0
95498: 940172ec bl 0xf2048 <_ZN6__tsan10cur_threadEv>
9549c: 4f05e540 movi v0.16b, #0xaa
954a0: 52801548 mov w8, #0xaa // =170
954a4: aa1403fe mov x30, x20
954a8: 39007fe8 strb w8, [sp, #0x1f]
954ac: aa0003f4 mov x20, x0
954b0: 910043e0 add x0, sp, #0x10
954b4: aa1403e1 mov x1, x20
954b8: bc01b3e0 stur s0, [sp, #0x1b]
954bc: d50320ff xpaclri
954c0: aa1e03e3 mov x3, x30
954c4: 97ffb461 bl 0x82648 <_ZN6__tsan17ScopedInterceptorC2EPNS_11ThreadStateEPKcm>
954c8: 97ff75ea bl 0x72c70 <_ZN11__sanitizer10StackTrace12GetCurrentPcEv>
954cc: 394c2688 ldrb w8, [x20, #0x309]
954d0: 7100051f cmp w8, #0x1
954d4: 540000c1 b.ne 0x954ec <__interceptor_prctl+0x84>
954d8: b9400a88 ldr w8, [x20, #0x8]
954dc: 35000088 cbnz w8, 0x954ec <__interceptor_prctl+0x84>
954e0: 394c2288 ldrb w8, [x20, #0x308]
954e4: 7100051f cmp w8, #0x1
954e8: 54000501 b.ne 0x95588 <__interceptor_prctl+0x120>
954ec: f0001128 adrp x8, 0x2bc000 <_ZN6__tsanL23interceptor_placeholderE+0xcac0>
954f0: 2a1803e0 mov w0, w24
954f4: aa1503e1 mov x1, x21
954f8: f9452508 ldr x8, [x8, #0xa48]
954fc: aa1703e2 mov x2, x23
95500: aa1603e3 mov x3, x22
95504: aa1303e4 mov x4, x19
95508: d63f0100 blr x8
9550c: f9400bf3 ldr x19, [sp, #0x10]
95510: 394c2668 ldrb w8, [x19, #0x309]
95514: 7100051f cmp w8, #0x1
95518: 540002a1 b.ne 0x9556c <__interceptor_prctl+0x104>
9551c: 39406be8 ldrb w8, [sp, #0x1a]
95520: 7100051f cmp w8, #0x1
95524: 54000d60 b.eq 0x956d0 <__interceptor_prctl+0x268>
95528: 394067e8 ldrb w8, [sp, #0x19]
9552c: 7100051f cmp w8, #0x1
95530: 54000de0 b.eq 0x956ec <__interceptor_prctl+0x284>
95534: b9400a68 ldr w8, [x19, #0x8]
95538: 350001a8 cbnz w8, 0x9556c <__interceptor_prctl+0x104>
9553c: b9403268 ldr w8, [x19, #0x30]
95540: 35000e48 cbnz w8, 0x95708 <__interceptor_prctl+0x2a0>
95544: f9400e68 ldr x8, [x19, #0x18]
95548: 91002109 add x9, x8, #0x8
9554c: f27c1d3f tst x9, #0xff0
95550: 54000ec0 b.eq 0x95728 <__interceptor_prctl+0x2c0>
95554: 5280004a mov w10, #0x2 // =2
95558: f900010a str x10, [x8]
9555c: f9000e69 str x9, [x19, #0x18]
95560: f9400a68 ldr x8, [x19, #0x10]
95564: d1002108 sub x8, x8, #0x8
95568: f9000a68 str x8, [x19, #0x10]
9556c: a9454ff4 ldp x20, x19, [sp, #0x50]
95570: a94457f6 ldp x22, x21, [sp, #0x40]
95574: a9435ff8 ldp x24, x23, [sp, #0x30]
95578: a94267fe ldp x30, x25, [sp, #0x20]
9557c: 910183ff add sp, sp, #0x60
95580: d50323bf autiasp
95584: d65f03c0 ret
...
```
Commit: 20b4f59ccad51e26e7cbd8b317c9f331d1ada6e5
https://github.com/llvm/llvm-project/commit/20b4f59ccad51e26e7cbd8b317c9f331d1ada6e5
Author: Shreeyash Pandey <shreeyash335 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/unittests/Target/RISCV/CMakeLists.txt
A llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp
Log Message:
-----------
[RISCV] add computeKnownBitsForTargetNode for RISCVISD::SRLW (#155995)
I've added support for computeKnownBitsForTargetNode for the SRLW
instruction. A test has been included which uses the snippet of IR as
suggested by topperc.
Fixed #154913
---------
Signed-off-by: Shreeyash Pandey <shreeyash335 at gmail.com>
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: 86879d46f6476386dc07772ede83cd43b6ddd739
https://github.com/llvm/llvm-project/commit/86879d46f6476386dc07772ede83cd43b6ddd739
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pr156256.ll
Log Message:
-----------
[X86] Only fold AND/ANDNP back to VSELECT if we know the predicated mask select is legal (#156663)
By only checking type legality we didn't account for 128/256-bit ops
being run on non-AVX512VL targets, or vXi8/i16 ops being run on
non-AVX512BW targets
This check is cropping up in several places now and I intend to hoist it
out into a common helper, but this initial fix needs to be as clean as
possible to be back ported to 21.X
Fixes #156256
Commit: d15998fe64619e1cc0d6285fbd24d5fe5429c9ef
https://github.com/llvm/llvm-project/commit/d15998fe64619e1cc0d6285fbd24d5fe5429c9ef
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/ptr.mlir
Log Message:
-----------
[mlir][ptr] Add translations to LLVMIR for ptr ops. (#156355)
Implements translation from ptr dialect to LLVM IR for core pointer
operations:
- `ptr.ptr_add` -> `getelementptr`
- `ptr.load` -> `load` with atomic ordering, volatility, and metadata
support
- `ptr.store` -> `store` with atomic ordering, volatility, and metadata
support
- `ptr.type_offset` -> GEP-based size computation
Example:
```mlir
llvm.func @test(%arg0: !ptr.ptr<#llvm.address_space<0>>) {
%0 = ptr.type_offset f64 : i32
%1 = ptr.ptr_add inbounds %arg0, %0 : !ptr.ptr<#llvm.address_space<0>>, i32
%2 = ptr.load volatile %1 : !ptr.ptr<#llvm.address_space<0>> -> f64
ptr.store %2, %arg0 : f64, !ptr.ptr<#llvm.address_space<0>>
llvm.return
}
```
Translates to:
```llvm
define void @test(ptr %0) {
%2 = getelementptr inbounds i8, ptr %0, i32 8
%3 = load volatile double, ptr %2, align 8
store double %3, ptr %0, align 8
ret void
}
```
Commit: 47793f9a73314a7669f436ee6e0528203c8633e7
https://github.com/llvm/llvm-project/commit/47793f9a73314a7669f436ee6e0528203c8633e7
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ExpandFp.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/lib/CodeGen/ExpandFp.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem-inf.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/lit.local.cfg
Log Message:
-----------
[AMDGPU] Implement IR expansion for frem instruction (#130988)
This patch implements a correctly rounded expansion of the frem
instruction in LLVM IR. This is useful for target architectures for
which such an expansion is too involved to be implement in ISel
Lowering. The expansion is based on the code from the AMD device libs
and has been tested successfully against the OpenCL conformance tests on
amdgpu. The expansion is implemented in the preexisting "expand-fp"
pass. It replaces the expansion of "frem" in ISel for the amdgpu target;
it is enabled for targets which do not directly support "frem" and for
which no matching "fmod" LibCall is available.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 0f032f1925389394802a86318ebc51b5e83f3b97
https://github.com/llvm/llvm-project/commit/0f032f1925389394802a86318ebc51b5e83f3b97
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety] Fix duplicate loan generation for ImplicitCastExpr (#153661)
This PR fixes a bug in the lifetime safety analysis where `ImplicitCastExpr` nodes were causing duplicate loan generation. The changes:
1. Remove the recursive `Visit(ICE->getSubExpr())` call in `VisitImplicitCastExpr` to prevent duplicate processing of the same expression
2. Ensure the CFG build options are properly configured for lifetime safety analysis by moving the flag check earlier
3. Enhance the unit test infrastructure to properly handle multiple loans per variable
4. Add a test case that verifies implicit casts to const don't create duplicate loans
5. Add a test case for ternary operators with a FIXME note about origin propagation
These changes prevent the analysis from generating duplicate loans when expressions are wrapped in implicit casts, which improves the accuracy of the lifetime safety analysis.
Commit: e6c63d920dec3e8874ac1dc3c3f19fb822f0ab06
https://github.com/llvm/llvm-project/commit/e6c63d920dec3e8874ac1dc3c3f19fb822f0ab06
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A clang/test/OpenMP/spirv_locstr.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Use target global AS for SrcLocStr (#156520)
We should set the correct target-specific AS for the SrcLocStr global
created in OMPIRBuilder.
We also may have to insert a constexpr addrspacecast because the struct
field type may be different than the value used to initialize it.
I actually want the cast to be from AS 1 to AS 4, but getting the type
to be AS4 relies on a PR currently in-review, so leave the cast target
to AS 0 for now.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 34e9f3d6e3757d4e6a13a3f3df32a134933b6e7b
https://github.com/llvm/llvm-project/commit/34e9f3d6e3757d4e6a13a3f3df32a134933b6e7b
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/IR/OpBase.td
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Target/LLVMIR/ptr.mlir
Log Message:
-----------
[mlir][ptr] Add `gather`, `masked_load`, `masked_store`, and `scatter` ops (#156368)
This patch adds the `gather`, `masked_load`, `masked_store`, and
`scatter` operations to the `ptr` dialect. It also implements
translation from these operations to LLVM intrinsics:
- ptr.gather -> llvm.masked.gather
- ptr.masked_load -> llvm.masked.load
- ptr.masked_store -> llvm.masked.store
- ptr.scatter -> llvm.masked.scatter
Example:
```mlir
llvm.func @mixed_masked_ops_address_spaces(%ptr: !ptr.ptr<#llvm.address_space<3>>, %ptrs: vector<4x!ptr.ptr<#llvm.address_space<3>>>,
%mask: vector<4xi1>, %value: vector<4xf64>, %passthrough: vector<4xf64>) {
%0 = ptr.gather %ptrs, %mask, %passthrough alignment = 8 : vector<4x!ptr.ptr<#llvm.address_space<3>>> -> vector<4xf64>
ptr.scatter %value, %ptrs, %mask alignment = 8 : vector<4xf64>, vector<4x!ptr.ptr<#llvm.address_space<3>>>
%1 = ptr.masked_load %ptr, %mask, %passthrough alignment = 8 : !ptr.ptr<#llvm.address_space<3>> -> vector<4xf64>
ptr.masked_store %value, %ptr, %mask alignment = 8 : vector<4xf64>, !ptr.ptr<#llvm.address_space<3>>
llvm.return
}
```
Translates to:
```llvm
define void @mixed_masked_ops_address_spaces(ptr addrspace(3) %0, <4 x ptr addrspace(3)> %1, <4 x i1> %2, <4 x double> %3, <4 x double> %4) {
%6 = call <4 x double> @llvm.masked.gather.v4f64.v4p3(<4 x ptr addrspace(3)> %1, i32 8, <4 x i1> %2, <4 x double> %4)
call void @llvm.masked.scatter.v4f64.v4p3(<4 x double> %3, <4 x ptr addrspace(3)> %1, i32 8, <4 x i1> %2)
%7 = call <4 x double> @llvm.masked.load.v4f64.p3(ptr addrspace(3) %0, i32 8, <4 x i1> %2, <4 x double> %4)
call void @llvm.masked.store.v4f64.p3(<4 x double> %3, ptr addrspace(3) %0, i32 8, <4 x i1> %2)
ret void
}
```
Commit: e8755e71c770bf65a26842ed68262336d2508dfc
https://github.com/llvm/llvm-project/commit/e8755e71c770bf65a26842ed68262336d2508dfc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/PriorityWorklist.h
Log Message:
-----------
[ADT] "Inline" TestAndEraseFromMap into PriorityWorklist.h (NFC) (#156596)
TestAndEraseFromMap is used only from PriorityWorklist::erase_if.
This patch "inlines" the struct into its sole user in the form of a
lambda function, eliminating a lot of boilerplate code.
Commit: 07e30043117c87f30a4505f2858a27ed0e2ea012
https://github.com/llvm/llvm-project/commit/07e30043117c87f30a4505f2858a27ed0e2ea012
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
Log Message:
-----------
[Support] Modernize YAML traits with is_detected (NFC) (#156598)
This patch modernizes has_* YAML traits with is_detected.
The resulting code should be a lot more readable because all the
SFINAE logic is hidden behind is_detected.
One note about has_FlowTraits. The original code uses a complex trick
to detect a member variable named "flow", intentionally triggering
ambiguity with "flow" in the two base classes. I've simplified the
check down to:
template <class U> using check = decltype(&U::flow);
without using SameType. The use of SameType here would make the trait
unnecessarily complicated.
While I am at it, this patch switches to "static constexpr bool".
Commit: d77aafbeee174449d590aaef656ea7f5ea001303
https://github.com/llvm/llvm-project/commit/d77aafbeee174449d590aaef656ea7f5ea001303
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Remove an unnecessary cast (NFC) (#156599)
getSExtValue already returns int64_t.
Commit: 94e0c46498e061d8d40774417ce121904c8c4524
https://github.com/llvm/llvm-project/commit/94e0c46498e061d8d40774417ce121904c8c4524
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
Log Message:
-----------
[RISCV] Remove an unnecessary cast (NFC) (#156600)
*MF is already non const.
Commit: fd2a21d41abf3a1b33824db740272d9d8ab25a6d
https://github.com/llvm/llvm-project/commit/fd2a21d41abf3a1b33824db740272d9d8ab25a6d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/docs/AddingConstrainedIntrinsics.rst
Log Message:
-----------
[llvm] Proofread AddingConstrainedIntrinsics.rst (#156601)
Commit: d25d8309d173f81bc26babf9964d4d021b76a4af
https://github.com/llvm/llvm-project/commit/d25d8309d173f81bc26babf9964d4d021b76a4af
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
Log Message:
-----------
[NFC] Remove trailing whitespaces from two files
Commit: 25a304559a7aba8ea7035dd68af2d9078a1a2826
https://github.com/llvm/llvm-project/commit/25a304559a7aba8ea7035dd68af2d9078a1a2826
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Log Message:
-----------
[lldb][ExpressionParser][NFC] Clean up expression language picking logic (#156642)
This patch moves the `frame_lang` logic to just the logging (because
that's what it was always used for anyway). The callsites decide whether
to fall back on to the frame language or not when running the
expression.
Commit: fd6a2b84e7a9c4d345eea2b07bce65311f02c75f
https://github.com/llvm/llvm-project/commit/fd6a2b84e7a9c4d345eea2b07bce65311f02c75f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Log Message:
-----------
[NFC][MC][ARM] Rearrange decoder functions 3/N (#156240)
Commit: 9d7449a82b83ee589b8af8d6f86525727788b3b9
https://github.com/llvm/llvm-project/commit/9d7449a82b83ee589b8af8d6f86525727788b3b9
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/ARM/MVETailPredication.cpp
Log Message:
-----------
[NFC][LLVM] Use `INITILIZE_PASS` instead of `INITIALIZE_PASS_BEGIN/END` (#156212)
Commit: 53fce759fb35f2a162bc7bcc1e56911643b0e7a8
https://github.com/llvm/llvm-project/commit/53fce759fb35f2a162bc7bcc1e56911643b0e7a8
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang-tools-extra/clang-tidy/readability/UppercaseLiteralSuffixCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp
Log Message:
-----------
[clang-tidy] Fix `readability-uppercase-literal-suffix` warning with hex literals (#156584)
This is a regression I introduced in #148275 and was [noticed
by](https://github.com/llvm/llvm-project/pull/148275#issuecomment-3246670841)
nettle. The check incorrectly fires on hex literals containing the
letter `b`.
(I felt a revert was unnecessary in this case. Maybe others disagree?)
Commit: a2693dc192366372da4170c82d1b0719066ded95
https://github.com/llvm/llvm-project/commit/a2693dc192366372da4170c82d1b0719066ded95
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/scan_messages.cpp
M clang/test/OpenMP/target_data_use_device_addr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_messages.cpp
M clang/test/OpenMP/task_in_reduction_message.cpp
M clang/test/OpenMP/taskgroup_task_reduction_messages.cpp
M clang/test/OpenMP/teams_reduction_messages.cpp
Log Message:
-----------
[clang][OpenMP] 6.0: detect privatization of array section/assumed-size array (#152786)
According to the OpenMP 6.0 specification, array sections with no length
and unknown size are considered assumed-size arrays. As of pull request
https://github.com/llvm/llvm-project/pull/148048
these types of array sections are allowed and can be specified in
clauses that allow array sections as list items. However, only two
clauses explicitly allow array sections that are assumed-size arrays:
- 'map' and 'use_device_addr'.
The other clauses that accept array sections do not explicitly accept
assumed-size arrays:
- inclusive, exclusive, has_device_addr, in_reduction, task_reduction,
reduction These cases should generate an error. See OpenMP 6.0
specification section 7.4 List Item Privatization, Restrictions, p. 222,
L15
Assumed-size arrays must not be privatized
For OpenMP 6.0, function getPrivateItem() now checks for array section
list items that are assumed-size arrays and generates an error if they
are not allowed for the clause.
Testing
- Updated LIT tests for assumed-size array sections to ensure these
clauses generate an error: inclusive, exclusive, has_device_addr,
in_reduction, task_reduction, reduction and that this clause is accepted
(codegen test): use_device_addr
- check-all
- OpenMP_VV (sollve_vv)
Commit: 5cf12458433a74859a5d90c8e5163ba1b2b717f5
https://github.com/llvm/llvm-project/commit/5cf12458433a74859a5d90c8e5163ba1b2b717f5
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/unittests/Target/RISCV/CMakeLists.txt
Log Message:
-----------
Fix build break in RISCV unit tests
/usr/bin/ld: unittests/Target/RISCV/CMakeFiles/RISCVTests.dir/RISCVSelectionDAGTest.cpp.o: undefined reference to symbol '_ZN4llvm19parseAssemblyStringENS_9Stri
ngRefERNS_12SMDiagnosticERNS_11LLVMContextEPNS_11SlotMappingE'
/usr/bin/ld: lib/libLLVMAsmParser.so.22.0git:
error adding symbols: DSO missing from command line
collect2: error: ld returned 1 exit status
Commit: 28646140110f11e83926b0e48ce052d1de1c4a04
https://github.com/llvm/llvm-project/commit/28646140110f11e83926b0e48ce052d1de1c4a04
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for d15998fe64619e1cc0d6285fbd24d5fe5429c9ef
Commit: 1efbd8e62cfb5aedd791396c7ca854066e027d33
https://github.com/llvm/llvm-project/commit/1efbd8e62cfb5aedd791396c7ca854066e027d33
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
Log Message:
-----------
[bazel][mlir] Port #156355: translations to LLVMIR for ptr ops (#156689)
Commit: 329b21505a5f26d85955664943b0e0ac3411e11b
https://github.com/llvm/llvm-project/commit/329b21505a5f26d85955664943b0e0ac3411e11b
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/test/Transforms/debug-allocatable-1.fir
M flang/test/Transforms/debug-assumed-rank-array.fir
M flang/test/Transforms/debug-assumed-shape-array-2.fir
M flang/test/Transforms/debug-assumed-shape-array.fir
M flang/test/Transforms/debug-ptr-type.fir
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
Log Message:
-----------
[MLIR][LLVM][Flang] Move the element param of DICompositeType to the end (#156624)
This commit moves the "element" param of `DICompositeType` to the end of
the parameter list. This is required as there seems to be a bug in the
attribute parser that breaks a print + parse roundtrip.
Related ticket: https://github.com/llvm/llvm-project/issues/156623
Commit: 99f61f34362b77c42c8261213256854516c7485d
https://github.com/llvm/llvm-project/commit/99f61f34362b77c42c8261213256854516c7485d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M offload/test/CMakeLists.txt
Log Message:
-----------
[Offload] Run unit tests as a part of check-offload (#156675)
Summary:
Add a dependnecy on the unit tests on the main check-offload test suite.
This matches what the other projects do, pass `llvm-lit` to the
directory to only run the lit tests, use the `check-offload-unit` for
only the unit tests.
Commit: 696590c07de868637e224502484d9847a691db20
https://github.com/llvm/llvm-project/commit/696590c07de868637e224502484d9847a691db20
Author: Benjamin Barenblat <bbaren at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/WORKSPACE
Log Message:
-----------
[bazel][libc] Update MPFR to v4.2.2 (#156691)
Use MPFR v4.2.2 rather than MPFR v4.1.1 for Bazel/Clang builds to avoid
conflicts with glibc’s `__float128` fallback typedef. See
https://gitlab.inria.fr/mpfr/mpfr/-/commit/c37c9d599b9aced92e182507bf223440bbc9a9f1
for further details.
Fixes https://github.com/llvm/llvm-project/issues/147879
Commit: 2a486148d754829a3ed16e1c4265f24d19cd3783
https://github.com/llvm/llvm-project/commit/2a486148d754829a3ed16e1c4265f24d19cd3783
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Port #153661: LifetimeSafetyTest dep (#156697)
Commit: fee17b3a96c29ddef59103bd7c02568f748e37ab
https://github.com/llvm/llvm-project/commit/fee17b3a96c29ddef59103bd7c02568f748e37ab
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/user-sgpr-count-diag.s
M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
M llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verify-av-mov-imm-pseudo.mir
M llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
M llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
M llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
M llvm/test/Verifier/AMDGPU/intrinsic-prefetch.ll
M llvm/test/Verifier/AMDGPU/mfma-scale.ll
M llvm/test/Verifier/AMDGPU/wmma-f8f6f4.ll
Log Message:
-----------
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
Using options like -filetype=null instead should allow tools to save
some work by not generating any output.
Commit: 7d6e72f11033685af069e40697cd9fc0bad0a682
https://github.com/llvm/llvm-project/commit/7d6e72f11033685af069e40697cd9fc0bad0a682
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
R llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add.ll
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir
Log Message:
-----------
[RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD (#155972)
RISCV does not provide a native atomic subtract instruction, so this
patch lowers `G_ATOMICRMW_SUB` by negating the RHS value and performing
an atomic add. The legalization rules in `RISCVLegalizerInfo` are
updated accordingly, with libcall fallbacks when `StdExtA` is not
available, and intrinsic legalization is extended to support
`riscv_masked_atomicrmw_sub`.
For example, lowering
`%1 = atomicrmw sub ptr %a, i32 1 seq_cst`
on riscv32a produces:
```
li a1, -1
amoadd.w.aqrl a0, a1, (a0)
```
On riscv64a, where the RHS type is narrower than XLEN, it currently
produces:
```
li a1, 1
neg a1, a1
amoadd.w.aqrl a0, a1, (a0)
```
There is still a constant-folding or InstConbiner gap. For instance,
lowering
```
%b = sub i32 %x, %y
%1 = atomicrmw sub ptr %a, i32 %b seq_cst
```
generates:
```
subw a1, a1, a2
neg a1, a1
amoadd.w.aqrl a0, a1, (a0)
```
This sequence could be optimized further to eliminate the redundant neg.
Addressing this may require improvements in the Combiner or Peephole
Optimizer in future work.
---------
Co-authored-by: Kane Wang <kanewang95 at foxmail.com>
Commit: d91a5c33df2e53c757c68b0a893d4654993fa3a5
https://github.com/llvm/llvm-project/commit/d91a5c33df2e53c757c68b0a893d4654993fa3a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/implied-by-bounded-memory-access.ll
Log Message:
-----------
[ConstraintElim] Bail out on non-canonical GEPs (#156688)
In most cases, GEPs should be canonicalized by InstCombine. Bail out on
non-canonical forms for simplicity.
Fixes
https://github.com/llvm/llvm-project/pull/155253#issuecomment-3248457478.
Commit: bad2036c6ef13e4b44fdea527c3f6ea49033358d
https://github.com/llvm/llvm-project/commit/bad2036c6ef13e4b44fdea527c3f6ea49033358d
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/test/Conversion/PtrToLLVM/ptr-to-llvm.mlir
M mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Target/LLVMIR/ptr.mlir
Log Message:
-----------
[mlir][ptr] Extend `ptr_add` operation to support shaped operands (#156374)
This patch extends `ptr_add` to work with shaped types with value
semantics, both for the offsets and base.
Concretely this patch makes the following changes:
- Supports scalar-to-scalar, scalar-to-shaped, shaped-to-scalar, and
shaped-to-shaped combinations
- Adds InferTypeOpInterface for automatic result type deduction
- Adds tests for LLVM IR translation with vector operands
Example:
```mlir
func.func @ptr_add_tensor_2d(%ptrs: tensor<4x8x!ptr.ptr<#ptr.generic_space>>, %offsets: tensor<4x8xindex>) -> tensor<4x8x!ptr.ptr<#ptr.generic_space>> {
%res = ptr.ptr_add %ptrs, %offsets : tensor<4x8x!ptr.ptr<#ptr.generic_space>>, tensor<4x8xindex>
%res1 = ptr.ptr_add nuw %ptrs, %offsets : tensor<4x8x!ptr.ptr<#ptr.generic_space>>, tensor<4x8xindex>
return %res : tensor<4x8x!ptr.ptr<#ptr.generic_space>>
}
```
The motivation behind this patch is to lay the groundwork for enabling
`triton` styled loads and stores, and their variants.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: 527c8ff11e4b05e3502a46a5ad52bb7f0da5ed2a
https://github.com/llvm/llvm-project/commit/527c8ff11e4b05e3502a46a5ad52bb7f0da5ed2a
Author: cmtice <cmtice at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/utils/lit/lit/ShUtil.py
M llvm/utils/lit/tests/unit/ShUtil.py
Log Message:
-----------
[lit] Update internal shell lexer to handle LLDB persistent vars. (#156125)
LLDB allows creation of 'persistent' variables, with names that start
with '$'. The lit internal shell was escaping the '$', making it '\\$',
in some CHECK lines, which causes an LLDB test,
TestExprWithSideEffectOnConvenienceVar, to fail when using the lit
internal shell.
Further explanation of the failing LLDB test: LLDB convenience variables
start with '$'. The test passes several quoted commands that use and
update convenience variables to lldb as arguments to be run in batch
mode. The tool that packages up the complete string and passes it to the
lit internal shell lexer for lexing inserts a backslash in front of the
'$' before passing the string in for lexing. The lexer was passing this
change along, causing the tests to fail.
This PR fixes the issue by having the lexer remove the newly added
escape on the '$'.
Commit: e75f054d18c426b421d7d4cc58342fcb60047cfc
https://github.com/llvm/llvm-project/commit/e75f054d18c426b421d7d4cc58342fcb60047cfc
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/MachO/Driver.cpp
A lld/test/MachO/read-workers.s
Log Message:
-----------
[lld][MachO] Silence warnings about --read-workers parsing (#156608)
The parsing of the --read-workers argument v is implemented like this:
unsigned threads = 0
if (!llvm::to_integer(v, threads, 0) || threads < 0) {
...
As reported by a compiler warning, the value of the "threads < 0"
expession is never going to be true. It could only evaluate to true if v
represents a negative number, but in this case llvm::to_integer returns
false since threads is unsigned and hence the second operand of the ||
operator will not be evaluated.
This patch removes the useless || operand to silence compiler warnings.
Since I had to first find out if --read-workers=0 is valid or not (it is),
I also added a test to document the valid values for the option and I adjusted
the error message on invalid values to clearly state that 0 is valid.
Commit: df9965cb5a116c4f8c07bff8349d9bf342d9c96f
https://github.com/llvm/llvm-project/commit/df9965cb5a116c4f8c07bff8349d9bf342d9c96f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/COFF/color-diagnostics.test
M lld/test/COFF/linkrepro-res.test
M lld/test/COFF/linkrepro.test
M lld/test/ELF/arm-exidx-range.s
M lld/test/ELF/color-diagnostics.test
M lld/test/ELF/file-access.s
M lld/test/ELF/linkerscript/invalid.test
M lld/test/ELF/lto/resolution-err.ll
M lld/test/MachO/color-diagnostics.test
M lld/test/MachO/framework.s
M lld/test/MachO/implicit-and-allowable-clients.test
M lld/test/MachO/link-search-at-loader-path-symlink.s
M lld/test/MachO/reexport-with-symlink.s
M lld/test/MachO/reexport-without-rpath.s
M lld/test/MachO/reproduce.s
M lld/test/MachO/tapi-rpath.s
M lld/test/wasm/reproduce.s
Log Message:
-----------
[lld] Remove shell requirements from tests
These tests all pass inside the lit internal shell. A couple were marked
as requiring a shell to exclude them on Windows. Update those tests to
explicitly carve out Windows rather than any configuration that does not
provide the shell feature.
Towards #102700.
Reviewers: petrhosek, cmtice, mysterymath, MaskRay, ilovepi
Reviewed By: cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/156510
Commit: 42f181a6b52c1acc81f6876fdab06b7a7027bfd8
https://github.com/llvm/llvm-project/commit/42f181a6b52c1acc81f6876fdab06b7a7027bfd8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M bolt/runtime/instr.cpp
A bolt/test/runtime/copy_file.py
M bolt/test/runtime/instrumentation-indirect-2.c
M clang-tools-extra/clang-tidy/readability/UppercaseLiteralSuffixCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCall.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/fmaintrin.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
R clang/lib/StaticAnalyzer/Checkers/CastSizeChecker.cpp
M clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp
R clang/test/AST/ast-dump-labeled-break-continue-json.c
R clang/test/Analysis/castsize.c
A clang/test/Analysis/ctu-import-type-decl-definition.c
M clang/test/Analysis/malloc-annotations.c
M clang/test/Analysis/malloc-annotations.cpp
M clang/test/Analysis/malloc.c
M clang/test/Analysis/malloc.cpp
M clang/test/Analysis/misc-ps.m
A clang/test/Analysis/model-file-missing.cpp
M clang/test/Analysis/qt_malloc.cpp
A clang/test/CIR/CodeGen/volatile.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
A clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-unsigned-int.c
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
M clang/test/CodeGen/X86/avx512f-builtins.c
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-cluster-load.cl
M clang/test/DebugInfo/CXX/structured-binding.cpp
M clang/test/OpenMP/error_message.cpp
M clang/test/OpenMP/scan_messages.cpp
A clang/test/OpenMP/spirv_locstr.cpp
M clang/test/OpenMP/target_data_use_device_addr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_messages.cpp
M clang/test/OpenMP/task_in_reduction_message.cpp
M clang/test/OpenMP/taskgroup_task_reduction_messages.cpp
M clang/test/OpenMP/teams_reduction_messages.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags-std.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags.cpp
M clang/test/SemaOpenACC/combined-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/compute-construct-reduction-clause.c
M clang/test/SemaOpenACC/compute-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/www/features.html
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/test/asan/TestCases/zero_alloc.cpp
M compiler-rt/test/msan/zero_alloc.cpp
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/lldb/LLDB.py
M flang-rt/lib/runtime/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Semantics/check-call.cpp
M flang/test/Driver/atomic-control-options.f90
M flang/test/Semantics/reduce01.f90
M flang/test/Transforms/debug-allocatable-1.fir
M flang/test/Transforms/debug-assumed-rank-array.fir
M flang/test/Transforms/debug-assumed-shape-array-2.fir
M flang/test/Transforms/debug-assumed-shape-array.fir
M flang/test/Transforms/debug-ptr-type.fir
M flang/tools/f18/CMakeLists.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/dl_info.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/math.yaml
M libc/src/__support/CPP/simd.h
M libc/src/__support/threads/thread.cpp
M libc/src/__support/threads/thread.h
M libc/src/dlfcn/CMakeLists.txt
M libc/src/dlfcn/dladdr.cpp
M libc/src/dlfcn/dladdr.h
M libc/src/math/CMakeLists.txt
A libc/src/math/atanpif16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/atanpif16.cpp
M libc/src/stdlib/exit.cpp
M libc/src/string/memory_utils/generic/inline_strlen.h
M libc/test/integration/src/__support/threads/CMakeLists.txt
A libc/test/integration/src/__support/threads/double_exit_test.cpp
A libc/test/integration/src/__support/threads/main_exit_test.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/atanpif16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/atanpif16_test.cpp
M libc/utils/MPFRWrapper/MPCommon.cpp
M libc/utils/MPFRWrapper/MPCommon.h
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
M libclc/clc/include/clc/clc_convert.h
R libclc/clc/include/clc/clcmacro.h
M libclc/clc/lib/amdgcn/math/clc_ldexp_override.cl
M libclc/clc/lib/amdgpu/math/clc_native_exp2.cl
M libclc/clc/lib/amdgpu/math/clc_sqrt_fp64.cl
M libclc/clc/lib/clspv/math/clc_sw_fma.cl
M libclc/clc/lib/generic/common/clc_degrees.cl
M libclc/clc/lib/generic/common/clc_radians.cl
M libclc/clc/lib/generic/common/clc_smoothstep.cl
M libclc/clc/lib/generic/common/clc_step.cl
M libclc/clc/lib/generic/integer/clc_clz.cl
M libclc/clc/lib/generic/integer/clc_ctz.cl
M libclc/clc/lib/generic/integer/clc_mad_sat.cl
M libclc/clc/lib/generic/math/clc_cbrt.cl
M libclc/clc/lib/generic/math/clc_cos.cl
M libclc/clc/lib/generic/math/clc_exp10.cl
M libclc/clc/lib/generic/math/clc_fmod.cl
M libclc/clc/lib/generic/math/clc_fract.cl
M libclc/clc/lib/generic/math/clc_frexp.inc
M libclc/clc/lib/generic/math/clc_hypot.cl
M libclc/clc/lib/generic/math/clc_ilogb.cl
M libclc/clc/lib/generic/math/clc_ldexp.cl
M libclc/clc/lib/generic/math/clc_lgamma_r.cl
M libclc/clc/lib/generic/math/clc_log.cl
M libclc/clc/lib/generic/math/clc_log10.cl
M libclc/clc/lib/generic/math/clc_log2.cl
M libclc/clc/lib/generic/math/clc_logb.cl
M libclc/clc/lib/generic/math/clc_nextafter.cl
M libclc/clc/lib/generic/math/clc_pow.cl
M libclc/clc/lib/generic/math/clc_pown.cl
M libclc/clc/lib/generic/math/clc_powr.cl
M libclc/clc/lib/generic/math/clc_remainder.cl
M libclc/clc/lib/generic/math/clc_remquo.cl
M libclc/clc/lib/generic/math/clc_sin.cl
M libclc/clc/lib/generic/math/clc_sw_fma.cl
M libclc/clc/lib/generic/relational/clc_bitselect.cl
M libclc/clc/lib/r600/math/clc_native_rsqrt.cl
M libclc/clc/lib/r600/math/clc_rsqrt_override.cl
M libclc/clc/lib/spirv/math/clc_fmax.cl
M libclc/clc/lib/spirv/math/clc_fmin.cl
M libclc/opencl/lib/generic/common/sign.cl
M libclc/opencl/lib/generic/common/smoothstep.cl
M libclc/opencl/lib/generic/math/atan2.cl
M libclc/opencl/lib/generic/math/atan2pi.cl
M libclc/opencl/lib/generic/math/log.cl
M libclc/opencl/lib/generic/math/log10.cl
M libclc/opencl/lib/generic/math/log2.cl
M libclc/opencl/lib/generic/math/nan.cl
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__config
M libcxx/include/__cxx03/bitset
M libcxx/include/__cxx03/forward_list
M libcxx/include/__cxx03/list
M libcxx/include/__functional/function.h
M libcxx/include/__ranges/as_rvalue_view.h
M libcxx/include/__tree
M libcxx/include/__type_traits/invoke.h
M libcxx/include/map
M libcxx/include/mutex
M libcxx/include/set
A libcxx/test/extensions/clang/thread/thread.mutex/lock.verify.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/set/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/forwardlist/types.pass.cpp
M libcxx/test/std/containers/sequences/list/types.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.as.rvalue/adaptor.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/index_const.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/nonstdmem.uglified.compile.pass.cpp
M lld/MachO/Driver.cpp
A lld/test/MachO/read-workers.s
M lldb/bindings/interface/SBStructuredDataExtensions.i
M lldb/include/lldb/Host/File.h
M lldb/source/Commands/Options.td
M lldb/source/Host/common/File.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/test/API/python_api/sbstructureddata/TestStructuredDataAPI.py
M lldb/test/Shell/SymbolFile/NativePDB/Inputs/incomplete-tag-type.cpp
R lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.cpp
A lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.test
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/AddingConstrainedIntrinsics.rst
M llvm/docs/LangRef.rst
M llvm/include/llvm/ADT/PriorityWorklist.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/CodeGen/ExpandFp.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Debuginfod/Debuginfod.h
M llvm/include/llvm/Debuginfod/HTTPServer.h
M llvm/include/llvm/IR/GEPNoWrapFlags.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/ExpandFp.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/Debuginfod/HTTPServer.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DebugOptions.h
M llvm/lib/Support/TypeSize.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MVETailPredication.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-extract.ll
A llvm/test/Analysis/CostModel/AArch64/sve-vls-shuffle-extract.ll
M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
A llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
A llvm/test/CodeGen/AArch64/scalable_masked_deinterleaved_loads.ll
M llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
A llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
A llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
A llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/applypriority.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/b52037.ll
M llvm/test/CodeGen/NVPTX/barrier.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bmsk.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/byval-arg-vectorize.ll
M llvm/test/CodeGen/NVPTX/byval-const-global.ll
M llvm/test/CodeGen/NVPTX/calling-conv.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/combine-min-max.ll
M llvm/test/CodeGen/NVPTX/common-linkage.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/convert-call-to-indirect.ll
M llvm/test/CodeGen/NVPTX/convert-fp.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm89.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/NVPTX/discard.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16-ex2.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
M llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fold-movs.ll
M llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/griddepcontrol.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/prefetch-inferas-test.ll
M llvm/test/CodeGen/NVPTX/prefetch.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/st_bulk.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/surf-tex.py
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/szext.ll
M llvm/test/CodeGen/NVPTX/tanhf.ll
M llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
M llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
M llvm/test/CodeGen/NVPTX/tcgen05-fence.ll
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M llvm/test/CodeGen/NVPTX/trunc-setcc.ll
M llvm/test/CodeGen/NVPTX/trunc-tofp.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/vaargs.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vector-compare.ll
M llvm/test/CodeGen/NVPTX/vector-select.ll
M llvm/test/CodeGen/NVPTX/vote.ll
M llvm/test/CodeGen/NVPTX/weak-global.ll
M llvm/test/CodeGen/NVPTX/wgmma-sm90a-fence.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx60-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx61-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm72.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx64-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx65-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx71-sm80.py
M llvm/test/CodeGen/NVPTX/wmma-ptx78-sm90.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm100a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm101a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py
A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
R llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add.ll
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
M llvm/test/CodeGen/RISCV/xqcibm-insbi.ll
M llvm/test/CodeGen/WebAssembly/global-set.ll
M llvm/test/CodeGen/X86/bswap-inline-asm.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
A llvm/test/CodeGen/X86/pr156256.ll
M llvm/test/DebugInfo/NVPTX/dbg-value-const-byref.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
M llvm/test/MC/AMDGPU/user-sgpr-count-diag.s
M llvm/test/MC/AMDGPU/vop3-literal.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
M llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verify-av-mov-imm-pseudo.mir
M llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
M llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/Transforms/ConstraintElimination/implied-by-bounded-memory-access.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem-inf.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/lit.local.cfg
A llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
M llvm/test/Transforms/InstCombine/gep-canonicalize-constant-indices.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size-needs-loop-guards.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/many-uses-fma-candidate.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
M llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
M llvm/test/Verifier/AMDGPU/intrinsic-prefetch.ll
M llvm/test/Verifier/AMDGPU/mfma-scale.ll
M llvm/test/Verifier/AMDGPU/wmma-f8f6f4.ll
M llvm/test/lit.cfg.py
A llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
M llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Target/RISCV/CMakeLists.txt
A llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp
M llvm/utils/lit/lit/ShUtil.py
M llvm/utils/lit/tests/unit/ShUtil.py
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/EnumAttr.td
M mlir/include/mlir/IR/OpBase.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
A mlir/lib/Dialect/SPIRV/IR/ArmGraphOps.cpp
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
M mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
A mlir/test/Conversion/FuncToLLVM/func-to-llvm-datalayout.mlir
M mlir/test/Conversion/PtrToLLVM/ptr-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
M mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/SPIRV/IR/availability.mlir
A mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/IR/array-of-attr.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-cp.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-shift.mlir
M mlir/test/Target/LLVMIR/ptr.mlir
M mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/test/mlir-tblgen/attr-or-type-format.td
M mlir/test/python/ir/operation.py
M offload/test/CMakeLists.txt
M offload/test/offloading/mandatory_but_no_devices.c
M offload/test/offloading/memory_manager.cpp
M utils/bazel/WORKSPACE
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/3086dc6d9cf5...42f181a6b52c
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list