[all-commits] [llvm/llvm-project] f07ab3: [AArch64][ISel] Select constructive EXT_ZZZI pseud...

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/users/gbossu.vector.extract.movprfx.3
  Home:   https://github.com/llvm/llvm-project
  Commit: f07ab3218a15f36ab04fc70f4a78134ff477c3eb
      https://github.com/llvm/llvm-project/commit/f07ab3218a15f36ab04fc70f4a78134ff477c3eb
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2025-08-07 (Thu, 07 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-pr92779.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll

  Log Message:
  -----------
  [AArch64][ISel] Select constructive EXT_ZZZI pseudo instruction

The patch changes existing patterns to select the EXT_ZZZI pseudo
instead of the EXT_ZZI destructive instruction for vector_splice.

Given that registers aren't tied anymore, this gives the register
allocator more freedom and a lot of MOVs get replaced with MOVPRFX.

In some cases however, we could have just chosen the same input and
output register, but regalloc preferred not to. This means we end up
with some test cases now having more instructions: there is now a
MOVPRFX while no MOV was previously needed.


  Commit: 56ac99a1339398b952815334df020c568d079bda
      https://github.com/llvm/llvm-project/commit/56ac99a1339398b952815334df020c568d079bda
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2025-08-07 (Thu, 07 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

  Log Message:
  -----------
  [AArch64] WIP Regalloc hints for EXT_ZZZI

This tries to ensure that the dst and first src register are mapped to
the same physical register. This isn't always possible because the
MachineScheduler has already moved instructions in a way that causes
interferences if both virt regs get mapped to the same phys reg.

WIP because there is probably a better place to do this.


Compare: https://github.com/llvm/llvm-project/compare/f07ab3218a15%5E...56ac99a13393

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