[all-commits] [llvm/llvm-project] e6f360: [MLIR][XeGPU] Allow load/store/prefetch uses [memr...
Stanislav Mekhanoshin via All-commits
all-commits at lists.llvm.org
Wed Jul 30 16:17:02 PDT 2025
Branch: refs/heads/users/rampitec/07-30-_amdgpu_add_v_ashr_pk_i8_i32_and_v_ashr_pk_u8_i32_on_gfx1250
Home: https://github.com/llvm/llvm-project
Commit: e6f360b0ab6573bf9d3bb0e42445a20c93eea8b1
https://github.com/llvm/llvm-project/commit/e6f360b0ab6573bf9d3bb0e42445a20c93eea8b1
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Allow load/store/prefetch uses [memref+offset] instead of tdesc (#150576)
Add variant of load/store/prefetch to allow offset. The new xegpu.load
variant accepts memref+offset, and the existing tdesc operand will be
removed in the future PR.
The semantics are combination of "creating scattered_tdesc + xegpu.load
with scattered_tdesc". The current xegpu.load accepts tdesc operand,
which encapsulates "memref+offset". This PR "fold" "memref+offset"
directly to xegpu.load replacing "tdesc". Create_tdesc will be removed
as scatter_tdesc only contains base address after offsets being taken
away, so there is no point to keep it.
```mlir
// wi level code example
%2 = xegpu.load %src[%offsets], %mask <{chunk_size = 2}> : ui64, vector<1xindex>, vector<1xi1> -> vector<2xf32>
xegpu.store %val, %src[%offsets], %mask: vector<1xf16>, memref<?xf16>, vector<1xindex>, vector<1xi1>
xegpu.prefetch %src[%0] : ui64, vector<1xindex>
```
Commit: ed940d7228aec95e994be848f1e42eab2a7fa7f3
https://github.com/llvm/llvm-project/commit/ed940d7228aec95e994be848f1e42eab2a7fa7f3
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
Log Message:
-----------
[DWARFLinker] Fix matching logic to remove type 1 missing offsets (#149618)
Second attempt to fix
https://discourse.llvm.org/t/rfc-new-dwarf-attribute-for-symbolication-of-merged-functions/79434/29?u=alx32
(First attempt: https://github.com/llvm/llvm-project/pull/143656)
Context: the sequence offset to row index we parsed may not be complete.
And we need to add manual matching to it.
https://github.com/llvm/llvm-project/pull/143656 attempts to do trivial
1:1 matching, however, sometimes they don't line up perfectly, as shown
below:
```
// While SeqOffToOrigRow parsed from CU could be the ground truth,
// e.g.
//
// SeqOff Row
// 0x08 9
// 0x14 15
//
// The StmtAttrs and SeqStartRows may not match perfectly, e.g.
//
// StmtAttrs SeqStartRows
// 0x04 3
// 0x08 5
// 0x10 9
// 0x12 11
// 0x14 15
//
// In this case, we don't want to assign 5 to 0x08, since we know 0x08
// maps to 9. If we do a dummy 1:1 mapping 0x10 will be mapped to 9
// which is incorrect. The expected behavior is ignore 5, realign the
// table based on the result from the line table:
//
// StmtAttrs SeqStartRows
// 0x04 3
// -- 5
// 0x08 9 <- LineTableMapping ground truth
// 0x10 11
// 0x12 --
// 0x14 15 <- LineTableMapping ground truth
```
In this case, we need to use the mapping we read from the line table as
a ground truth and organize them properly to prevent duplicated
offset/missing offset.
Test:
Updated the test case
---------
Signed-off-by: Peter Rong <PeterRong at meta.com>
Commit: 7d2332391f81d44d7c9d1ca40bd5f393c59ad0df
https://github.com/llvm/llvm-project/commit/7d2332391f81d44d7c9d1ca40bd5f393c59ad0df
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
Log Message:
-----------
[AMDGPU] Fix destination op_sel for v_cvt_scale32_* and v_cvt_sr_* (#151411)
GFX950 uses OP_SEL[MSB:LSB] for both src reads and dest writes. So this
patch essentially revert the work from
https://github.com/llvm/llvm-project/pull/151286 regarding dest writes.
Commit: af809841826513bd617ad8a1f1ffec2268423286
https://github.com/llvm/llvm-project/commit/af809841826513bd617ad8a1f1ffec2268423286
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
Merge branch 'main' into users/rampitec/07-30-_amdgpu_add_v_ashr_pk_i8_i32_and_v_ashr_pk_u8_i32_on_gfx1250
Compare: https://github.com/llvm/llvm-project/compare/b0f03f13073b...af8098418265
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