[all-commits] [llvm/llvm-project] b10331: [TableGen] Check destination instruction predicate...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b103311c1d75bb00845e0160fce76d75fe2377d3
      https://github.com/llvm/llvm-project/commit/b103311c1d75bb00845e0160fce76d75fe2377d3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/test/TableGen/CompressInstEmitter/suboperands.td
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen] Check destination instruction predicates in CompressInstEmitter. (#151061)

In addition to checking the predicate from the CompressPat, also check
the destination instruction. This prevents creating bad instructions if
CompressPat isn't a proper subset of the destination instruction. This
prevents mistakes that we can't catch at compile time.

We are able to verify RegisterClass hierarchy at compile time so don't
have to check the destination register class.

I've added comments for the operand names to make auditing easier.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications