[all-commits] [llvm/llvm-project] dbcbdc: [RISCV] Add IsSignExtendingOpW to P-ext CLS, CLSW, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbcbdc4da0a9f4627562c305492b4464afe5b467
      https://github.com/llvm/llvm-project/commit/dbcbdc4da0a9f4627562c305492b4464afe5b467
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td

  Log Message:
  -----------
  [RISCV] Add IsSignExtendingOpW to P-ext CLS, CLSW, and ABSW instructions. (#151037)

This matches other W instructions. CLS is included since it can only
return 0-64 which has bits [63:31] as zero. This is similar to CLZ.

This doesn't do anything yet since we don't have CodeGen support for P.



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