[all-commits] [llvm/llvm-project] 4e3266: [RISCV] Implement load/store support for XAndesBFH...

Thu Jul 24 23:28:46 PDT 2025

  Branch: refs/heads/users/MaskRay/spr/mc-allocate-initial-fragment-and-define-section-symbol-in-changesection
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e3266fb6e40dedf99e25693e02f358de998ae69
      https://github.com/llvm/llvm-project/commit/4e3266fb6e40dedf99e25693e02f358de998ae69
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-07-25 (Fri, 25 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    M llvm/test/CodeGen/RISCV/xandesbfhcvt.ll

  Log Message:
  -----------
  [RISCV] Implement load/store support for XAndesBFHCvt (#150350)

We use `lh` to load 2 bytes from memory into a gpr, then mask this gpr
with -65536 to emulate nan-boxing behavior, and then the value in gpr is
moved to fpr using `fmv.w.x`.
To move the value back from fpr to gpr, we use `fmv.x.w` and finally,
`sh` is used to store the lower 2 bytes back to memory.

If zfh is enabled at the same time, we can just use flh/fsw to
load/store bf16 directly.

  Commit: 7c37722f198286379abacd220162f221c49d184e
      https://github.com/llvm/llvm-project/commit/7c37722f198286379abacd220162f221c49d184e
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [IA] Recognize repeated masks which come from shuffle vectors (#150285)

This extends the fixed vector lowering to support the case where the
mask is formed via shufflevector idiom.

---------

Co-authored-by: Luke Lau <luke_lau at icloud.com>

  Commit: 4bee7e09dfabf326ead941067a9ce9975f768918
      https://github.com/llvm/llvm-project/commit/4bee7e09dfabf326ead941067a9ce9975f768918
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp

  Log Message:
  -----------
  [RISCV][IA] Rework VL for strided LD/ST optimization [nfc] (#150525)

I'd originally written this creating a new VL, but realized it was
probably cleaner to be explicit about the truncation which is happening.
As these VLs are all constants (since these two codepaths see fixed
vectors) this should result in identical constants being created.

  Commit: 4b1ca9c072cc36af77afecbc95be3c3c3e764404
      https://github.com/llvm/llvm-project/commit/4b1ca9c072cc36af77afecbc95be3c3c3e764404
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-25 (Fri, 25 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
    M llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll

  Log Message:
  -----------
  [RISCV] Remove -riscv-enable-vl-optimizer flag (#149349)

The RISCVVLOptimizer has been enabled by default for a while now and I'm
not aware of any outstanding issues that might need it to be disabled.
This removes the -riscv-enable-vl-optimizer flag to reduce the number of
configurations we have to support.

  Commit: bd91e8a5bd115be1350d4ad3a7100303511b1d15
      https://github.com/llvm/llvm-project/commit/bd91e8a5bd115be1350d4ad3a7100303511b1d15
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen] Strengthen check for what operands can be an immediate in CompressInstEmitter. (#150568)

Registers can be represented by RegisterOperand, not just RegisterClass.
Instead of trying to block certain classes, only allow Operand.

  Commit: d368d117e7ee9720acd3eac6fb41c0885575a114
      https://github.com/llvm/llvm-project/commit/d368d117e7ee9720acd3eac6fb41c0885575a114
  Author: Jacques Pienaar <jpienaar at google.com>
  Date:   2025-07-25 (Fri, 25 Jul 2025)

  Changed paths:
    A llvm/include/llvm/Support/DebugLog.h
    M llvm/unittests/Support/CMakeLists.txt
    A llvm/unittests/Support/DebugLogTest.cpp

  Log Message:
  -----------
  [llvm][support] Add LDBG macro. (#143704)

Add macro that mirror a common usage of logging to output .This makes it easy to have
streaming log like behavior while still using the base debug logging.

I also wanted to avoid inventing a full logging library here while enabling others to change the sink without too much pain, so put it in its own header (this also avoids making Debug depend on raw_ostream beyond forward reference). The should allow a consistent dev experience without fixing the sink too much.

---------

Co-authored-by: Mehdi Amini <joker.eph at gmail.com>

  Commit: 8bd6edaf9a85a4119a66d08d939a3e5f880f5d17
      https://github.com/llvm/llvm-project/commit/8bd6edaf9a85a4119a66d08d939a3e5f880f5d17
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    A llvm/include/llvm/Support/DebugLog.h
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
    M llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll
    M llvm/test/CodeGen/RISCV/xandesbfhcvt.ll
    M llvm/unittests/Support/CMakeLists.txt
    A llvm/unittests/Support/DebugLogTest.cpp
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  .

Created using spr 1.3.5-bogner

Compare: https://github.com/llvm/llvm-project/compare/ded5c472c170...8bd6edaf9a85

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications