[all-commits] [llvm/llvm-project] 4e3266: [RISCV] Implement load/store support for XAndesBFH...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e3266fb6e40dedf99e25693e02f358de998ae69
      https://github.com/llvm/llvm-project/commit/4e3266fb6e40dedf99e25693e02f358de998ae69
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-07-25 (Fri, 25 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    M llvm/test/CodeGen/RISCV/xandesbfhcvt.ll

  Log Message:
  -----------
  [RISCV] Implement load/store support for XAndesBFHCvt (#150350)

We use `lh` to load 2 bytes from memory into a gpr, then mask this gpr
with -65536 to emulate nan-boxing behavior, and then the value in gpr is
moved to fpr using `fmv.w.x`.
To move the value back from fpr to gpr, we use `fmv.x.w` and finally,
`sh` is used to store the lower 2 bytes back to memory.

If zfh is enabled at the same time, we can just use flh/fsw to
load/store bf16 directly.



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