[all-commits] [llvm/llvm-project] d3937e: [RISCV] Pass sign-extended value to isInt check in...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d3937e2d12648caa49fd80f9520a391fde2f7ba5
      https://github.com/llvm/llvm-project/commit/d3937e2d12648caa49fd80f9520a391fde2f7ba5
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-25 (Fri, 25 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/xqciac.ll

  Log Message:
  -----------
  [RISCV] Pass sign-extended value to isInt check in expandMul (#150211)

In the `isInt` check that was added in #147661 we were passing the
zero-extended `uint64_t` value instead of the sign-extended one.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications