[all-commits] [llvm/llvm-project] 17658d: [HEXAGON] Add AssertSext in sign-extended mpy (#14...

[Abinaya Saravanan via All-commits]

  Branch: refs/heads/release/21.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 17658dbedd9470886daa897808188c478243809c
      https://github.com/llvm/llvm-project/commit/17658dbedd9470886daa897808188c478243809c
  Author: Abinaya Saravanan <quic_asaravan at quicinc.com>
  Date:   2025-07-22 (Tue, 22 Jul 2025)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    A llvm/test/CodeGen/Hexagon/mpy-operand-hoist.ll

  Log Message:
  -----------
  [HEXAGON] Add AssertSext in sign-extended mpy (#149061)

The pattern i32xi32->i64, should be matched to the sign-extended
multiply op, instead of explicit sign- extension of the operands
followed by non-widening multiply (this takes 4 operations instead of
one). Currently, if one of the operands of multiply inside a loop is a
constant, the sign-extension of this constant is hoisted out of the loop
by LICM pass and this pattern is not matched by the ISEL.

This change handles multiply operand with Opcode of the type AssertSext
which is seen when the sign-extension is hoisted out-of the loop.
Modifies the DetectUseSxtw() to check for this.

(cherry picked from commit fcabb53f0c349885167ea3d0e53915e6c42271a7)



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