[all-commits] [llvm/llvm-project] cb92bc: [RISCV] Swap source register operands in QC_SHLADD...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/release/21.x
  Home:   https://github.com/llvm/llvm-project
  Commit: cb92bc511e395e6232c381441f505c85752554d4
      https://github.com/llvm/llvm-project/commit/cb92bc511e395e6232c381441f505c85752554d4
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-22 (Tue, 22 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/xqciac.ll

  Log Message:
  -----------
  [RISCV] Swap source register operands in QC_SHLADD ISEL patterns (#149697)

The instruction does `rd = (rs1 << shamt) + rs2` but the ISEL patterns
had `rs1` and `rs2` the other way around which is incorrect.

(cherry picked from commit 84e689b1db02be1687c3093d66ace913250780bd)



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