[all-commits] [llvm/llvm-project] e8a891: [AArch64][Machine-Combiner] Split gather patterns ...

Jonathan Cohen via All-commits all-commits at lists.llvm.org
Thu Jul 17 09:22:18 PDT 2025


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e8a891b0f9d2a742ac3904116aaec2c7c9231b24
      https://github.com/llvm/llvm-project/commit/e8a891b0f9d2a742ac3904116aaec2c7c9231b24
  Author: Jonathan Cohen <joncoh at apple.com>
  Date:   2025-07-17 (Thu, 17 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    A llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
    M llvm/test/CodeGen/AArch64/fsh.ll
    M llvm/test/CodeGen/AArch64/llvm.frexp.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/nontemporal.ll

  Log Message:
  -----------
  [AArch64][Machine-Combiner] Split gather patterns into neon regs to multiple vectors (#142941)

This changes optimizes gather-like sequences, where we load values
separately into lanes of a neon vector. Since each load has serial
dependency, when performing multiple i32 loads into a 128 bit vector for example, it
is more profitable to load into separate vector registers and zip them. 

rdar://151851094



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