[all-commits] [llvm/llvm-project] 0736f3: [DAG] Handle truncated splat in isBoolConstant (#1...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Jul 11 06:16:49 PDT 2025
Branch: refs/heads/users/alexey-bataev/spr/slpremove-emission-of-vector_insertvector_extract-instrinsics
Home: https://github.com/llvm/llvm-project
Commit: 0736f330b06db85cf9322296eec44e07fe604789
https://github.com/llvm/llvm-project/commit/0736f330b06db85cf9322296eec44e07fe604789
Author: David Green <david.green at arm.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-llrint.ll
M llvm/test/CodeGen/AArch64/sve-lrint.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/X86/pr78897.ll
Log Message:
-----------
[DAG] Handle truncated splat in isBoolConstant (#145473)
This allows truncated splat / buildvector in isBoolConstant, to allow
certain not instructions to be recognized post-legalization, and allow
vselect to optimize.
An override for x86 avx512 predicated vectors is required to avoid an
infinite recursion from the code that detects zero vectors. From:
```
// Check if the first operand is all zeros and Cond type is vXi1.
// If this an avx512 target we can improve the use of zero masking by
// swapping the operands and inverting the condition.
```
Commit: 0edc98cd6d310f78be14f7629d3a341551f90b36
https://github.com/llvm/llvm-project/commit/0edc98cd6d310f78be14f7629d3a341551f90b36
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
A llvm/test/CodeGen/ARM/min-max-combine.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout-unknown-lanes.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
Log Message:
-----------
[ARM] Copy SMAX(lhs, 0) and SMIN(lhs, 0) patterns from AArch64 to ARM (#146565)
They work on ARM too.
Commit: d8a2141ff98ee35cd1886f536ccc3548b012820b
https://github.com/llvm/llvm-project/commit/d8a2141ff98ee35cd1886f536ccc3548b012820b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Support/StringRef.cpp
Log Message:
-----------
[NFC][LLVM][ADT] Simplify `StringRef` case insensitive compare (#147994)
Change `ascii_strncasecmp` to use a range for loop and use StringRef
parameters.
Commit: 3d08a409593e8fc44bd2142a0aa1819cd37b6e73
https://github.com/llvm/llvm-project/commit/3d08a409593e8fc44bd2142a0aa1819cd37b6e73
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGen/bitfields_be.c
Log Message:
-----------
[CIR] Upstream new SetBitfieldOp for handling C and C++ struct bitfields (#147609)
This PR upstreams the `set_bitfield` operation used to assign values to
bitfield members in C and C++ struct types.
Handling of AAPCS-specific volatile bitfield semantics will be addressed
in a future PR.
Commit: 0c0aa56cdcf1fe3970a5f3875db412530512fc07
https://github.com/llvm/llvm-project/commit/0c0aa56cdcf1fe3970a5f3875db412530512fc07
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
R compiler-rt/lib/builtins/aarch64/emupac.cpp
M compiler-rt/lib/builtins/int_types.h
R compiler-rt/test/builtins/Unit/aarch64/emupac.c
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
M llvm/utils/gn/secondary/compiler-rt/test/builtins/BUILD.gn
Log Message:
-----------
Revert "compiler-rt: Introduce runtime functions for emulated PAC."
As well as followup "builtins: Speculative MSVC fix."
This reverts commits 5b1db59fb87b4146f827d17396f54ef30ae0dc40 and
f1c4df5b7bb79efb3e9be7fa5f8176506499d0a6.
Needs fixes for failing tests which will take time to implement.
Commit: 61004b7eb5bf63d813118753727e02be13d1e9e0
https://github.com/llvm/llvm-project/commit/61004b7eb5bf63d813118753727e02be13d1e9e0
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/lib/Dialect/GPU/CMakeLists.txt
A mlir/lib/Dialect/GPU/Transforms/XeVMAttachTarget.cpp
M mlir/test/Dialect/LLVMIR/attach-targets.mlir
M mlir/test/lib/Dialect/GPU/CMakeLists.txt
Log Message:
-----------
[MLIR][GPU] Add xevm-attach-target transform pass. (#147372)
Add xevm-attach-target transform pass and unit-tests.
Co-authored-by: by Sang Ik Lee sang.ik.lee at intel.com.
Co-authored-by: Artem Kroviakov artem.kroviakov at intel.com
Commit: 74a6e5cf91aa2c19696bf59bf0d6ecf7346e0968
https://github.com/llvm/llvm-project/commit/74a6e5cf91aa2c19696bf59bf0d6ecf7346e0968
Author: WhatAmISupposedToPutHere <css7o4rrtol2 at opayq.co>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M lld/Common/DriverDispatcher.cpp
M lld/MinGW/Driver.cpp
M lld/test/MinGW/driver.test
Log Message:
-----------
[LLD][MinGW] Support machine:arm64x when invoked in MinGW mode. (#145343)
Mingw mode already supports building machine:arm64ec arm64x binaries,
support machine:arm64x ones too.
Signed-off-by: Sasha Finkelstein <fnkl.kernel at gmail.com>
Commit: 838701a5403efbaf6e25254377a6f033acee6681
https://github.com/llvm/llvm-project/commit/838701a5403efbaf6e25254377a6f033acee6681
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
Log Message:
-----------
MemProf: Add minimum count threshold for inlining of promoted calls (#148001)
Allow users to set the minimum absolute count for inlining of indirect
calls promoted during cloning. This is primarily meant to enable
generation of synthetic vp metadata introduced in PR141164 when
profiling memprof-optimized binaries.
Commit: 88ba06d6fc36c2c817eb208d06f408afa7373be8
https://github.com/llvm/llvm-project/commit/88ba06d6fc36c2c817eb208d06f408afa7373be8
Author: Uzair Nawaz <uzairnawaz at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libc/src/__support/str_to_float.h
M libc/src/__support/str_to_integer.h
Log Message:
-----------
[libc] Addressed todo to make first_non_whitespace to return an idx instead of ptr (#148004)
Addressed todo to make first_non_whitespace to return an idx instead of
ptr
Commit: 7920dff39406c2af3859d8e316c8f098526d6af3
https://github.com/llvm/llvm-project/commit/7920dff39406c2af3859d8e316c8f098526d6af3
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPDInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
A llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd3.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd_features.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vopd.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vopd3.txt
Log Message:
-----------
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)
Commit: 3076794e924f30ae21d1a12f27b1e6349dfa5fc4
https://github.com/llvm/llvm-project/commit/3076794e924f30ae21d1a12f27b1e6349dfa5fc4
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
A clang/include/clang/Analysis/Analyses/LifetimeSafety.h
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/CMakeLists.txt
A clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
A clang/test/Sema/warn-lifetime-safety-dataflow.cpp
Log Message:
-----------
[LifetimeSafety] Introduce intra-procedural analysis in Clang (#142313)
This patch introduces the initial implementation of the
intra-procedural, flow-sensitive lifetime analysis for Clang, as
proposed in the recent RFC:
https://discourse.llvm.org/t/rfc-intra-procedural-lifetime-analysis-in-clang/86291
The primary goal of this initial submission is to establish the core
dataflow framework and gather feedback on the overall design, fact
representation, and testing strategy. The focus is on the dataflow
mechanism itself rather than exhaustively covering all C++ AST edge
cases, which will be addressed in subsequent patches.
#### Key Components
* **Conceptual Model:** Introduces the fundamental concepts of `Loan`,
`Origin`, and `Path` to model memory borrows and the lifetime of
pointers.
* **Fact Generation:** A frontend pass traverses the Clang CFG to
generate a representation of lifetime-relevant events, such as pointer
assignments, taking an address, and variables going out of scope.
* **Testing:** `llvm-lit` tests validate the analysis by checking the
generated facts.
### Next Steps
*(Not covered in this PR but planned for subsequent patches)*
The following functionality is planned for the upcoming patches to build
upon this foundation and make the analysis usable in practice:
* **Dataflow Lattice:** A dataflow lattice used to map each pointer's
symbolic `Origin` to the set of `Loans` it may contain at any given
program point.
* **Fixed-Point Analysis:** A worklist-based, flow-sensitive analysis
that propagates the lattice state across the CFG to a fixed point.
* **Placeholder Loans:** Introduce placeholder loans to represent the
lifetimes of function parameters, forming the basis for analysis
involving function calls.
* **Annotation and Opaque Call Handling:** Use placeholder loans to
correctly model **function calls**, both by respecting
`[[clang::lifetimebound]]` annotations and by conservatively handling
opaque/un-annotated functions.
* **Error Reporting:** Implement the final analysis phase that consumes
the dataflow results to generate user-facing diagnostics. This will
likely require liveness analysis to identify live origins holding
expired loans.
* **Strict vs. Permissive Modes:** Add the logic to support both
high-confidence (permissive) and more comprehensive (strict) warning
levels.
* **Expanded C++ Coverage:** Broaden support for common patterns,
including the lifetimes of temporary objects and pointers within
aggregate types (structs/containers).
* Performance benchmarking
* Capping number of iterations or number of times a CFGBlock is
processed.
---------
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: b6a4621f3b6e7c59a6c6fe8a37f161d687ea441c
https://github.com/llvm/llvm-project/commit/b6a4621f3b6e7c59a6c6fe8a37f161d687ea441c
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/utils/TableGen/SearchableTableEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Minor code cleanup in SearchableTableEmitter (#147856)
- Add braces around if/else bodies per LLVM coding standards.
- Use range for loops and structured bindings.
- use auto for variables initialized with `dyn_cast`.
- Refactor `compareBy` to also use early return in the comparison loop
by extracting the comparison into lambdas.
Commit: 78eb92b383b13c0f4e22e17a35f9eabd4832a409
https://github.com/llvm/llvm-project/commit/78eb92b383b13c0f4e22e17a35f9eabd4832a409
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
Log Message:
-----------
[gn build] Port 3076794e924f
Commit: 4859b92b7f4e0365517acd464cec29721f469461
https://github.com/llvm/llvm-project/commit/4859b92b7f4e0365517acd464cec29721f469461
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenACC/RegisterOpenACCExtensions.cpp
M flang/test/Fir/OpenACC/openacc-mappable.fir
M flang/test/Fir/OpenACC/openacc-type-categories-class.f90
M flang/test/Fir/OpenACC/openacc-type-categories.f90
M flang/test/lib/OpenACC/TestOpenACCInterfaces.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Log Message:
-----------
[flang][acc] Update FIR ref, heap, and pointer to be MappableType (#147834)
The MappableType OpenACC type interface is a richer interface that
allows OpenACC dialect to be capable to better interact with a source
dialect, FIR in this case. fir.box and fir.class types already
implemented this interface. Now the same is being done with the other
FIR types that represent variables.
One additional notable change is that fir.array no longer implements
this interface. This is because MappableType is primarily intended for
variables - and FIR variables of this type have storage associated and
thus there's a pointer-like type (fir.ref/heap/pointer) that holds the
array type.
The end goal of promoting these FIR types to MappableType is that we
will soon implement ability to generate recipes outside of the frontend
via this interface.
Commit: f28a497a06c2d9202638d753e1cd2e247814d180
https://github.com/llvm/llvm-project/commit/f28a497a06c2d9202638d753e1cd2e247814d180
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M lldb/include/lldb/Breakpoint/Breakpoint.h
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/include/lldb/Breakpoint/BreakpointOptions.h
A lldb/include/lldb/Breakpoint/StopCondition.h
M lldb/source/API/SBBreakpoint.cpp
M lldb/source/API/SBBreakpointLocation.cpp
M lldb/source/API/SBBreakpointName.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/Options.td
M lldb/source/Target/StopInfo.cpp
M lldb/test/API/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
A lldb/test/Shell/Breakpoint/condition-lang.test
Log Message:
-----------
[lldb] Support specifying a language for breakpoint conditions (#147603)
LLDB breakpoint conditions take an expression that's evaluated using the
language of the code where the breakpoint is located. Users have asked
to have an option to tell it to evaluate the expression in a specific
language.
This is feature is especially helpful for Swift, for example for a
condition based on the value in memory at an offset from a register.
Such a condition is pretty difficult to write in Swift, but easy in C.
This PR adds a new argument (-Y) to specify the language of the
condition expression. We can't reuse the current -L option, since you
might want to break on only Swift symbols, but run a C expression there
as per the example above.
rdar://146119507
Commit: 545b075a87300306658a3c0cbc224bc2e9764457
https://github.com/llvm/llvm-project/commit/545b075a87300306658a3c0cbc224bc2e9764457
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dep after 61004b7eb5bf63d813118753727e02be13d1e9e0
Commit: 14b2d2cc3a5418d88f98b2f1ec4568e69e8fdb04
https://github.com/llvm/llvm-project/commit/14b2d2cc3a5418d88f98b2f1ec4568e69e8fdb04
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
Log Message:
-----------
RuntimeLibcalls: Add entries for objc runtime calls (#147920)
Stop emitting these calls by name in PreISelIntrinsicLowering. This
is still kind of a hack. We should be going through the abstract
RTLIB:Libcall, and then checking if the call is really supported in
this module. Do this as a placeholder until RuntimeLibcalls is a
module analysis.
Commit: 76eead1bd700e165c7dcfcb6a0998d31b1782e68
https://github.com/llvm/llvm-project/commit/76eead1bd700e165c7dcfcb6a0998d31b1782e68
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
A mlir/include/mlir/Conversion/XeVMToLLVM/XeVMToLLVM.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/XeVMToLLVM/CMakeLists.txt
A mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
A mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir
Log Message:
-----------
[MLIR][Conversion] Add convert-xevm-to-llvm pass. (#147375)
Although XeVM is an LLVM extension dialect,
SPIR-V backend relies on [function
calls](https://llvm.org/docs/SPIRVUsage.html#instructions-as-function-calls)
instead of defining LLVM intrinsics to represent SPIR-V instructions.
convert-xevm-to-llvm pass lowers xevm ops to function declarations and
calls using the above naming convention.
In the future, most part of the pass should be replaced with llvmBuilder
and handled as part of translation to LLVM instead.
---------
Co-authored-by: Artem Kroviakov <artem.kroviakov at intel.com>
Commit: 78e0c767897ebb5bd8ccc87ab55a5ebd1397d77b
https://github.com/llvm/llvm-project/commit/78e0c767897ebb5bd8ccc87ab55a5ebd1397d77b
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/test/CIR/CodeGen/bitfields.c
Log Message:
-----------
[CIR][NFC] Add example for get_bitfield with volatile qualifier (#147828)
The example demonstrates how `get_bitfield` is emitted when accessing a
bitfield declared as `volatile`.
Commit: b415db02e7c2b5ae86fdae25f84e646917617818
https://github.com/llvm/llvm-project/commit/b415db02e7c2b5ae86fdae25f84e646917617818
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/test/CIR/CodeGen/enum.cpp
M clang/test/CIR/CodeGen/namespace.cpp
Log Message:
-----------
[CIR] Add handlers for 'using enum' and namespace alias (#148011)
These decl types don't require any code generation, though when debug
info is implemented, we will need to add handling for that. Until then,
we just need to have a handler so they don't generate an NYI error.
Commit: eb97422e002c0523a7f220cf2fc6c75be920dd6a
https://github.com/llvm/llvm-project/commit/eb97422e002c0523a7f220cf2fc6c75be920dd6a
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/MC/AMDGPU/gfx1250_err.s
Log Message:
-----------
[AMDGPU] Disable DPP with v_mov_b64 on gfx1250 (#148054)
Commit: da608271ae7ae7d62d82060357cb01d714ae1dbc
https://github.com/llvm/llvm-project/commit/da608271ae7ae7d62d82060357cb01d714ae1dbc
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
R mlir/include/mlir/Conversion/XeVMToLLVM/XeVMToLLVM.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/CMakeLists.txt
R mlir/lib/Conversion/XeVMToLLVM/CMakeLists.txt
R mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
R mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir
Log Message:
-----------
Revert "[MLIR][Conversion] Add convert-xevm-to-llvm pass." (#148081)
Reverts llvm/llvm-project#147375
Commit: 6fc3b40b2cfc33550dd489072c01ffab16535840
https://github.com/llvm/llvm-project/commit/6fc3b40b2cfc33550dd489072c01ffab16535840
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/abs-vector.ll
Log Message:
-----------
[msan] Model is_int_min_poison to avoid false negative in abs (#148069)
Note: since this patch reduces false negatives, buggy code that formerly
passed with MSan may start failing.
The current MSan handler for abs, like Hercules' in New York, ignores
is_int_min_poison. This patch fixes the issue by poisoning the shadow
corresponding to each int_min input value if is_int_min_poison.
Commit: c0b82df5f3484870d3728156da7d7e3720ef53ad
https://github.com/llvm/llvm-project/commit/c0b82df5f3484870d3728156da7d7e3720ef53ad
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep3.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep4.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep5.mir
Log Message:
-----------
[MachinePipeliner] Add validation for missed loop-carried memory deps (#145878)
This patch adds an additional validation step to ensure that the
generated schedule does not violate loop-carried memory dependencies.
Prior to this patch, incorrect schedules could be produced due to the
lack of checks for the following types of dependencies:
- load-to-store backward (from bottom to top within the BB) dependencies
- store-to-load dependencies
- store-to-store dependencies
One possible solution to this issue is to add these dependencies
directly to the dependency graph, although doing so may lead to
performance degradation. In addition, no known cases of incorrect code
generation caused by these missing dependencies have been observed in
practice. Given these factors, this patch introduces a post-scheduling
validation phase to check for such previously missed dependencies,
instead of adding them to the graph before searching for a schedule.
Since no actual problems have been identified so far, it is likely that
most generated schedules are already valid. Therefore, this additional
validation is not expected to cause performance degradation in practice.
Split off from #135148 .
The remaining tasks are as follows:
- Address other missing loop-carried dependencies (e.g., output
dependencies between physical registers, barrier instructions, and
instructions that may raise floating-point exceptions)
- Remove code that are currently retained to maintain the existing
behavior but probably unnecessary.
- Eliminate `SwingSchedulerDAG::isLoopCarriedDep` and use
`SwingSchedulerDDG` to traverse edges after dependency analysis part.
Commit: 7d510b7f21d1b5da2d84c8e3f7003a27b34e021d
https://github.com/llvm/llvm-project/commit/7d510b7f21d1b5da2d84c8e3f7003a27b34e021d
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
M llvm/test/Analysis/DependenceAnalysis/Coupled.ll
M llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
Log Message:
-----------
[DA] Set Distance to zero when Direction is EQ (#147966)
A Dependence object has two entries: Distance and Direction. The former
represents the distance of the dependence, while the latter
characterizes the distance by whether the value of it is positive,
negative, or zero (especially, zero is represented by EQ in DA). So it
is expected that the Distance equals zero iff the Direction is EQ.
However, this condition was not satisfied in some cases.
This patch adds a logic to set the Distance to zero if the Direction is
EQ. Although it is ideal that the Distance is updated to zero
simultaneously when the Direction is set to EQ, achieving it would
require changing the entire code in DA.
Commit: 1f990f0c2d33a1ed230306b3678d1f1d0d5db995
https://github.com/llvm/llvm-project/commit/1f990f0c2d33a1ed230306b3678d1f1d0d5db995
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_vopd.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vopd3.s
Log Message:
-----------
[AMDGPU] gfx1250 VOPD MC overflow tests. NFC. (#147826)
Commit: eba513054417bd3d7b68724fb564d3e2f4e1bd31
https://github.com/llvm/llvm-project/commit/eba513054417bd3d7b68724fb564d3e2f4e1bd31
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt
Log Message:
-----------
AMDGPU: Add MC tests for s_barrier_signal and s_get_barrier_state for gfx1250, NFC (#148070)
Commit: 34a1daae8390184a7f7072c49a5f47ce24287d59
https://github.com/llvm/llvm-project/commit/34a1daae8390184a7f7072c49a5f47ce24287d59
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaCXX/concept-crash-on-diagnostic.cpp
Log Message:
-----------
[Clang] Mark a concept as being invalid if the constraint is invalid (#147938)
Make sure to mark a concept decl as being invalid if the constraint is
invalid.
Fixes #138823
Commit: 7704f817d0a60596c4c8883c8a8ece67f0a8255a
https://github.com/llvm/llvm-project/commit/7704f817d0a60596c4c8883c8a8ece67f0a8255a
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/Format/BreakableToken.cpp
Log Message:
-----------
[clang-format][NFC] Replace a function with StringRef::contains (#146245)
Commit: cb52efb8936c0da0a03958daa95d45eaaf8806fb
https://github.com/llvm/llvm-project/commit/cb52efb8936c0da0a03958daa95d45eaaf8806fb
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Split line comments separated by backslashes (#147648)
Fixes #147341
Commit: aa4c8564c5df217bf589fed21dc009e21c3e9ca5
https://github.com/llvm/llvm-project/commit/aa4c8564c5df217bf589fed21dc009e21c3e9ca5
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/Analysis/UninitializedValues.cpp
Log Message:
-----------
[clang][NFC] Remove an unused parameter in CFGBlockValues::getValue() (#147897)
The second parameter is unused since 6080d32194.
Commit: f0befb0dcda4e908f6cd0b771753a36cc5fb980f
https://github.com/llvm/llvm-project/commit/f0befb0dcda4e908f6cd0b771753a36cc5fb980f
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/Analysis/Analyses/UninitializedValues.h
M clang/lib/Analysis/UninitializedValues.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
A clang/test/SemaCXX/uninitialized-multiple-uses.cpp
M clang/test/SemaCXX/warn-uninitialized-const-reference.cpp
Log Message:
-----------
[clang] Combine ConstRefUse with other warnings for uninitialized values (#147898)
This helps to avoid duplicating warnings in cases like:
```
> cat test.cpp
void bar(int);
void foo(const int &);
void test(bool a) {
int v = v;
if (a)
bar(v);
else
foo(v);
}
> clang++.exe test.cpp -fsyntax-only -Wuninitialized
test.cpp:4:11: warning: variable 'v' is uninitialized when used within its own initialization [-Wuninitialized]
4 | int v = v;
| ~ ^
test.cpp:4:11: warning: variable 'v' is uninitialized when used within its own initialization [-Wuninitialized]
4 | int v = v;
| ~ ^
2 warnings generated.
```
Commit: 82acb599fc0a17cd99a539709cfb6d2141f83a2d
https://github.com/llvm/llvm-project/commit/82acb599fc0a17cd99a539709cfb6d2141f83a2d
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
A llvm/include/llvm/Support/UniqueBBID.h
M llvm/lib/CodeGen/BasicBlockPathCloning.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
Log Message:
-----------
[NFC] Split UniqueBBID definition to a separate file. (#148043)
Commit: c25a5e08ba8242bd4eca387adb557ee4185a0c1e
https://github.com/llvm/llvm-project/commit/c25a5e08ba8242bd4eca387adb557ee4185a0c1e
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libc/shared/math.h
A libc/shared/math/expf16.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/expf16.h
A libc/src/__support/math/expf16_utils.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/expf16.cpp
M libc/src/math/generic/expxf16.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor expf16 implementation to header-only in src/__support/math folder. (#147428)
Part of #147386
in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: 34b55e1807d5e161a9e03366fb3d51011fedbfdd
https://github.com/llvm/llvm-project/commit/34b55e1807d5e161a9e03366fb3d51011fedbfdd
Author: hev <wangrui at loongson.cn>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
A llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
Log Message:
-----------
[LoongArch] Precommit tests for 128-to-256-bit vector insertion and 256-to-128-bit subvector extraction (NFC) (#146299)
Commit: aa9902691db5cbb9db77270902f615f3c0877deb
https://github.com/llvm/llvm-project/commit/aa9902691db5cbb9db77270902f615f3c0877deb
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang-tools-extra/clangd/ModulesBuilder.cpp
Log Message:
-----------
[NFC] [clangd] [Modules] Logging more if compilation failed
Coming from internal using experience.
The original log is just confusing... Users can't understand it unless
he reads the code.
This patch tries to make this more understandable.
Note that the mentioned module files in the logs might be removed
intentionally. We need another option to allow users to remain these
module files. Let's done this in another patch.
Commit: c919221bbe56fae15b509fcc84c25b0c041eb6b5
https://github.com/llvm/llvm-project/commit/c919221bbe56fae15b509fcc84c25b0c041eb6b5
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
Log Message:
-----------
[flang][cuda][NFC] Remove TODO implemented in semantic (#148058)
Commit: 22d584e34ecef694755a1408db11ad8486dfbb36
https://github.com/llvm/llvm-project/commit/22d584e34ecef694755a1408db11ad8486dfbb36
Author: Trevor Gross <tgross at intrepidcs.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
R llvm/test/CodeGen/X86/fp128-abi.ll
R llvm/test/CodeGen/X86/i128-abi.ll
A llvm/test/CodeGen/X86/i128-fp128-abi.ll
Log Message:
-----------
[x86] Synchronize fp128 and i128 ABI tests (nfc) (#147923)
The ABI tests for fp128 covers a handful of things that the i128 test
currently does not, including targets other than x86-64 Linux and some
simpler argument cases. Update the i128 test to be consistent with
fp128. All existing test function patterns still exist, though they all
wind up renamed.
Additionally correct some `call` signatures in the fp128 test (not
relevant for output).
Commit: f09e589ca6d8ca5666f10c07a0b347f05d90816a
https://github.com/llvm/llvm-project/commit/f09e589ca6d8ca5666f10c07a0b347f05d90816a
Author: Un1q32 <joey.t.reinhart at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86CallingConv.td
M llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
M llvm/test/CodeGen/X86/inline-asm-fpstack.ll
M llvm/test/CodeGen/X86/isel-fcmp-x87.ll
M llvm/test/CodeGen/X86/long-double-abi-align.ll
Log Message:
-----------
properly align long double on i386 darwin (#148102)
Fixes https://github.com/llvm/llvm-project/issues/148034
e49fcfc7cdf82e41f15a857083c0fb275c1b6021 broke long double stack
alignment on i386 Darwin, this PR fixes the issue.
Commit: b6b64f49c422e6d52db3bce556ae13d4d8fe2ea1
https://github.com/llvm/llvm-project/commit/b6b64f49c422e6d52db3bce556ae13d4d8fe2ea1
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M .clang-tidy
Log Message:
-----------
Format root clang-tidy config (NFC) (#147902)
Formatted config to column format, which is more readable.
Placed checks in alphabetical order.
Commit: eba35cc1c0e4e2c59f9fd1f7a6f3b17cb4d8c765
https://github.com/llvm/llvm-project/commit/eba35cc1c0e4e2c59f9fd1f7a6f3b17cb4d8c765
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/lib/Lower/Support/Utils.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/test/Fir/do_concurrent.fir
M flang/test/Fir/invalid.fir
A flang/test/Lower/do_concurrent_reduce.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops3.f90
M flang/test/Transforms/do_concurrent-to-do_loop-unodered.fir
Log Message:
-----------
[flang][do concurrent] Re-model `reduce` to match reductions are modelled in OpenMP and OpenACC (#145837)
This PR proposes re-modelling `reduce` specifiers to match OpenMP and
OpenACC. In particular, this PR includes the following:
* A new `fir` op: `fir.delcare_reduction` which is identical to OpenMP's
`omp.declare_reduction` op.
* Updating the `reduce` clause on `fir.do_concurrent.loop` to use the
new op.
* Re-uses the `ReductionProcessor` component to emit reductions for `do
concurrent` just like we do for OpenMP. To do this, the
`ReductionProcessor` had to be refactored to be more generalized.
* Upates mapping `do concurrent` to `fir.loop ... unordered` nests using
the new reduction model.
Unfortunately, this is a big PR that would be difficult to divide up in
smaller parts because the bottom of the changes are the `fir` table-gen
changes to `do concurrent`. However, doing these MLIR changes cascades
to the other parts that have to be modified to not break things.
This PR goes in the same direction we went for `private/local`
speicifiers. Now the `do concurrent` and OpenMP (and OpenACC) dialects
are modelled in essentially the same way which makes mapping between
them more trivial, hopefully.
PR stack:
- https://github.com/llvm/llvm-project/pull/145837 (this one)
- https://github.com/llvm/llvm-project/pull/146025
- https://github.com/llvm/llvm-project/pull/146028
- https://github.com/llvm/llvm-project/pull/146033
Commit: 66969c9494c39d0bd5e09a6f4aca1e9327c5b108
https://github.com/llvm/llvm-project/commit/66969c9494c39d0bd5e09a6f4aca1e9327c5b108
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/select-cond.ll
A llvm/test/CodeGen/RISCV/xqcics.ll
Log Message:
-----------
[RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675)
Add CodeGen support for conditional select instructions in this
extension
Commit: b01ef20c5b059402a68bfb8afc0a6c96e78e95c8
https://github.com/llvm/llvm-project/commit/b01ef20c5b059402a68bfb8afc0a6c96e78e95c8
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[GitHub][workflows] Use latest clang-format version 20.1.8 (#148099)
Commit: 57194ac5053628955277e87dc51c74ad982bd543
https://github.com/llvm/llvm-project/commit/57194ac5053628955277e87dc51c74ad982bd543
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
Log Message:
-----------
Mark test added in #142313 as requiring asserts since it uses `-debug-only`.
Commit: 9b81db7b32f20d27e544c53512f9c3a4bc6bf871
https://github.com/llvm/llvm-project/commit/9b81db7b32f20d27e544c53512f9c3a4bc6bf871
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
Log Message:
-----------
[RISCV] Use source element type for the zero constant in IR for vwcvt intrinsic. (#148023)
The vwcvt intrinsic produces a vwadd with a scalar 0 for the RHS. We
should be using the element type of the source so that the 0 needs to be
widened.
The i32->i64 vwcvt previously failed on RV32 because the legalization
code doesn't expect to see an i64 type.
Commit: f9292c25cf29e789d58ccd91fb29428abfc7d8fa
https://github.com/llvm/llvm-project/commit/f9292c25cf29e789d58ccd91fb29428abfc7d8fa
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
A clang/test/CodeGen/PowerPC/check-zero-vector.c
A llvm/test/CodeGen/PowerPC/check-zero-vector.ll
Log Message:
-----------
[NFC][PowerPC] Add test case for lockdown of vector compare greater than support for Zero vector comparisons (#147246)
NFC patch to add testcase for locking down the support of Zero vector
comparisons using the `vcmpgtuh (vector compare greater than unsigned
halfword)` instruction.
Currently `vcmpequh (vector compare equal unsigned halfword)` is in use.
---------
Co-authored-by: himadhith <himadhith.v at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>
Commit: 7c8a197918a0c4044c1be39a26d517eea95a5ec9
https://github.com/llvm/llvm-project/commit/7c8a197918a0c4044c1be39a26d517eea95a5ec9
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
A flang/include/flang/Lower/OpenMP/Clauses.h
A flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/ClauseFinder.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
R flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/Decomposer.cpp
M flang/lib/Lower/OpenMP/Decomposer.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/lib/Lower/OpenMP/ReductionProcessor.cpp
R flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/lib/Lower/Support/ReductionProcessor.cpp
Log Message:
-----------
[NFC][flang] Move `ReductionProcessor` to `Lower/Support`. (#146025)
With #145837, the `ReductionProcessor` component is now used by both
OpenMP and `do concurrent`. Therefore, this PR moves it to a shared
location: `flang/Lower/Support`.
PR stack:
- https://github.com/llvm/llvm-project/pull/145837
- https://github.com/llvm/llvm-project/pull/146025 (this one)
- https://github.com/llvm/llvm-project/pull/146028
- https://github.com/llvm/llvm-project/pull/146033
Commit: 799270a807a6fec265388bd0efbac31f46b49a29
https://github.com/llvm/llvm-project/commit/799270a807a6fec265388bd0efbac31f46b49a29
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
Log Message:
-----------
[RISCV] Add missing indexed load/store intrinsic tests for zvfbfmin (#148097)
https://github.com/riscv-non-isa/rvv-intrinsic-doc/commit/d6d33a0e60fd234f26b79e4fcb00e6ace0b64b4c
adds missing indexed load/store which with other index size.
Commit: e0eb8f0ef3ef908770900a082441588a43cc460f
https://github.com/llvm/llvm-project/commit/e0eb8f0ef3ef908770900a082441588a43cc460f
Author: offsetof <offsetof at mailo.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaCast.cpp
M clang/test/CXX/expr/expr.post/expr.static.cast/p3-0x.cpp
Log Message:
-----------
[clang] Fix static_cast bypassing access control (#132285)
Fix access and ambiguity checks not being performed when converting to
an rvalue reference to a base class type with `static_cast`.
Fixes #121429
---------
Co-authored-by: Corentin Jabot <corentinjabot at gmail.com>
Commit: 17784e8d2973494c295156ecf3a23253e3401c72
https://github.com/llvm/llvm-project/commit/17784e8d2973494c295156ecf3a23253e3401c72
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/include/llvm/Support/Endian.h
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/unittests/Support/EndianTest.cpp
Log Message:
-----------
[support] Add packed_endian_specific_integral::value() (#147974)
They are already implicitly convertible to the underlying type, but that
doesn't work in some contexts, and it can be useful to get the
underlying value without needing the remember/guess the right type.
I converted a couple of call sites to demonstrate usefulness, but
there's likely more of them. I know at least of at least a few in LLDB,
but I don't want to make this a cross-project patch.
Commit: a510e75949a4efa4305ba4c6276c9098693d465e
https://github.com/llvm/llvm-project/commit/a510e75949a4efa4305ba4c6276c9098693d465e
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
Log Message:
-----------
[flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion (#146028)
Re-organizes the op definition a little bit and removes a method that
does not add much value to the API.
PR stack:
- https://github.com/llvm/llvm-project/pull/145837
- https://github.com/llvm/llvm-project/pull/146025
- https://github.com/llvm/llvm-project/pull/146028 (this one)
- https://github.com/llvm/llvm-project/pull/146033
Commit: eb0d61af6e5ede942365c0e4760a75e0e725d388
https://github.com/llvm/llvm-project/commit/eb0d61af6e5ede942365c0e4760a75e0e725d388
Author: hev <wangrui at loongson.cn>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
M llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
M llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
Log Message:
-----------
[LoongArch] Optimize 128-to-256-bit vector insertion and 256-to-128-bit subvector extraction (#146300)
This patch replaces stack-based accesses with register moves when
converting between 128-bit and 256-bit vectors. A 128-bit subvector
extract from, or insert to, the lower half of a 256-bit vector is now
treated as a subregister copy that needs no instruction.
Fixes #147769
Commit: 2ae76d55550781326f3d1b2996143d880304353c
https://github.com/llvm/llvm-project/commit/2ae76d55550781326f3d1b2996143d880304353c
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/MC/AMDGPU/gfx9_asm_vop2_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_features.txt
Log Message:
-----------
[AMDGPU] Use different values for SISrcMods::NEG and SISrcMods::SEXT (#147964)
The SISrcMods::NEG and SISrcMods::SEXT enumerators share the same enum
value. At the time when they were introduced, it was assumed that the
"floating point" "neg"/"abs" and the "integer" "sext" source modifiers
are mutually exclusive. This can lead to miscompilation as a "sext"
modifier may right now be accepted erroneously on some instructions
which are encoded as floating point instructions (see the test case
modified by this PR). The encoding will then use the "neg" modifier.
Furthermore, the "neg"/"abs" and the "sext" modifiers are not
necessarily mutually exclusive, i.e. the hardware may support both. This
cannot be handled correctly with the current representation.
This patch changes the SISrcMods enum to use different values for NEG
and SEXT. This is meant as a first step to allow their coexistence on
the same instruction.
Commit: a516c60ec34682db0d35a20fe3e299a9ae17a356
https://github.com/llvm/llvm-project/commit/a516c60ec34682db0d35a20fe3e299a9ae17a356
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
Log Message:
-----------
[NFC] Correct typo: invertion -> inversion (#147995)
Commit: 9de657abaf3d60918cb10edbbada3c4b520b0b0c
https://github.com/llvm/llvm-project/commit/9de657abaf3d60918cb10edbbada3c4b520b0b0c
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqciac.ll
Log Message:
-----------
[RISCV] Add ISel patterns for Xqciac QC.MULIADD instruction (#147661)
Add basic isel patterns for the multiple accumulate QC.MULIADD
instruction.
While most case work with just the TD file pattern, there are few cases
which need to be handled in ISelLowering depending on the immediate we
are multiplying with:
- imm + 1 , imm - 1, 1 - imm, -1 - imm are a power of 2 --> these become
slli and add/sub
- immediate is 2^n - 2 ^m --> this becomes (add/sub (shl X, C1), (shl X,
C2))
- imm - 2, imm - 4, imm - 6 is a power of 2 --> these use shxadd when
zba is enabled
The patch does not decompose mul if Xqciac is present, for the above
conditions. There could be cases where this may not beneficial which I
plan to address in follow up patches.
Commit: a84ae9c2dd1fbec20d00896fdd879f57c7c49245
https://github.com/llvm/llvm-project/commit/a84ae9c2dd1fbec20d00896fdd879f57c7c49245
Author: David Green <david.green at arm.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/machine-combiner-maddimm.mir
M llvm/test/CodeGen/AArch64/madd-combiner.ll
Log Message:
-----------
[AArch64] Use mov imm pseudo instructions in madd combine. (#147510)
The usual path for lowering immediates in AArch64 is to generate a
MOVi32imm or MOVi64imm pseudo instruction, that can be moved /
rematerialized around as required, being expanded into one or multiple
instructions after register allocation.
The code for the MachineCombiner was generating MOVN/ORR/MOVZ directly.
This converts them to use the pseudos, allowing the generated immediates
to be materialized if required. The code is hopefully simpler as a
result, and the Sub and Add patterns have been combined to reduce
duplication.
Commit: c3ec38dc7c47525f8c7591ddec7e74d8dfb19c28
https://github.com/llvm/llvm-project/commit/c3ec38dc7c47525f8c7591ddec7e74d8dfb19c28
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
Log Message:
-----------
[NVPTX][NFC] Move more TMA intrinsics lowering to tablegen (#147576)
This patch moves the lowering of the TMA Tensor prefetch
and S2G-copy intrinsics to tablegen itself. This is in preparation
for adding Blackwell-specific additions to these intrinsic.
The TMA reduction intrinsics lowering is kept intact (C++), and
hence the macro names are updated to reflect the current usage.
The existing tests have full coverage and continue to pass as expected.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: edd615eef216d2ef9a39c7d9ffd8b8c79852f091
https://github.com/llvm/llvm-project/commit/edd615eef216d2ef9a39c7d9ffd8b8c79852f091
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNProcessors.td
Log Message:
-----------
AMDGPU: Remove "gws" feature from generic targets (#148122)
Here "generic targets" means when no target is specified. This is
because gfx12+ does not support this feature, and thus it is no longer
universally available.
Fixes: SWDEV-541399
Commit: d679b9a8226fdb1204f8022b78b761fde44fea0b
https://github.com/llvm/llvm-project/commit/d679b9a8226fdb1204f8022b78b761fde44fea0b
Author: yronglin <yronglin777 at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/test/CXX/basic/basic.link/p3.cpp
Log Message:
-----------
[NFC][C++][Modules] Refine test/CXX/basic.link/p3.cpp with split-file (#147945)
Refine basic.link.p3 tests with split-file.
---------
Signed-off-by: Wang, Yihan <yronglin777 at gmail.com>
Commit: 0e9b7b054cee679d1a509574f1e88d99accd8cb7
https://github.com/llvm/llvm-project/commit/0e9b7b054cee679d1a509574f1e88d99accd8cb7
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
A flang/test/Transforms/DoConcurrent/reduce_add.mlir
A flang/test/Transforms/DoConcurrent/reduce_all_regions.mlir
A flang/test/Transforms/DoConcurrent/reduce_local.mlir
Log Message:
-----------
[flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (#146033)
Now that we have changes introduced by #145837, mapping reductions from
`do concurrent` to OpenMP is almost trivial. This PR adds such mapping.
PR stack:
- https://github.com/llvm/llvm-project/pull/145837
- https://github.com/llvm/llvm-project/pull/146025
- https://github.com/llvm/llvm-project/pull/146028
- https://github.com/llvm/llvm-project/pull/146033 (this one)
Commit: a9102f564071c6825226903f346209a85aacb2bd
https://github.com/llvm/llvm-project/commit/a9102f564071c6825226903f346209a85aacb2bd
Author: Christian Sigg <csigg at google.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/python/mlir/dialects/TransformTuneExtensionOps.td
Log Message:
-----------
[mlir] Fix TransformTuneExtensionOps.td include guards
Commit: 0e5f9f67cd990e55aaa64472c5fcc2117ac7ae33
https://github.com/llvm/llvm-project/commit/0e5f9f67cd990e55aaa64472c5fcc2117ac7ae33
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpState.h
Log Message:
-----------
[clang][bytecode] Keep a list of initializing blocks in InterpState (#148120)
So we can know what blocks we're currently running constructors or
destructors for.
Commit: ab1c4905f4dc3bdeb05bff1f3de24f73d6d612e4
https://github.com/llvm/llvm-project/commit/ab1c4905f4dc3bdeb05bff1f3de24f73d6d612e4
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
A flang/test/HLFIR/fir-reduction-alloca-block.fir
A flang/test/Lower/do_concurrent_reduce_allocatable.f90
Log Message:
-----------
[flang][do concurrent] Extned `getAllocaBlock()` and emit yields correctly (#146853)
Handles some loose ends in `do concurrent` reduction declarations. This
PR extends `getAllocaBlock` to handle declare ops, and also emit
`fir.yield` in all regions.
Commit: 1f39b92a161af06dad589044c22137c28a4b49e8
https://github.com/llvm/llvm-project/commit/1f39b92a161af06dad589044c22137c28a4b49e8
Author: pkarveti <quic_pkarveti at quicinc.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
A llvm/test/CodeGen/Hexagon/bitcast-i32-to-v32i1.ll
A llvm/test/CodeGen/Hexagon/bitcast-v2i16-to-v32i1.ll
A llvm/test/CodeGen/Hexagon/bitcast-v4i8-to-v32i1.ll
Log Message:
-----------
[Hexagon] Handle bitcast of i32/v2i16/v4i8 -> v32i1 when Hvx is enabled (#147466)
Commit: d679dc78229ccc9060374b58c1fa911e2c4a1335
https://github.com/llvm/llvm-project/commit/d679dc78229ccc9060374b58c1fa911e2c4a1335
Author: pkarveti <quic_pkarveti at quicinc.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll
Log Message:
-----------
[Hexagon]Handle truncate of v4i8/v2i16 -> v4i1/v2i1 when Hvx is enabled (#147476)
Commit: e908f6131e70394023fd6c5fab7fb10c16c184ed
https://github.com/llvm/llvm-project/commit/e908f6131e70394023fd6c5fab7fb10c16c184ed
Author: William Huynh <William.Huynh at arm.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M libc/include/llvm-libc-macros/wchar-macros.h
M libc/test/src/math/smoke/RoundToIntegerTest.h
Log Message:
-----------
[libc] Fix WEOF and fix 1'000'000 error messages on test failure (#147928)
1. WEOF is defined as a `wint_t` by the C standard. On certain
architectures, the test won't compile on `-Wall`. This fixes it.
2. If `testSubnormalRange` fails, it will spit out way too many error
messages, which overwhelms my test environment. I reduce this to 1k for
now.
This is required for #145349
Commit: f1cee58789ef49cf0a7cc081e539190edf15b92a
https://github.com/llvm/llvm-project/commit/f1cee58789ef49cf0a7cc081e539190edf15b92a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/iterator/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/iterator/TestDataFormatterStdIterator.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/iterator/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/iterator/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/iterator/TestDataFormatterLibccIterator.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/iterator/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/iterator/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/iterator/TestDataFormatterStdIterator.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/iterator/main.cpp
Log Message:
-----------
[lldb][test] Combine libstdc++ and libc++ iterator tests into generic test (#147175)
This combines the libc++ and libstdc++ test cases. The libstdcpp tests
were a subset of the libc++ test, so this patch moves the libcxx test
into generic and removes the libstdcpp test entirely.
There are currently no formatters for libstdcpp
std::unorderd_map::iterator. So I removed those test-cases. We already
test them for libc++ in `libcxx/unordered_map-iterator`. And we test
`std::unordered_map` in `generic/unorderd`. So these test-cases would be
redundant.
Split out from https://github.com/llvm/llvm-project/pull/146740
Commit: b8d21bf63bbc140a58ae708d981c20723af28f2f
https://github.com/llvm/llvm-project/commit/b8d21bf63bbc140a58ae708d981c20723af28f2f
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/config.bzl
Log Message:
-----------
[bazel] Turn on EXPERIMENTAL_KEY_INSTRUCTIONS
It has been introduced in #131344 and turned on at #144324
Commit: def7bbbe17c6d0302a0cccf67355e36c45fcb224
https://github.com/llvm/llvm-project/commit/def7bbbe17c6d0302a0cccf67355e36c45fcb224
Author: nerix <nerixdev at outlook.de>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CMakeLists.txt
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/Generic.cpp
M lldb/source/Plugins/Language/CPlusPlus/MsvcStl.h
A lldb/source/Plugins/Language/CPlusPlus/MsvcStlSmartPointer.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/shared_ptr/TestDataFormatterStdSharedPtr.py
Log Message:
-----------
[LLDB] Add formatters for MSVC STL std::shared_ptr (#147575)
This PR adds formatters for `std::shared_ptr` and `std::weak_ptr`. They
are similar to the ones from libc++ and libstdc++.
[Section from MSVC STL
NatVis](https://github.com/microsoft/STL/blob/313964b78a8fd5a52e7965e13781f735bcce13c5/stl/debugger/STL.natvis#L512-L578).
To support debugging with PDB debug info, I had to add an early exit in
`GetDesugaredSmartPointerValue`, because with PDB, LLDB doesn't know
about template types. This isn't an issue here, since the typedef type
is already resolved there, so no casting is needed.
The tests don't check for PDB - maybe this should be changed? I don't
know a good way to do this. PDB has the downside that it resolves
typedefs. Here in particular, the test for `element_type` would need to
be replaced with `User` and `std::string` with
`std::basic_string<char,std::char_traits<char>,std::allocator<char> >`.
Towards #24834.
Commit: 6bed7b7947ad1b21214cf06bc335d0ec23e4627b
https://github.com/llvm/llvm-project/commit/6bed7b7947ad1b21214cf06bc335d0ec23e4627b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
Log Message:
-----------
[gn build] Port def7bbbe17c6
Commit: 74e3dfe389fda89b584f6e1f4b00700f54b1b1ac
https://github.com/llvm/llvm-project/commit/74e3dfe389fda89b584f6e1f4b00700f54b1b1ac
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
Log Message:
-----------
[LV] Disable forcing interleaving for uncountable early exit loops (#147993)
Interleaving does not currently work properly when vectorising loops
with uncountable early exits. Interleaving is already disabled for
normal vectorisation and for the pragma/hint - this patch also disables
it when using -force-vector-interleave.
Commit: 7b91df386820aaf84b30c09d48fba110a42bdc56
https://github.com/llvm/llvm-project/commit/7b91df386820aaf84b30c09d48fba110a42bdc56
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
A mlir/test/Target/LLVMIR/omptarget-debug-reduc-fn-loc.mlir
Log Message:
-----------
[OMPIRBuilder] Don't use invalid debug loc in reduction functions. (#147950)
We have this pattern of code in OMPIRBuilder for many functions that are
used in reduction operations.
```
Function *LtGRFunc = Function::Create
BasicBlock *EntryBlock = BasicBlock::Create(Ctx, "entry", LtGRFunc);
Builder.SetInsertPoint(EntryBlock);
```
The insertion point is moved to the new function but the debug location is not updated. This means that reduction function will use the debug location that points to another function. This problem gets hidden because these functions gets inlined but the potential for failure exists.
This patch resets the debug location when insertion point is moved to new function. Some `InsertPointGuard` have been added to make sure why restore the debug location correctly when we are done with the reduction function.
Commit: c0422733e3b78ae29cc41b729a2a4adafc0c63bc
https://github.com/llvm/llvm-project/commit/c0422733e3b78ae29cc41b729a2a4adafc0c63bc
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/SemaCXX/cxx1z-constexpr-lambdas.cpp
Log Message:
-----------
[clang][bytecode] Check lambda captures before binding decls (#148130)
If the given decls is a lambda capture (but also a BindingDecl), handle
it as a lambda capture instead of a BindingDecl.
Commit: 9544bb5c299c36d1f31cddbb5350eda6f53b6e2b
https://github.com/llvm/llvm-project/commit/9544bb5c299c36d1f31cddbb5350eda6f53b6e2b
Author: Marius Kamp <msk at posteo.org>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
A llvm/test/Transforms/InstCombine/icmp_or_umul_overflow.ll
Log Message:
-----------
[InstCombine] Fold umul.overflow(x, c1) | (x*c1 > c2) to x > c2/c1 (#147327)
The motivation of this pattern is to check whether the product of a
variable and a constant would be mathematically (i.e., as integer
numbers instead of bit vectors) greater than a given constant bound. The
pattern appears to occur when compiling several Rust projects (it seems
to originate from the `smallvec` crate but I have not checked this
further).
Unless `c1` is `0`, we can transform this pattern into `x > c2/c1` with
all operations working on unsigned integers. Due to undefined behavior
when an element of a non-splat vector is `0`, the transform is only
implemented for scalars and splat vectors.
Alive proof: https://alive2.llvm.org/ce/z/LawTkm
Closes #142674
Commit: e608e3f023603c3687ed2da6f2e6408668ab28e6
https://github.com/llvm/llvm-project/commit/e608e3f023603c3687ed2da6f2e6408668ab28e6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Log Message:
-----------
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.
Commit: 44481f506770ed41e49d0f336eb569bacec0d32a
https://github.com/llvm/llvm-project/commit/44481f506770ed41e49d0f336eb569bacec0d32a
Author: jjasmine <jjasmine at igalia.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll
M llvm/test/CodeGen/WebAssembly/simd-select.ll
Log Message:
-----------
[DAGCombine] Change isBuildVectorAll* -> isConstantSplatVectorAll* for Vselect (#147305)
Change isBuildVectorAll* -> isConstantSplatVectorAll* in VSelect in case
the fold happens after BuildVector has been canonically transformed to
Splat or if the Splat is initially in vselect already
- Fixes #73454
- Update related test cases, add extra tests in wasm
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: 1ace9fa60b668f5a6d0bf4768ff8b4c0dd62f0dd
https://github.com/llvm/llvm-project/commit/1ace9fa60b668f5a6d0bf4768ff8b4c0dd62f0dd
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Enable Bfloat fma contraction. (#147941)
Commit: 77861b3a8f26bb31446db79979a92aeee86ed20f
https://github.com/llvm/llvm-project/commit/77861b3a8f26bb31446db79979a92aeee86ed20f
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/parallel_ast_print.cpp
A clang/test/OpenMP/parallel_message_messages.cpp
A clang/test/OpenMP/parallel_severity_messages.cpp
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[OpenMP][clang] 6.0: parsing/sema for message/severity for parallel (#146093)
Implement parsing and semantic analysis support for the message and
severity clauses that have been added to the parallel directive in
OpenMP 6.0, 12.1.
Commit: 82a276e6100c29a660bf5e5a19ee14e8d486e5fa
https://github.com/llvm/llvm-project/commit/82a276e6100c29a660bf5e5a19ee14e8d486e5fa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
Log Message:
-----------
[ARM][WebAssembly] Remove unused PatternMatch namespace. NFC. (#147984)
Avoid file-level "using namespace llvm::PatternMatch" to make it easier to potentially use SDPatternMatch in the future.
Commit: 7eb14d9dd19524719c831ecf75d5a8df735db49d
https://github.com/llvm/llvm-project/commit/7eb14d9dd19524719c831ecf75d5a8df735db49d
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[TTI] Fix value-based BasicTTIImpl vp.{gather,scatter} costing (#148020)
After #147677 we now preserve value based costing for vp intrinsics
instead of switching it to type based costing.
However for vp.gather and vp.scatter, even though they fallback to their
functionally equivalent masked.gather and masked.scatter, the number of
arguments are different due to the alignment being a dedicated argument.
This caused a crash detected at
https://lab.llvm.org/staging/#/builders/210/builds/988
Thix fixes it by explicitly handling the two intrinsics and adding test
coverage.
Note that the type based costing isn't yet implemented for
masked.gather/masked.scatter so it doesn't show up correctly.
Commit: 9a805ba16993e3cea7a341a2626ee260d92399ca
https://github.com/llvm/llvm-project/commit/9a805ba16993e3cea7a341a2626ee260d92399ca
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
Log Message:
-----------
[flang][NFC] Fix deprecation warning (#147932)
I started getting deprecation warnings from operations constructors
which seem to be doing implicit construction of mlir::ValueRange from a
std::nullopt by relying on implicit conversion from std::nullopt into
llvm::ArrayRef. ArrayRef{std::nullopt} is what has been deprecated.
Commit: aee21c368b41cd5f7765a31b9dbe77f2bffadd4e
https://github.com/llvm/llvm-project/commit/aee21c368b41cd5f7765a31b9dbe77f2bffadd4e
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
Log Message:
-----------
[RISCV] AddEdge between mask producer and user of V0 (#146855)
If there are multiple masks producers followed by multiple
masked consumers, may a move(vmv* v0, vx) will be generated
to save mask.
By moving the mask's producer after the mask's use,
the spill can be eliminated, and the move can be removed.
Commit: 5cd56c9216b2c524423a5d913fc8458d28e25d1a
https://github.com/llvm/llvm-project/commit/5cd56c9216b2c524423a5d913fc8458d28e25d1a
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
A mlir/test/Dialect/LLVMIR/cse-nvvm.mlir
Log Message:
-----------
[MLIR][NVVM] Remove Pure trait from clock, clock64, globaltimer Ops (#147608)
This commit removes Pure trait from clock, clock64 and globaltimer Ops by creating NVVM_NCSpecialRegisterOp class to represent Ops which return non-constant values. This prevents CSE pass from optimizing awayredundant uses of them
Commit: 8472eb1361bbabd6428a65da446618503e439743
https://github.com/llvm/llvm-project/commit/8472eb1361bbabd6428a65da446618503e439743
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/test/CodeGen/AArch64/ldst_update_cfpath.mir
M llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
Log Message:
-----------
[AArch64LoadStoreOpt] BaseReg update is searched also in CF successor (#145583)
Look for reg update instruction (to merge w/ mem instruction into
pre/post-increment form) not only inside a single MBB but also along a
CF path going downward w/o side enters such that BaseReg is alive along
it but not at its exits.
Regression test is updated accordingly.
Commit: 9098bffb0370273e67c76ab996eb4559dcc71f34
https://github.com/llvm/llvm-project/commit/9098bffb0370273e67c76ab996eb4559dcc71f34
Author: Druzhkov Sergei <serzhdruzhok at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
A lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
R lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_runInTerminal.py
M lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/README.md
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Add external terminal support (#146950)
This patch deprecates the `runInTerminal` option in favour of `console`
which allow the user the specify an integrated or external option.
Commit: 95134a680ed119f31dd7a99df9a9632903f6780b
https://github.com/llvm/llvm-project/commit/95134a680ed119f31dd7a99df9a9632903f6780b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
Log Message:
-----------
[AMDGPU] merge-stores.ll - regenerate test checks
Commit: 2110a77cd03c83bf3616c421e2ee0c7a6e0f3031
https://github.com/llvm/llvm-project/commit/2110a77cd03c83bf3616c421e2ee0c7a6e0f3031
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
Log Message:
-----------
[AMDGPU] fmuladd.f64.ll - regenerate test checks
Commit: 5fd319f5cc9b2439a3731c9e08c60bbf69b2ecc7
https://github.com/llvm/llvm-project/commit/5fd319f5cc9b2439a3731c9e08c60bbf69b2ecc7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
Log Message:
-----------
[AMDGPU] load-local-i16.ll - regenerate test checks
Commit: fa921d166a77afbf0e1c4b2e0b4c0020da21594c
https://github.com/llvm/llvm-project/commit/fa921d166a77afbf0e1c4b2e0b4c0020da21594c
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Clang][Doc] Add Changelog line for (#144886) (#147978)
The patch [CUDA][HIP] Add a __device__ version of
std::__glibcxx_assert_fail() (#144886) missed a changelog line.
Commit: 4a35214bddbb67f9597a500d48ab8c4fb25af150
https://github.com/llvm/llvm-project/commit/4a35214bddbb67f9597a500d48ab8c4fb25af150
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M mlir/test/mlir-tblgen/attrdefs.td
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
Log Message:
-----------
[mlir][ODS] Fix TableGen for AttrOrTypeDef::hasStorageCustomConstructor (#147957)
There is a `hasStorageCustomConstructor` flag that allows one to provide
custom attribute/type construction implementation. Unfortunately, it
seems like the flag does not work properly: the generated C++ produces
*empty body* method instead of producing only a declaration.
Commit: a61ea9fd9b9c100ce4fce9212dc85230257fd5c8
https://github.com/llvm/llvm-project/commit/a61ea9fd9b9c100ce4fce9212dc85230257fd5c8
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/readability/NamedParameterCheck.cpp
M clang-tools-extra/clang-tidy/readability/NamedParameterCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/named-parameter.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/named-parameter.cpp
Log Message:
-----------
[clang-tidy] Add an option in 'readability-named-parameter' to print names without comment (#147953)
Add InsertPlainNamesInForwardDecls option to readability-named-parameter
check to insert parameter names without comments for forward
declarations only.
When enabled, forward declarations get plain parameter names (e.g., `int
param`) while function definitions continue to use commented names
(e.g., `int /*param*/`). Named parameters in forward decls don't cause
compiler warnings and some developers prefer to have names without
comments but in sync between declarations and the definition.
Default behavior remains unchanged
(InsertPlainNamesInForwardDecls=false).
Example with InsertPlainNamesInForwardDecls=true:
```cpp
// Forward declaration - gets plain name because the definition has name.
void func(int param);
void func(int param) { ... = param; }
```
Commit: 96bc07d49221dc40eb751e0759be2ccbb8a64f00
https://github.com/llvm/llvm-project/commit/96bc07d49221dc40eb751e0759be2ccbb8a64f00
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-cli-canonical_loop.mlir
A mlir/test/Target/LLVMIR/openmp-cli-unroll-heuristic01.mlir
A mlir/test/Target/LLVMIR/openmp-cli-unroll-heuristic02.mlir
Log Message:
-----------
[MLIR][OpenMP] Add canonical loop LLVM-IR lowering (#147069)
Support for translating the operations introduced in #144785 to LLVM-IR.
In order to keep the lowering simple,
`OpenMPIRBuider::unrollLoopHeuristic` is applied when encountering the
`omp.unroll_heuristic` op. As a result, the operation that unrolling is
applied to (`omp.canonical_loop`) must have been emitted before even
though logically there is no such requirement.
Eventually, all transformations on a loop must be applied directly after
emitting `omp.canonical_loop`, i.e. future transformations must be
looked-up when encountering `omp.canonical_loop` itself. This is because
many OpenMPIRBuilder methods (e.g. `createParallel`) expect all the
region code to be emitted withing a callback. In the case of
`createParallel`, the region code is getting outlined into a new
function. Therefore, making the operation order a formal requirement
would not make the implementation any easier.
Commit: a60405c2d51ffe428dd38b8b1020c19189968f76
https://github.com/llvm/llvm-project/commit/a60405c2d51ffe428dd38b8b1020c19189968f76
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll
Log Message:
-----------
[LSR] Regenerate test checks (NFC)
Commit: 6630cde4e644f3b4147b984f9832c89fb3306698
https://github.com/llvm/llvm-project/commit/6630cde4e644f3b4147b984f9832c89fb3306698
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/docs/ReleaseNotes.md
Log Message:
-----------
[flang][docs] Update release notes for OpenMP (#147988)
Co-authored-by: Kiran Chandramohan <kiranchandramohan at gmail.com>
Commit: 587ba75a491d256500e4125c7c1de725c93fa84e
https://github.com/llvm/llvm-project/commit/587ba75a491d256500e4125c7c1de725c93fa84e
Author: arun-thmn <arun.thangamani at intel.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
Log Message:
-----------
[mlir][x86vector] AVX2 I8 Dot Op (#147908)
Adds AVX2 i8 dot-product operation and defines lowering to LLVM
intrinsics.
Target assembly instruction: `vpdpbssd.128/256`
Commit: a2246eebcae47c5cb92c524ee96191edb358922d
https://github.com/llvm/llvm-project/commit/a2246eebcae47c5cb92c524ee96191edb358922d
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/C/C23/n3030.c
A clang/test/C/C23/n3030_1.c
M clang/test/CXX/dcl.dcl/dcl.enum/p2.cpp
A clang/test/CodeGen/enum3.c
M clang/test/SemaCXX/enum-scoped.cpp
Log Message:
-----------
[C23] Accept an _Atomic underlying type (#147802)
The underlying type of an enumeration is the non-atomic, unqualified
version of the specified type. Clang was rejecting such enumerations,
with a hard error, but now has the ability to downgrade the error into a
warning. Additionally, we diagnose (as a warning) dropping other
qualifiers. _Atomic is special given that an atomic type need not have
the same size as its non-atomic counterpart, and that the C++ version
of <stdatomic.h> defines _Atomic to std::atomic for easing cross-
language atomic use and std::atomic is an invalid enum base in C++.
(Note: we expose _Atomic in C++ even without including
<stdatomic,h>.)
Fixes #147736
Commit: 567d164e5965da22f47099d23aeb544493e84871
https://github.com/llvm/llvm-project/commit/567d164e5965da22f47099d23aeb544493e84871
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
Log Message:
-----------
[MLIR] Fix build break in X86VectorDialect.cpp
mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp:109:10: error: could not convert ‘intrinsicOprnds’ from ‘SmallVector<[...],3>’ to
‘SmallVector<[...],6>’ 109 | return intrinsicOprnds;
| ^~~~~~~~~~~~~~~
| | | SmallVector<[...],3>
Commit: ea65415f310732da7cdfbb2e7c6c6c48ed08a54c
https://github.com/llvm/llvm-project/commit/ea65415f310732da7cdfbb2e7c6c6c48ed08a54c
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
Log Message:
-----------
Remove some FIXMEs that no longer apply; NFC
Noticed these while doing a review on changes in the area, but C23
added support for nodiscard with a message, so it's not an extension
we need to diagnose.
Commit: c040172b9ada96d025f52c3ce49d34cad075091b
https://github.com/llvm/llvm-project/commit/c040172b9ada96d025f52c3ce49d34cad075091b
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/include/mlir/TableGen/Class.h
M mlir/lib/TableGen/Class.cpp
Log Message:
-----------
[mlir][TableGen] Verify compatibility of tblgen::Method properties (#147979)
Following a recent discovery of a method being defined both "inline" and
"declaration" (declaration implying no definition), verify the method
properties in general to fail early in the development and avoid
accidental bugs (especially for "opt-in" features).
Commit: 638943b27e172fdd6e86b44c83451fa7300c172b
https://github.com/llvm/llvm-project/commit/638943b27e172fdd6e86b44c83451fa7300c172b
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/openmp-utils.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/allocators-unparse.f90
A flang/test/Semantics/OpenMP/allocators07.f90
Log Message:
-----------
[flang][OpenMP] Convert AST node for ALLOCATORS to use Block as body (#148005)
The ALLOCATORS construct is one of the few constructs that require a
special form of the associated block.
Convert the AST node to use OmpDirectiveSpecification for the directive
and the optional end directive, and to use parser::Block as the body:
the form of the block is checked in the semantic checks (with a more
meaningful message).
Commit: 3231cb4b19ebc03cc288767a018fe8312328ca0a
https://github.com/llvm/llvm-project/commit/3231cb4b19ebc03cc288767a018fe8312328ca0a
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
A clang/test/Sema/constant-builtins-vector.cpp
R clang/test/Sema/constant_builtins_vector.cpp
Log Message:
-----------
[clang] Fix copy/paste error in vector `__builtin_elementwise_{add,sub}_sat` implementation. (#147973)
Closes #147891.
Commit: b293c8bfb6dd658c7e0197b93617b9083f2bb9cc
https://github.com/llvm/llvm-project/commit/b293c8bfb6dd658c7e0197b93617b9083f2bb9cc
Author: Matthias Springer <me at m-sp.org>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
Log Message:
-----------
[mlir][TosaToLinalg] Ensure valid insertion pointer after op erasure (#146908)
Erasing/replacing an op, which is also the current insertion point,
invalidates the insertion point. Explicitly set the insertion point, so
that subsequent op insertions do not crash after the One-Shot Dialect
Conversion refactoring. (`ConversionPatternRewriter` will start behaving
more like a "normal" rewriter.)
Commit: 104c4263719055803436a8a4a54736fd52dbcdc5
https://github.com/llvm/llvm-project/commit/104c4263719055803436a8a4a54736fd52dbcdc5
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Log Message:
-----------
[AArch64] Remove an unused variable (NFC)
Commit: 6bcc38e6f8a7f224ec3138b55ba67238886f5243
https://github.com/llvm/llvm-project/commit/6bcc38e6f8a7f224ec3138b55ba67238886f5243
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
Log Message:
-----------
[FIX] Fix sanitizer-aarch64-linux build after commit 8472eb1361bbabd6… (#148206)
The previous commit 8472eb1361bbabd6428a65da446618503e439743 broke the
sanitizer-aarch64-linux builder.
This patch fixes it: unused variable is removed
Commit: 539991e33f1df194b6ca00039a1bab04b045f47b
https://github.com/llvm/llvm-project/commit/539991e33f1df194b6ca00039a1bab04b045f47b
Author: nerix <nero.9 at hotmail.de>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/MsvcStlSmartPointer.cpp
Log Message:
-----------
[LLDB] Use non synthetic value for MSVC smart ptr check (#148176)
I forgot to use the non-synthetic value to check for the `_Ptr` member.
Fixes the test failure from #147575.
---------
Co-authored-by: Michael Buch <michaelbuch12 at gmail.com>
Commit: 8eb6ef04e4dccf08e769c0ad772fdc78f86c2378
https://github.com/llvm/llvm-project/commit/8eb6ef04e4dccf08e769c0ad772fdc78f86c2378
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-07-11 (Fri, 11 Jul 2025)
Changed paths:
M .clang-tidy
M .github/workflows/pr-code-format.yml
M clang-tools-extra/clang-tidy/readability/NamedParameterCheck.cpp
M clang-tools-extra/clang-tidy/readability/NamedParameterCheck.h
M clang-tools-extra/clangd/ModulesBuilder.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/named-parameter.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/named-parameter.cpp
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/OpenMPClause.h
A clang/include/clang/Analysis/Analyses/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/UninitializedValues.h
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Format/Format.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/CMakeLists.txt
A clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/Analysis/UninitializedValues.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/C/C23/n3030.c
A clang/test/C/C23/n3030_1.c
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGen/bitfields_be.c
M clang/test/CIR/CodeGen/enum.cpp
M clang/test/CIR/CodeGen/namespace.cpp
M clang/test/CXX/basic/basic.link/p3.cpp
M clang/test/CXX/dcl.dcl/dcl.enum/p2.cpp
M clang/test/CXX/expr/expr.post/expr.static.cast/p3-0x.cpp
A clang/test/CodeGen/PowerPC/check-zero-vector.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
A clang/test/CodeGen/enum3.c
M clang/test/OpenMP/parallel_ast_print.cpp
A clang/test/OpenMP/parallel_message_messages.cpp
A clang/test/OpenMP/parallel_severity_messages.cpp
A clang/test/Sema/constant-builtins-vector.cpp
R clang/test/Sema/constant_builtins_vector.cpp
A clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/SemaCXX/concept-crash-on-diagnostic.cpp
M clang/test/SemaCXX/cxx1z-constexpr-lambdas.cpp
M clang/test/SemaCXX/enum-scoped.cpp
A clang/test/SemaCXX/uninitialized-multiple-uses.cpp
M clang/test/SemaCXX/warn-uninitialized-const-reference.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
R compiler-rt/lib/builtins/aarch64/emupac.cpp
M compiler-rt/lib/builtins/int_types.h
R compiler-rt/test/builtins/Unit/aarch64/emupac.c
M flang/docs/ReleaseNotes.md
M flang/examples/FeatureList/FeatureList.cpp
A flang/include/flang/Lower/OpenMP/Clauses.h
A flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/ClauseFinder.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
R flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/Decomposer.cpp
M flang/lib/Lower/OpenMP/Decomposer.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/lib/Lower/OpenMP/ReductionProcessor.cpp
R flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Lower/Support/Utils.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenACC/RegisterOpenACCExtensions.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/openmp-utils.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Fir/OpenACC/openacc-mappable.fir
M flang/test/Fir/OpenACC/openacc-type-categories-class.f90
M flang/test/Fir/OpenACC/openacc-type-categories.f90
M flang/test/Fir/do_concurrent.fir
M flang/test/Fir/invalid.fir
A flang/test/HLFIR/fir-reduction-alloca-block.fir
A flang/test/Lower/do_concurrent_reduce.f90
A flang/test/Lower/do_concurrent_reduce_allocatable.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops3.f90
M flang/test/Parser/OpenMP/allocators-unparse.f90
A flang/test/Semantics/OpenMP/allocators07.f90
A flang/test/Transforms/DoConcurrent/reduce_add.mlir
A flang/test/Transforms/DoConcurrent/reduce_all_regions.mlir
A flang/test/Transforms/DoConcurrent/reduce_local.mlir
M flang/test/Transforms/do_concurrent-to-do_loop-unodered.fir
M flang/test/lib/OpenACC/TestOpenACCInterfaces.cpp
M libc/include/llvm-libc-macros/wchar-macros.h
M libc/shared/math.h
A libc/shared/math/expf16.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/expf16.h
A libc/src/__support/math/expf16_utils.h
M libc/src/__support/str_to_float.h
M libc/src/__support/str_to_integer.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/expf16.cpp
M libc/src/math/generic/expxf16.h
M libc/test/src/math/smoke/RoundToIntegerTest.h
M lld/Common/DriverDispatcher.cpp
M lld/MinGW/Driver.cpp
M lld/test/MinGW/driver.test
M lldb/include/lldb/Breakpoint/Breakpoint.h
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/include/lldb/Breakpoint/BreakpointOptions.h
A lldb/include/lldb/Breakpoint/StopCondition.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/API/SBBreakpoint.cpp
M lldb/source/API/SBBreakpointLocation.cpp
M lldb/source/API/SBBreakpointName.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/Options.td
M lldb/source/Plugins/Language/CPlusPlus/CMakeLists.txt
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/Generic.cpp
M lldb/source/Plugins/Language/CPlusPlus/MsvcStl.h
A lldb/source/Plugins/Language/CPlusPlus/MsvcStlSmartPointer.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/test/API/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/iterator/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/iterator/TestDataFormatterStdIterator.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/iterator/main.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/shared_ptr/TestDataFormatterStdSharedPtr.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/iterator/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/iterator/TestDataFormatterLibccIterator.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/iterator/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/iterator/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/iterator/TestDataFormatterStdIterator.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/iterator/main.cpp
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
A lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
R lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_runInTerminal.py
M lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py
A lldb/test/Shell/Breakpoint/condition-lang.test
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/README.md
M lldb/tools/lldb-dap/package.json
M llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/Support/Endian.h
A llvm/include/llvm/Support/UniqueBBID.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/CodeGen/BasicBlockPathCloning.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPDInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/X86CallingConv.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
M llvm/test/Analysis/DependenceAnalysis/Coupled.ll
M llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
A llvm/test/CodeGen/AArch64/ldst_update_cfpath.mir
M llvm/test/CodeGen/AArch64/machine-combiner-maddimm.mir
M llvm/test/CodeGen/AArch64/madd-combiner.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-llrint.ll
M llvm/test/CodeGen/AArch64/sve-lrint.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
A llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
A llvm/test/CodeGen/ARM/min-max-combine.ll
A llvm/test/CodeGen/Hexagon/bitcast-i32-to-v32i1.ll
A llvm/test/CodeGen/Hexagon/bitcast-v2i16-to-v32i1.ll
A llvm/test/CodeGen/Hexagon/bitcast-v4i8-to-v32i1.ll
M llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep3.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep4.mir
M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep5.mir
A llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
A llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
M llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
A llvm/test/CodeGen/PowerPC/check-zero-vector.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/select-cond.ll
A llvm/test/CodeGen/RISCV/xqciac.ll
A llvm/test/CodeGen/RISCV/xqcics.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout-unknown-lanes.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll
M llvm/test/CodeGen/WebAssembly/simd-select.ll
M llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
R llvm/test/CodeGen/X86/fp128-abi.ll
R llvm/test/CodeGen/X86/i128-abi.ll
A llvm/test/CodeGen/X86/i128-fp128-abi.ll
M llvm/test/CodeGen/X86/inline-asm-fpstack.ll
M llvm/test/CodeGen/X86/isel-fcmp-x87.ll
M llvm/test/CodeGen/X86/long-double-abi-align.ll
M llvm/test/CodeGen/X86/pr78897.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/abs-vector.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd3.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vopd_features.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/AMDGPU/gfx9_asm_vop2_features.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vopd.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vopd3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_features.txt
M llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
A llvm/test/Transforms/InstCombine/icmp_or_umul_overflow.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/unittests/Support/EndianTest.cpp
M llvm/utils/TableGen/SearchableTableEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
M llvm/utils/gn/secondary/compiler-rt/test/builtins/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/TableGen/Class.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Dialect/GPU/CMakeLists.txt
A mlir/lib/Dialect/GPU/Transforms/XeVMAttachTarget.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/TableGen/Class.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/python/mlir/dialects/TransformTuneExtensionOps.td
M mlir/test/Dialect/LLVMIR/attach-targets.mlir
A mlir/test/Dialect/LLVMIR/cse-nvvm.mlir
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
A mlir/test/Target/LLVMIR/omptarget-debug-reduc-fn-loc.mlir
A mlir/test/Target/LLVMIR/openmp-cli-canonical_loop.mlir
A mlir/test/Target/LLVMIR/openmp-cli-unroll-heuristic01.mlir
A mlir/test/Target/LLVMIR/openmp-cli-unroll-heuristic02.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
M mlir/test/lib/Dialect/GPU/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M mlir/test/mlir-tblgen/attrdefs.td
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/config.bzl
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase, address comments
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/a9bc9786f12e...8eb6ef04e4dc
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list