[all-commits] [llvm/llvm-project] bbcebe: [DAG] Refactor X86 combineVSelectWithAllOnesOrZero...

[woruyu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bbcebec3af5ac473f5d3557683f18a79a4b12ab5
      https://github.com/llvm/llvm-project/commit/bbcebec3af5ac473f5d3557683f18a79a4b12ab5
  Author: woruyu <99597449+woruyu at users.noreply.github.com>
  Date:   2025-07-02 (Wed, 02 Jul 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-zip.ll
    M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
    M llvm/test/CodeGen/AArch64/concatbinop.ll
    M llvm/test/CodeGen/AArch64/sat-add.ll
    M llvm/test/CodeGen/AArch64/select_cc.ll
    M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/vselect-constants.ll
    M llvm/test/CodeGen/AArch64/vselect-ext.ll
    M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
    M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
    M llvm/test/CodeGen/LoongArch/lasx/xvmskcond.ll
    M llvm/test/CodeGen/LoongArch/lsx/vselect.ll
    M llvm/test/CodeGen/Mips/msa/compare_float.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll
    M llvm/test/CodeGen/PowerPC/sat-add.ll
    M llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll

  Log Message:
  -----------
  [DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (#145298)

This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -> andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) & x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>



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