[all-commits] [llvm/llvm-project] 887f38: [MLIR] Fix incorrect slice contiguity inference in...
Momchil Velikov via All-commits
all-commits at lists.llvm.org
Wed Jun 4 04:13:58 PDT 2025
Branch: refs/heads/users/momchil-velikov/memref-contig-slice
Home: https://github.com/llvm/llvm-project
Commit: 887f383aa07cca3fe023cd64b3b119cbf013c17b
https://github.com/llvm/llvm-project/commit/887f383aa07cca3fe023cd64b3b119cbf013c17b
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-06-04 (Wed, 04 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/test/Dialect/Vector/vector-transfer-flatten.mlir
Log Message:
-----------
[MLIR] Fix incorrect slice contiguity inference in `vector::isContiguousSlice`
Previously, slices were sometimes marked as non-contiguous when
they were actually contiguous. This occurred when the vector type had
leading unit dimensions, e.g., `vector<1x1x...x1xd0xd1x...xdn-1xT>``.
In such cases, only the trailing n dimensions of the memref need to be
contiguous, not the entire vector rank.
This affects how `FlattenContiguousRowMajorTransfer{Read,Write}Pattern`
flattens `transfer_read` and `transfer_write`` ops. The pattern used
to collapse a number of dimensions equal the vector rank, which
may be is incorrect when leading dimensions are unit-sized.
This patch fixes the issue by collapsing only as many trailing memref
dimensions as are actually contiguous.
Commit: 8ae1b9981882c48b1bedfb8a6617e4d764c1a836
https://github.com/llvm/llvm-project/commit/8ae1b9981882c48b1bedfb8a6617e4d764c1a836
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-06-04 (Wed, 04 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
Log Message:
-----------
[fixup] Don't try to collapse non-leftmost dynamic dimension
Even though it's possible in principle, the affected patterns need
strides to be determined statically.
Commit: c981866c6ea1e784606bb193da87c155716b2bbc
https://github.com/llvm/llvm-project/commit/c981866c6ea1e784606bb193da87c155716b2bbc
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-06-04 (Wed, 04 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-flatten.mlir
Log Message:
-----------
[fixup] Update a member functon name and fix a test failure
Compare: https://github.com/llvm/llvm-project/compare/efac66672f0f...c981866c6ea1
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