[all-commits] [llvm/llvm-project] efdaf0: [AMDGPU][SDAG] Add ISD::PTRADD DAG combines

[Fabian Ritter via All-commits]

  Branch: refs/heads/users/ritter-x2a/06-04-_amdgpu_sdag_add_isd_ptradd_dag_combines
  Home:   https://github.com/llvm/llvm-project
  Commit: efdaf03ba25edfd254a3b9bc79470ed861e123c1
      https://github.com/llvm/llvm-project/commit/efdaf03ba25edfd254a3b9bc79470ed861e123c1
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2025-06-04 (Wed, 04 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll

  Log Message:
  -----------
  [AMDGPU][SDAG] Add ISD::PTRADD DAG combines

This patch focuses on generic DAG combines, plus an AMDGPU-target-specific one
that is closely connected.

The generic DAG combine is based on a part of PR #105669 by @rgwott, which was
adapted from work by @jrtc27, @arichardson, @davidchisnall in the CHERI/Morello
LLVM tree. I added some parts and removed several disjuncts from the
reassociation condition:
- `isNullConstant(X)`, since there are address spaces where 0 is a perfectly
  normal value that shouldn't be treated specially,
- `(YIsConstant && ZOneUse)` and `(N0OneUse && ZOneUse && !ZIsConstant)`, since
  they cause regressions in AMDGPU.

For SWDEV-516125.



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