[all-commits] [llvm/llvm-project] 746c68: [LoongArch] Introduce `32s` target feature for LA3...

[hev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 746c682c4a8a6418fa7fca2c65176433135e6549
      https://github.com/llvm/llvm-project/commit/746c682c4a8a6418fa7fca2c65176433135e6549
  Author: hev <wangrui at loongson.cn>
  Date:   2025-05-20 (Tue, 20 May 2025)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArch.td
    M llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/test/CodeGen/LoongArch/alloca.ll
    M llvm/test/CodeGen/LoongArch/alsl.ll
    M llvm/test/CodeGen/LoongArch/annotate-tablejump.ll
    M llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll
    M llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/LoongArch/bitreverse.ll
    M llvm/test/CodeGen/LoongArch/bnez-beqz.ll
    M llvm/test/CodeGen/LoongArch/branch-relaxation.ll
    M llvm/test/CodeGen/LoongArch/bstrins_w.ll
    M llvm/test/CodeGen/LoongArch/bstrpick_w.ll
    M llvm/test/CodeGen/LoongArch/bswap-bitreverse.ll
    M llvm/test/CodeGen/LoongArch/bswap.ll
    M llvm/test/CodeGen/LoongArch/bytepick.ll
    M llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/LoongArch/ctpop-with-lsx.ll
    M llvm/test/CodeGen/LoongArch/exception-pointer-register.ll
    M llvm/test/CodeGen/LoongArch/fabs.ll
    M llvm/test/CodeGen/LoongArch/fcopysign.ll
    M llvm/test/CodeGen/LoongArch/feature-32bit.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-csr-side-effects.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/ashr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lam-bh.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/br.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-flt.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/load-store-fp.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/lshr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-int.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-int.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-int.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sext-zext-trunc.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/shl.ll
    M llvm/test/CodeGen/LoongArch/jump-table.ll
    M llvm/test/CodeGen/LoongArch/rotl-rotr.ll
    M llvm/test/CodeGen/LoongArch/select-to-shiftand.ll
    M llvm/test/CodeGen/LoongArch/shift-masked-shamt.ll
    M llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
    M llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/LoongArch/typepromotion-overflow.ll
    M llvm/test/MC/LoongArch/Basic/Integer/atomic.s
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.generated.expected
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.nogenerated.expected

  Log Message:
  -----------
  [LoongArch] Introduce `32s` target feature for LA32S ISA extensions (#139695)

According to the offical LoongArch reference manual, the 32-bit
LoongArch is divied into two variants: the Reduced version (LA32R) and
Standard version (LA32S). LA32S extends LA32R by adding additional
instructions, and the 64-bit version (LA64) fully includes the LA32S
instruction set.

This patch introduces a new target feature `32s` for the LoongArch
backend, enabling support for instructions specific to the LA32S
variant.

The LA32S exntension includes the following additional instructions:

- ALSL.W
- {AND,OR}N
- B{EQ,NE}Z
- BITREV.{4B,W}
- BSTR{INS,PICK}.W
- BYTEPICK.W
- CL{O,Z}.W
- CPUCFG
- CT{O,Z}.W
- EXT.W,{B,H}
- F{LD,ST}X.{D,S}
- MASK{EQ,NE}Z
- PC{ADDI,ALAU12I}
- REVB.2H
- ROTR{I},W

Additionally, LA32R defines three new instruction aliases:

- RDCNTID.W RJ => RDTIMEL.W ZERO, RJ
- RDCNTVH.W RD => RDTIMEH.W RD, ZERO
- RDCNTVL.W RD => RDTIMEL.W RD, ZERO



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