[all-commits] [llvm/llvm-project] 2bc9f4: [DAGCombiner] Fold pattern for srl-shl-zext (REAPP...

[Alexander Peskov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2bc9f43ba1116fb3989e28ecc3934209145a6250
      https://github.com/llvm/llvm-project/commit/2bc9f43ba1116fb3989e28ecc3934209145a6250
  Author: Alexander Peskov <apeskov at nvidia.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/NVPTX/shift-opt.ll

  Log Message:
  -----------
  [DAGCombiner] Fold pattern for srl-shl-zext (REAPPLIED) (#140038)

Fold (srl (lop x, (shl (zext y), c1)), c1) -> (lop (srl x, c1), (zext y)) where c1 <= leadingzeros(zext(y)).

This is equivalent of existing fold chain (srl (shl (zext y), c1), c1) -> (and (zext y), mask) -> (zext y), but logical op in the middle prevents it from combining.

Profit : Allow to reduce the number of instructions.

Original commit: #138290 / bbc5221

Previously reverted due to conflict in LIT test. Mainline changed
default version of load instruction to untyped version by this #137698 .
Updated test uses `ld.param.b64` instead of `ld.param.u64`.



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