[all-commits] [llvm/llvm-project] 540cf2: [RISCV] Split f64 loads/stores for RV32+Zdinx duri...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 540cf25a6df56fa1810a7411477dca9896aeed20
      https://github.com/llvm/llvm-project/commit/540cf25a6df56fa1810a7411477dca9896aeed20
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/test/CodeGen/RISCV/double-calling-conv.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-imm.ll
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/double-previous-failure.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
    M llvm/test/CodeGen/RISCV/zdinx-memoperand.ll

  Log Message:
  -----------
  [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)

This avoids a bunch of complexity around making sure the offset doesn't
exceed 4093 so we can add 4 after splitting later. By splitting early,
the split loads/stores will get selected independently.

There's a bit of follow up work to do, particularly around splitting a
constant pool load. Overall I think this is cleaner with less edge
cases.



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