[all-commits] [llvm/llvm-project] 426573: [RISCV] Use RISCVRegisterInfo::isRVVRegClass to re...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 426573332cb7c70ede293d13bac7564eb2c0b753
      https://github.com/llvm/llvm-project/commit/426573332cb7c70ede293d13bac7564eb2c0b753
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in storeRegToStackSlot/loadRegFromStackSlot. NFC (#139979)



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