[all-commits] [llvm/llvm-project] 28b7d6: [TableGen][CodeGen] Give every leaf register a uni...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 28b7d6621a70799705b04d2e08dc98a185151d3a
      https://github.com/llvm/llvm-project/commit/28b7d6621a70799705b04d2e08dc98a185151d3a
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2025-05-13 (Tue, 13 May 2025)

  Changed paths:
    A llvm/test/TableGen/SubRegsAndAliases.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][CodeGen] Give every leaf register a unique regunit (#139526)

Give every leaf register a unique regunit, even if it has ad hoc
aliases.

Previously only leaf registers *without* ad hoc aliases would get a
unique regunit, but that caused situations where regunits could not be
used to distinguish a register from its subregs. For example:

- Registers A and B alias. They both get regunit 0 only.
- Register C has subregs A and B. It inherits regunits from its subregs,
  so it also gets regunit 0 only.

After this fix, registers A and B will get a unique regunit in addition
to the regunit representing the alias, for example:

- A will get regunits 0 and 1.
- B will get regunits 0 and 2.
- C will get regunits 0, 1 and 2.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications