[all-commits] [llvm/llvm-project] 2ec13c: [AArch64][SVE] Add patterns for bit-select instruc...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ec13c513fb9de52abd7a3431151fd6bcf02a1c0
      https://github.com/llvm/llvm-project/commit/2ec13c513fb9de52abd7a3431151fd6bcf02a1c0
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve2-bsl.ll

  Log Message:
  -----------
  [AArch64][SVE] Add patterns for bit-select instructions. (#138689)

This patch adds patterns to select SVE2 bit-sel instructions such as BSL
from (or (and a, c), (and b, (vnot c)))) and other similar patterns. For
example:
```cpp
svuint64_t bsl(svuint64_t a, svuint64_t b, svuint64_t c) {
  return (a & c) | (b & ~c);
}
```
Currently:
```gas
bsl:
  and     z0.d, z2.d, z0.d
  bic     z1.d, z1.d, z2.d
  orr     z0.d, z0.d, z1.d
  ret
```
Becomes:
```gas
bsl:
  bsl     z0.d, z0.d, z1.d, z2.d
  ret
```



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