[all-commits] [llvm/llvm-project] af03d6: [AArch64][SVE] Refactor getPTrue to return splat(1...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af03d6b5186235620316640b58006b51301d316d
      https://github.com/llvm/llvm-project/commit/af03d6b5186235620316640b58006b51301d316d
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
    M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
    M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

  Log Message:
  -----------
  [AArch64][SVE] Refactor getPTrue to return splat(1) when pattern=all. (#139236)

Similarly to #135016, refactor getPTrue to return splat (1) for
all-active patterns. The main motivation for this is to improve
code gen for fixed-length vector loads/stores that are converted to SVE
masked memory ops when the vectors are wider than Neon. Emitting the
mask as a splat helps DAGCombiner simplify all-active masked
loads/stores into unmaked ones, for which it already has suitable
combines and ISel has suitable patterns.



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