[all-commits] [llvm/llvm-project] 8dc89e: [LLVM][InstCombine] Enable constant folding for SV...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8dc89e34199b6b1d0f5ea1f9940ccc8e957eef0a
      https://github.com/llvm/llvm-project/commit/8dc89e34199b6b1d0f5ea1f9940ccc8e957eef0a
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-04-30 (Wed, 30 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll

  Log Message:
  -----------
  [LLVM][InstCombine] Enable constant folding for SVE asr,lsl and lsr intrinsics. (#137350)

The SVE intrinsics support shift amounts greater-than-or-equal to the
element type's bit-length, essentially saturating the shift amount to
the bit-length. However, the IR instructions consider this undefined
behaviour that results in poison. To account for this we now ignore the
result of the simplifications that result in poison. This allows
existing code to be used to simplify the shifts but does mean:

1) We don't simplify cases like "svlsl_s32(x, splat(32)) => 0".
2) We no longer constant fold cases like "svadd(poison, X) => poison"

For (1) we'd need dedicated target specific combines anyway and the
result of (2) is not specified by the ACLE and replicating LLVM IR
behaviour might be confusing to ACLE writers.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications