[all-commits] [llvm/llvm-project] b9f1de: [TableGen] Combine the two separate OperandMapping...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9f1de04f65b062559d01c83dfd3948601924ee1
      https://github.com/llvm/llvm-project/commit/b9f1de04f65b062559d01c83dfd3948601924ee1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-16 (Wed, 16 Apr 2025)

  Changed paths:
    M llvm/utils/TableGen/PseudoLoweringEmitter.cpp

  Log Message:
  -----------
  [TableGen] Combine the two separate OperandMapping loops in PseudoLoweringEmitter. (#136007)

Previously we had one loop over the DAG for immediates and registers and
another loop over the destination operands for mapping from the source.

Now we have a single loop over the destination operands that handles immediates,
registers, and named operands. A helper method is added so we can handle
operands and sub-operands specified by a sub-dag.

My goal is to allow a named operand to appear in a sub-dag which wasn't
supported before. This will allow the destination instruction to have an
operand with sub-operands when the source does not have sub operands.

For RISC-V, I'm looking into using an operand with sub-operands to
represent an reg+offset memory address. I need to be able to lower a
pseudo instruction that only has a register operand to an instruction
that has a reg+offset operand. The offset will be filled in with 0
during expansion and the register will be copied from the source.

The expansion would look like this:
def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
                                [(riscv_call GPRJALR:$rs1)]>,
PseudoInstExpansion<(JALR X1, (ops GPR:$rs1, 0))>;



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